[llvm] [Xtensa] Implement sextload i8 (PR #106053)

[Andrei Safronov via llvm-commits]

https://github.com/andreisfr updated https://github.com/llvm/llvm-project/pull/106053

>From 68abaf1ec4e1c886ab7ceac318bc9aadbbb01eff Mon Sep 17 00:00:00 2001
From: Andrei Safronov <safronov at espressif.com>
Date: Mon, 26 Aug 2024 02:50:04 +0300
Subject: [PATCH 1/2] [Xtensa] Implement sextload i8.

---
 llvm/lib/Target/Xtensa/XtensaISelLowering.cpp |  3 ++-
 llvm/test/CodeGen/Xtensa/load.ll              | 13 +++++++++++++
 2 files changed, 15 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/Xtensa/load.ll

diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
index c7675c2f501761..0d2ce26a942e03 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -70,11 +70,12 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
   setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand);
 
-  // No sign extend instructions for i1
+  // No sign extend instructions for i1 and sign extend load i8
   for (MVT VT : MVT::integer_valuetypes()) {
     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
     setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
+    setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
   }
 
   setOperationAction(ISD::ConstantPool, PtrVT, Custom);
diff --git a/llvm/test/CodeGen/Xtensa/load.ll b/llvm/test/CodeGen/Xtensa/load.ll
new file mode 100644
index 00000000000000..94ab64340a5dad
--- /dev/null
+++ b/llvm/test/CodeGen/Xtensa/load.ll
@@ -0,0 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=xtensa < %s | FileCheck %s
+
+define signext i8 @test_load_i8(i32 noundef %0){
+; CHECK-LABEL: test_load_i8:
+; CHECK:         l8ui a8, a2, 0
+; CHECK-NEXT:    slli a8, a8, 24
+; CHECK-NEXT:    srai a2, a8, 24
+; CHECK-NEXT:    ret
+  %2 = inttoptr i32 %0 to ptr
+  %3 = load i8, ptr %2, align 1
+  ret i8 %3
+}

>From 625086efd19db5f28f7098c172037bf7635df9df Mon Sep 17 00:00:00 2001
From: Andrei Safronov <safronov at espressif.com>
Date: Mon, 26 Aug 2024 14:23:38 +0300
Subject: [PATCH 2/2] [Xtensa] Fix load test

---
 llvm/test/CodeGen/Xtensa/load.ll | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/llvm/test/CodeGen/Xtensa/load.ll b/llvm/test/CodeGen/Xtensa/load.ll
index 94ab64340a5dad..2f730f56eb1f51 100644
--- a/llvm/test/CodeGen/Xtensa/load.ll
+++ b/llvm/test/CodeGen/Xtensa/load.ll
@@ -1,13 +1,12 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc --mtriple=xtensa < %s | FileCheck %s
 
-define signext i8 @test_load_i8(i32 noundef %0){
+define signext i8 @test_load_i8(ptr %p){
 ; CHECK-LABEL: test_load_i8:
 ; CHECK:         l8ui a8, a2, 0
 ; CHECK-NEXT:    slli a8, a8, 24
 ; CHECK-NEXT:    srai a2, a8, 24
 ; CHECK-NEXT:    ret
-  %2 = inttoptr i32 %0 to ptr
-  %3 = load i8, ptr %2, align 1
-  ret i8 %3
+  %1 = load i8, ptr %p, align 1
+  ret i8 %1
 }