[llvm] [AArch64] Reland merge index address with large offset into base address (PR #79951)

via llvm-commits llvm-commits at lists.llvm.org
Mon Aug 26 04:07:18 PDT 2024


vfdff wrote:

* I find the root cause: it can only be reproduce when configure the build with **-DCMAKE_BUILD_TYPE=Release**, so I dump all the matched scenarios ,and find the Release version generate extra case compare to **-DCMAKE_BUILD_TYPE=RelWithDebInfo**, where **MOVZWi and MOVKWi** don't set the same registers, so should add checking to avoid this case.
  > CMAKE_COMMON_OPTIONS+=" -DLLVM_APPEND_VC_REV=OFF -GNinja -DCMAKE_BUILD_TYPE=Release"
```
Offset:  262160  Scale:  8
Creating base address load/store.
    Replacing instructions:
    renamable $w8 = MOVZWi 16, 0
    renamable $w11 = MOVKWi killed $w11(tied-def 0), 4, 16, implicit-def $x11
    renamable $x0 = LDRXroX renamable $x19, killed renamable $x11, 0, 0, debug-location !16303 :: (dereferenceable load (s64) from %ir.Subtarget163, !tbaa !1062); llvm-project/llvm/lib/Target/PowerPC/PPCISelLowering.cpp:5971:7
  with instruction:
    $x11 = ADDXri $x19, 64, 12, debug-location !16303; llvm-project/llvm/lib/Target/PowerPC/PPCISelLowering.cpp:5971:7
    renamable $x0 = LDRXui killed renamable $x11, 2, debug-location !16303 :: (dereferenceable load (s64) from %ir.Subtarget163, !tbaa !1062); llvm-project/llvm/lib/Target/PowerPC/PPCISelLowering.cpp:5971:7
```

https://github.com/llvm/llvm-project/pull/79951


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