[llvm] AMDGPU/NewPM: Port SIFoldOperands to new pass manager (PR #105801)
Akshat Oke via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 25 22:06:48 PDT 2024
https://github.com/Akshat-Oke updated https://github.com/llvm/llvm-project/pull/105801
>From 5ce183e3aed46e8cf06ff7372a09632f9a408330 Mon Sep 17 00:00:00 2001
From: Akshat Oke <Akshat.Oke at amd.com>
Date: Fri, 23 Aug 2024 07:02:03 +0000
Subject: [PATCH 1/4] AMDGPU/NewPM: Port SIFoldOperands to new pass manager
---
llvm/lib/Target/AMDGPU/AMDGPU.h | 6 +-
llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 1 +
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 7 +-
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 118 ++++++++++--------
llvm/lib/Target/AMDGPU/SIFoldOperands.h | 23 ++++
.../AMDGPU/constant-fold-imm-immreg.mir | 1 +
.../CodeGen/AMDGPU/flat-scratch-fold-fi.mir | 1 +
llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir | 3 +
.../CodeGen/AMDGPU/fold-cndmask-wave32.mir | 1 +
llvm/test/CodeGen/AMDGPU/fold-cndmask.mir | 1 +
llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir | 1 +
.../CodeGen/AMDGPU/fold-fi-operand-shrink.mir | 1 +
llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir | 1 +
...ld-immediate-operand-shrink-with-carry.mir | 1 +
.../AMDGPU/fold-immediate-operand-shrink.mir | 1 +
.../CodeGen/AMDGPU/fold-implicit-operand.mir | 1 +
.../CodeGen/AMDGPU/fold-multiple-commute.mir | 1 +
.../CodeGen/AMDGPU/fold-operands-order.mir | 1 +
.../AMDGPU/fold-operands-remove-m0-redef.mir | 1 +
.../AMDGPU/fold-operands-scalar-fmac.mir | 1 +
llvm/test/CodeGen/AMDGPU/fold-over-exec.mir | 1 +
llvm/test/CodeGen/AMDGPU/fold-readlane.mir | 1 +
llvm/test/CodeGen/AMDGPU/fold-sgpr-copy.mir | 1 +
.../AMDGPU/fold-short-64-bit-literals.mir | 2 +
llvm/test/CodeGen/AMDGPU/fold-vgpr-phyreg.mir | 1 +
.../fold-zero-high-bits-clear-kill-flags.mir | 1 +
.../CodeGen/AMDGPU/folding-of-i32-as-i64.mir | 1 +
.../AMDGPU/high-bits-zeroed-16-bit-ops.mir | 3 +
.../AMDGPU/huge-number-operand-folds.mir | 1 +
llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir | 1 +
.../CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir | 1 +
.../AMDGPU/pseudo-scalar-transcendental.mir | 1 +
.../CodeGen/AMDGPU/si-fold-aligned-agprs.mir | 1 +
.../CodeGen/AMDGPU/si-fold-aligned-vgprs.mir | 2 +
.../CodeGen/AMDGPU/si-fold-copy-kills.mir | 1 +
llvm/test/CodeGen/AMDGPU/si-fold-kimm.mir | 1 +
.../CodeGen/AMDGPU/si-fold-reg-sequence.mir | 1 +
.../CodeGen/AMDGPU/si-fold-scalar-clamp.mir | 1 +
.../CodeGen/AMDGPU/skip-fold-regsequence.mir | 1 +
llvm/test/CodeGen/AMDGPU/swdev282079.mir | 1 +
40 files changed, 141 insertions(+), 55 deletions(-)
create mode 100644 llvm/lib/Target/AMDGPU/SIFoldOperands.h
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index c50474893eb7d5..6eb641db076958 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -35,7 +35,7 @@ void initializeAMDGPURegBankSelectPass(PassRegistry &);
// SI Passes
FunctionPass *createGCNDPPCombinePass();
FunctionPass *createSIAnnotateControlFlowLegacyPass();
-FunctionPass *createSIFoldOperandsPass();
+FunctionPass *createSIFoldOperandsLegacyPass();
FunctionPass *createSIPeepholeSDWAPass();
FunctionPass *createSILowerI1CopiesLegacyPass();
FunctionPass *createAMDGPUGlobalISelDivergenceLoweringPass();
@@ -160,8 +160,8 @@ extern char &AMDGPURewriteOutArgumentsID;
void initializeGCNDPPCombinePass(PassRegistry &);
extern char &GCNDPPCombineID;
-void initializeSIFoldOperandsPass(PassRegistry &);
-extern char &SIFoldOperandsID;
+void initializeSIFoldOperandsLegacyPass(PassRegistry &);
+extern char &SIFoldOperandsLegacyID;
void initializeSIPeepholeSDWAPass(PassRegistry &);
extern char &SIPeepholeSDWAID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index d8741b4b06a984..10e394ed03df8f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -97,4 +97,5 @@ FUNCTION_PASS_WITH_PARAMS(
MACHINE_FUNCTION_PASS("amdgpu-isel", AMDGPUISelDAGToDAGPass(*this))
MACHINE_FUNCTION_PASS("si-fix-sgpr-copies", SIFixSGPRCopiesPass())
MACHINE_FUNCTION_PASS("si-i1-copies", SILowerI1CopiesPass())
+MACHINE_FUNCTION_PASS("si-fold-operands", SIFoldOperandsPass());
#undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 570f089e914699..81b0b0a03772d1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -34,6 +34,7 @@
#include "R600.h"
#include "R600TargetMachine.h"
#include "SIFixSGPRCopies.h"
+#include "SIFoldOperands.h"
#include "SIMachineFunctionInfo.h"
#include "SIMachineScheduler.h"
#include "TargetInfo/AMDGPUTargetInfo.h"
@@ -404,7 +405,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
initializeSILowerSGPRSpillsPass(*PR);
initializeSIFixSGPRCopiesLegacyPass(*PR);
initializeSIFixVGPRCopiesPass(*PR);
- initializeSIFoldOperandsPass(*PR);
+ initializeSIFoldOperandsLegacyPass(*PR);
initializeSIPeepholeSDWAPass(*PR);
initializeSIShrinkInstructionsPass(*PR);
initializeSIOptimizeExecMaskingPreRAPass(*PR);
@@ -1258,7 +1259,7 @@ void GCNPassConfig::addMachineSSAOptimization() {
// instructions leftover after the operands are folded as well.
//
// XXX - Can we get away without running DeadMachineInstructionElim again?
- addPass(&SIFoldOperandsID);
+ addPass(&SIFoldOperandsLegacyID);
if (EnableDPPCombine)
addPass(&GCNDPPCombineID);
addPass(&SILoadStoreOptimizerID);
@@ -1266,7 +1267,7 @@ void GCNPassConfig::addMachineSSAOptimization() {
addPass(&SIPeepholeSDWAID);
addPass(&EarlyMachineLICMID);
addPass(&MachineCSEID);
- addPass(&SIFoldOperandsID);
+ addPass(&SIFoldOperandsLegacyID);
}
addPass(&DeadMachineInstructionElimID);
addPass(createSIShrinkInstructionsPass());
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 875738dad74ced..7ed15f392a7d64 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -8,6 +8,7 @@
//===----------------------------------------------------------------------===//
//
+#include "SIFoldOperands.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
@@ -66,9 +67,8 @@ struct FoldCandidate {
bool needsShrink() const { return ShrinkOpcode != -1; }
};
-class SIFoldOperands : public MachineFunctionPass {
+class SIFoldOperandsImpl {
public:
- static char ID;
MachineRegisterInfo *MRI;
const SIInstrInfo *TII;
const SIRegisterInfo *TRI;
@@ -121,11 +121,23 @@ class SIFoldOperands : public MachineFunctionPass {
bool tryOptimizeAGPRPhis(MachineBasicBlock &MBB);
public:
- SIFoldOperands() : MachineFunctionPass(ID) {
- initializeSIFoldOperandsPass(*PassRegistry::getPassRegistry());
- }
+ SIFoldOperandsImpl() = default;
+
+ bool run(MachineFunction &MF);
+};
+
+class SIFoldOperandsLegacy : public MachineFunctionPass {
+public:
+ static char ID;
- bool runOnMachineFunction(MachineFunction &MF) override;
+ SIFoldOperandsLegacy() : MachineFunctionPass(ID) {}
+
+ bool runOnMachineFunction(MachineFunction &MF) override {
+ if (skipFunction(MF.getFunction()))
+ return false;
+ SIFoldOperandsImpl Impl;
+ return Impl.run(MF);
+ }
StringRef getPassName() const override { return "SI Fold Operands"; }
@@ -137,12 +149,12 @@ class SIFoldOperands : public MachineFunctionPass {
} // End anonymous namespace.
-INITIALIZE_PASS(SIFoldOperands, DEBUG_TYPE,
- "SI Fold Operands", false, false)
+INITIALIZE_PASS(SIFoldOperandsLegacy, DEBUG_TYPE, "SI Fold Operands", false,
+ false)
-char SIFoldOperands::ID = 0;
+char SIFoldOperandsLegacy::ID = 0;
-char &llvm::SIFoldOperandsID = SIFoldOperands::ID;
+char &llvm::SIFoldOperandsLegacyID = SIFoldOperandsLegacy::ID;
static const TargetRegisterClass *getRegOpRC(const MachineRegisterInfo &MRI,
const TargetRegisterInfo &TRI,
@@ -177,8 +189,8 @@ static unsigned macToMad(unsigned Opc) {
// TODO: Add heuristic that the frame index might not fit in the addressing mode
// immediate offset to avoid materializing in loops.
-bool SIFoldOperands::frameIndexMayFold(const MachineInstr &UseMI, int OpNo,
- const MachineOperand &OpToFold) const {
+bool SIFoldOperandsImpl::frameIndexMayFold(
+ const MachineInstr &UseMI, int OpNo, const MachineOperand &OpToFold) const {
if (!OpToFold.isFI())
return false;
@@ -196,11 +208,11 @@ bool SIFoldOperands::frameIndexMayFold(const MachineInstr &UseMI, int OpNo,
return OpNo == VIdx && SIdx == -1;
}
-FunctionPass *llvm::createSIFoldOperandsPass() {
- return new SIFoldOperands();
+FunctionPass *llvm::createSIFoldOperandsLegacyPass() {
+ return new SIFoldOperandsLegacy();
}
-bool SIFoldOperands::canUseImmWithOpSel(FoldCandidate &Fold) const {
+bool SIFoldOperandsImpl::canUseImmWithOpSel(FoldCandidate &Fold) const {
MachineInstr *MI = Fold.UseMI;
MachineOperand &Old = MI->getOperand(Fold.UseOpNo);
const uint64_t TSFlags = MI->getDesc().TSFlags;
@@ -230,7 +242,7 @@ bool SIFoldOperands::canUseImmWithOpSel(FoldCandidate &Fold) const {
return true;
}
-bool SIFoldOperands::tryFoldImmWithOpSel(FoldCandidate &Fold) const {
+bool SIFoldOperandsImpl::tryFoldImmWithOpSel(FoldCandidate &Fold) const {
MachineInstr *MI = Fold.UseMI;
MachineOperand &Old = MI->getOperand(Fold.UseOpNo);
unsigned Opcode = MI->getOpcode();
@@ -354,7 +366,7 @@ bool SIFoldOperands::tryFoldImmWithOpSel(FoldCandidate &Fold) const {
return false;
}
-bool SIFoldOperands::updateOperand(FoldCandidate &Fold) const {
+bool SIFoldOperandsImpl::updateOperand(FoldCandidate &Fold) const {
MachineInstr *MI = Fold.UseMI;
MachineOperand &Old = MI->getOperand(Fold.UseOpNo);
assert(Old.isReg());
@@ -464,9 +476,9 @@ static void appendFoldCandidate(SmallVectorImpl<FoldCandidate> &FoldList,
FoldList.emplace_back(MI, OpNo, FoldOp, Commuted, ShrinkOp);
}
-bool SIFoldOperands::tryAddToFoldList(SmallVectorImpl<FoldCandidate> &FoldList,
- MachineInstr *MI, unsigned OpNo,
- MachineOperand *OpToFold) const {
+bool SIFoldOperandsImpl::tryAddToFoldList(
+ SmallVectorImpl<FoldCandidate> &FoldList, MachineInstr *MI, unsigned OpNo,
+ MachineOperand *OpToFold) const {
const unsigned Opc = MI->getOpcode();
auto tryToFoldAsFMAAKorMK = [&]() {
@@ -645,8 +657,8 @@ bool SIFoldOperands::tryAddToFoldList(SmallVectorImpl<FoldCandidate> &FoldList,
return true;
}
-bool SIFoldOperands::isUseSafeToFold(const MachineInstr &MI,
- const MachineOperand &UseMO) const {
+bool SIFoldOperandsImpl::isUseSafeToFold(const MachineInstr &MI,
+ const MachineOperand &UseMO) const {
// Operands of SDWA instructions must be registers.
return !TII->isSDWA(MI);
}
@@ -654,7 +666,7 @@ bool SIFoldOperands::isUseSafeToFold(const MachineInstr &MI,
// Find a def of the UseReg, check if it is a reg_sequence and find initializers
// for each subreg, tracking it to foldable inline immediate if possible.
// Returns true on success.
-bool SIFoldOperands::getRegSeqInit(
+bool SIFoldOperandsImpl::getRegSeqInit(
SmallVectorImpl<std::pair<MachineOperand *, unsigned>> &Defs,
Register UseReg, uint8_t OpTy) const {
MachineInstr *Def = MRI->getVRegDef(UseReg);
@@ -686,7 +698,7 @@ bool SIFoldOperands::getRegSeqInit(
return true;
}
-bool SIFoldOperands::tryToFoldACImm(
+bool SIFoldOperandsImpl::tryToFoldACImm(
const MachineOperand &OpToFold, MachineInstr *UseMI, unsigned UseOpIdx,
SmallVectorImpl<FoldCandidate> &FoldList) const {
const MCInstrDesc &Desc = UseMI->getDesc();
@@ -752,12 +764,10 @@ bool SIFoldOperands::tryToFoldACImm(
return true;
}
-void SIFoldOperands::foldOperand(
- MachineOperand &OpToFold,
- MachineInstr *UseMI,
- int UseOpIdx,
- SmallVectorImpl<FoldCandidate> &FoldList,
- SmallVectorImpl<MachineInstr *> &CopiesToReplace) const {
+void SIFoldOperandsImpl::foldOperand(
+ MachineOperand &OpToFold, MachineInstr *UseMI, int UseOpIdx,
+ SmallVectorImpl<FoldCandidate> &FoldList,
+ SmallVectorImpl<MachineInstr *> &CopiesToReplace) const {
const MachineOperand *UseOp = &UseMI->getOperand(UseOpIdx);
if (!isUseSafeToFold(*UseMI, *UseOp))
@@ -1187,7 +1197,7 @@ static void mutateCopyOp(MachineInstr &MI, const MCInstrDesc &NewDesc) {
}
MachineOperand *
-SIFoldOperands::getImmOrMaterializedImm(MachineOperand &Op) const {
+SIFoldOperandsImpl::getImmOrMaterializedImm(MachineOperand &Op) const {
// If this has a subregister, it obviously is a register source.
if (!Op.isReg() || Op.getSubReg() != AMDGPU::NoSubRegister ||
!Op.getReg().isVirtual())
@@ -1206,7 +1216,7 @@ SIFoldOperands::getImmOrMaterializedImm(MachineOperand &Op) const {
// Try to simplify operations with a constant that may appear after instruction
// selection.
// TODO: See if a frame index with a fixed offset can fold.
-bool SIFoldOperands::tryConstantFoldOp(MachineInstr *MI) const {
+bool SIFoldOperandsImpl::tryConstantFoldOp(MachineInstr *MI) const {
if (!MI->allImplicitDefsAreDead())
return false;
@@ -1307,7 +1317,7 @@ bool SIFoldOperands::tryConstantFoldOp(MachineInstr *MI) const {
}
// Try to fold an instruction into a simpler one
-bool SIFoldOperands::tryFoldCndMask(MachineInstr &MI) const {
+bool SIFoldOperandsImpl::tryFoldCndMask(MachineInstr &MI) const {
unsigned Opc = MI.getOpcode();
if (Opc != AMDGPU::V_CNDMASK_B32_e32 && Opc != AMDGPU::V_CNDMASK_B32_e64 &&
Opc != AMDGPU::V_CNDMASK_B64_PSEUDO)
@@ -1346,7 +1356,7 @@ bool SIFoldOperands::tryFoldCndMask(MachineInstr &MI) const {
return true;
}
-bool SIFoldOperands::tryFoldZeroHighBits(MachineInstr &MI) const {
+bool SIFoldOperandsImpl::tryFoldZeroHighBits(MachineInstr &MI) const {
if (MI.getOpcode() != AMDGPU::V_AND_B32_e64 &&
MI.getOpcode() != AMDGPU::V_AND_B32_e32)
return false;
@@ -1368,8 +1378,8 @@ bool SIFoldOperands::tryFoldZeroHighBits(MachineInstr &MI) const {
return true;
}
-bool SIFoldOperands::foldInstOperand(MachineInstr &MI,
- MachineOperand &OpToFold) const {
+bool SIFoldOperandsImpl::foldInstOperand(MachineInstr &MI,
+ MachineOperand &OpToFold) const {
// We need mutate the operands of new mov instructions to add implicit
// uses of EXEC, but adding them invalidates the use_iterator, so defer
// this.
@@ -1442,7 +1452,7 @@ bool SIFoldOperands::foldInstOperand(MachineInstr &MI,
return true;
}
-bool SIFoldOperands::tryFoldFoldableCopy(
+bool SIFoldOperandsImpl::tryFoldFoldableCopy(
MachineInstr &MI, MachineOperand *&CurrentKnownM0Val) const {
// Specially track simple redefs of m0 to the same value in a block, so we
// can erase the later ones.
@@ -1519,7 +1529,8 @@ bool SIFoldOperands::tryFoldFoldableCopy(
// Clamp patterns are canonically selected to v_max_* instructions, so only
// handle them.
-const MachineOperand *SIFoldOperands::isClamp(const MachineInstr &MI) const {
+const MachineOperand *
+SIFoldOperandsImpl::isClamp(const MachineInstr &MI) const {
unsigned Op = MI.getOpcode();
switch (Op) {
case AMDGPU::V_MAX_F32_e64:
@@ -1567,7 +1578,7 @@ const MachineOperand *SIFoldOperands::isClamp(const MachineInstr &MI) const {
}
// FIXME: Clamp for v_mad_mixhi_f16 handled during isel.
-bool SIFoldOperands::tryFoldClamp(MachineInstr &MI) {
+bool SIFoldOperandsImpl::tryFoldClamp(MachineInstr &MI) {
const MachineOperand *ClampSrc = isClamp(MI);
if (!ClampSrc || !MRI->hasOneNonDBGUser(ClampSrc->getReg()))
return false;
@@ -1662,7 +1673,7 @@ static int getOModValue(unsigned Opc, int64_t Val) {
// FIXME: Does this need to check IEEE mode bit? SNaNs are generally not
// handled, so will anything other than that break?
std::pair<const MachineOperand *, int>
-SIFoldOperands::isOMod(const MachineInstr &MI) const {
+SIFoldOperandsImpl::isOMod(const MachineInstr &MI) const {
unsigned Op = MI.getOpcode();
switch (Op) {
case AMDGPU::V_MUL_F64_e64:
@@ -1740,7 +1751,7 @@ SIFoldOperands::isOMod(const MachineInstr &MI) const {
}
// FIXME: Does this need to check IEEE bit on function?
-bool SIFoldOperands::tryFoldOMod(MachineInstr &MI) {
+bool SIFoldOperandsImpl::tryFoldOMod(MachineInstr &MI) {
const MachineOperand *RegOp;
int OMod;
std::tie(RegOp, OMod) = isOMod(MI);
@@ -1779,7 +1790,7 @@ bool SIFoldOperands::tryFoldOMod(MachineInstr &MI) {
// Try to fold a reg_sequence with vgpr output and agpr inputs into an
// instruction which can take an agpr. So far that means a store.
-bool SIFoldOperands::tryFoldRegSequence(MachineInstr &MI) {
+bool SIFoldOperandsImpl::tryFoldRegSequence(MachineInstr &MI) {
assert(MI.isRegSequence());
auto Reg = MI.getOperand(0).getReg();
@@ -1926,7 +1937,7 @@ static bool isAGPRCopy(const SIRegisterInfo &TRI,
// loop:
// %3:areg = PHI %2:areg, %entry, %X:areg,
// %4:areg = (instr using %3:areg)
-bool SIFoldOperands::tryFoldPhiAGPR(MachineInstr &PHI) {
+bool SIFoldOperandsImpl::tryFoldPhiAGPR(MachineInstr &PHI) {
assert(PHI.isPHI());
Register PhiOut = PHI.getOperand(0).getReg();
@@ -2030,7 +2041,7 @@ bool SIFoldOperands::tryFoldPhiAGPR(MachineInstr &PHI) {
}
// Attempt to convert VGPR load to an AGPR load.
-bool SIFoldOperands::tryFoldLoad(MachineInstr &MI) {
+bool SIFoldOperandsImpl::tryFoldLoad(MachineInstr &MI) {
assert(MI.mayLoad());
if (!ST->hasGFX90AInsts() || MI.getNumExplicitDefs() != 1)
return false;
@@ -2117,7 +2128,7 @@ bool SIFoldOperands::tryFoldLoad(MachineInstr &MI) {
// %0:areg = PHI %tmp_agpr, %a, %x, %c
// %1:areg = PHI %tmp_agpr, %a, %y, %c
// %2:areg = PHI %tmp_agpr, %a, %z, %c
-bool SIFoldOperands::tryOptimizeAGPRPhis(MachineBasicBlock &MBB) {
+bool SIFoldOperandsImpl::tryOptimizeAGPRPhis(MachineBasicBlock &MBB) {
// This is only really needed on GFX908 where AGPR-AGPR copies are
// unreasonably difficult.
if (ST->hasGFX90AInsts())
@@ -2182,10 +2193,7 @@ bool SIFoldOperands::tryOptimizeAGPRPhis(MachineBasicBlock &MBB) {
return Changed;
}
-bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
- if (skipFunction(MF.getFunction()))
- return false;
-
+bool SIFoldOperandsImpl::run(MachineFunction &MF) {
MRI = &MF.getRegInfo();
ST = &MF.getSubtarget<GCNSubtarget>();
TII = ST->getInstrInfo();
@@ -2246,3 +2254,15 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
return Changed;
}
+
+PreservedAnalyses SIFoldOperandsPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &) {
+ SIFoldOperandsImpl Impl;
+ bool Changed = Impl.run(MF);
+ if (!Changed) {
+ return PreservedAnalyses::all();
+ }
+ PreservedAnalyses PA;
+ PA.preserveSet<CFGAnalyses>();
+ return PA;
+}
\ No newline at end of file
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.h b/llvm/lib/Target/AMDGPU/SIFoldOperands.h
new file mode 100644
index 00000000000000..8ece17d586fe87
--- /dev/null
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.h
@@ -0,0 +1,23 @@
+//===- SIFoldOperands.h -----------------------------------------*- C++- *-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AMDGPU_SIFOLDOPERANDS_H
+#define LLVM_LIB_TARGET_AMDGPU_SIFOLDOPERANDS_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+class SIFoldOperandsPass : public PassInfoMixin<SIFoldOperandsPass> {
+public:
+ SIFoldOperandsPass() = default;
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
+} // namespace llvm
+
+#endif
\ No newline at end of file
diff --git a/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir b/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
index 3db2b6ed9ab4ba..e5c7da6ee98fcc 100644
--- a/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination -o - %s | FileCheck -enable-var-scope -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs -passes si-fold-operands,dead-mi-elimination -o - %s | FileCheck -enable-var-scope -check-prefix=GCN %s
...
# GCN-LABEL: name: s_fold_and_imm_regimm_32{{$}}
diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir b/llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir
index 32c594c796912f..aa34cf8a37fd4d 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir
+++ b/llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+enable-flat-scratch -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+enable-flat-scratch -passes=si-fold-operands -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
---
name: test_fold_fi_scratch_load_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir b/llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir
index e94546fd5e8a51..4ccafe0b2b5664 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir
@@ -3,6 +3,9 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck %s --check-prefixes=GFX90A
# RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck %s --check-prefixes=GFX90A
+# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -passes si-fold-operands %s -o - | FileCheck %s --check-prefixes=GFX908
+# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -passes si-fold-operands %s -o - | FileCheck %s --check-prefixes=GFX90A
+# RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs -passes si-fold-operands %s -o - | FileCheck %s --check-prefixes=GFX90A
---
name: test_sgpr_init_multiuse
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/AMDGPU/fold-cndmask-wave32.mir b/llvm/test/CodeGen/AMDGPU/fold-cndmask-wave32.mir
index dd3c798dcbcfc4..28e44080de1b5e 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-cndmask-wave32.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-cndmask-wave32.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -run-pass si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -passes si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s
---
name: fold_cndmask
diff --git a/llvm/test/CodeGen/AMDGPU/fold-cndmask.mir b/llvm/test/CodeGen/AMDGPU/fold-cndmask.mir
index 4b84c0ec56f4d7..9b8bb428b01344 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-cndmask.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-cndmask.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn -run-pass si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -passes si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s
# CHECK: %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
# CHECK: %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir b/llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir
index dcd64f58db201a..f11ec3dfbf3794 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -passes si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s
# Kernels can have no FP
---
diff --git a/llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir b/llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir
index 2b5ec86244ec2a..c0808a8a62d11e 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -passes si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s
---
diff --git a/llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir b/llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
index 5d68c3135a0263..9f25266ff0814e 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn -run-pass si-fold-operands -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -passes si-fold-operands -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# GCN-LABEL: name: fold-imm-copy
# GCN: V_AND_B32_e32 65535
diff --git a/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir b/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir
index fc2d4807f72d42..3c4fe1109f1c04 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -passes si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s
---
diff --git a/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir b/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir
index 2bf0ceaa568185..c561e4ec79592c 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -passes si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s
---
diff --git a/llvm/test/CodeGen/AMDGPU/fold-implicit-operand.mir b/llvm/test/CodeGen/AMDGPU/fold-implicit-operand.mir
index b8abc3b2e08873..282a754efb809d 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-implicit-operand.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-implicit-operand.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn -run-pass si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -passes si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s
---
# Make sure there is no crash when trying to fold an immediate into an
# implicit use
diff --git a/llvm/test/CodeGen/AMDGPU/fold-multiple-commute.mir b/llvm/test/CodeGen/AMDGPU/fold-multiple-commute.mir
index e9c0e50e579824..88a9b4bddb98fb 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-multiple-commute.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-multiple-commute.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -passes si-fold-operands %s -o - | FileCheck %s
# Check that the addc instructions are commuted to allow folding of the constant
# 0 into multiple uses as an inline operand.
diff --git a/llvm/test/CodeGen/AMDGPU/fold-operands-order.mir b/llvm/test/CodeGen/AMDGPU/fold-operands-order.mir
index b23faff507e320..2d329114e84b75 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-operands-order.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-operands-order.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=hawaii -verify-machineinstrs -run-pass si-fold-operands -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=hawaii -verify-machineinstrs -passes si-fold-operands -o - %s | FileCheck -check-prefix=GCN %s
...
---
diff --git a/llvm/test/CodeGen/AMDGPU/fold-operands-remove-m0-redef.mir b/llvm/test/CodeGen/AMDGPU/fold-operands-remove-m0-redef.mir
index 5bb34792ecaa97..9ffd39d429d097 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-operands-remove-m0-redef.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-operands-remove-m0-redef.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass=si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs -passes=si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s
--- |
define amdgpu_kernel void @redef_m0_same_copy() { ret void }
diff --git a/llvm/test/CodeGen/AMDGPU/fold-operands-scalar-fmac.mir b/llvm/test/CodeGen/AMDGPU/fold-operands-scalar-fmac.mir
index 08693ec9db1d4b..9dbdd89b282c90 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-operands-scalar-fmac.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-operands-scalar-fmac.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -verify-machineinstrs -run-pass=si-fold-operands %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -verify-machineinstrs -passes=si-fold-operands %s -o - | FileCheck %s
---
name: fmac_fold_inlinable_src0_to_fmamk
diff --git a/llvm/test/CodeGen/AMDGPU/fold-over-exec.mir b/llvm/test/CodeGen/AMDGPU/fold-over-exec.mir
index 9cc6c257b029d1..c1397e77faf73b 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-over-exec.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-over-exec.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs -passes si-fold-operands %s -o - | FileCheck %s
# CHECK-LABEL: bb.2:
# CHECK: %I_out
diff --git a/llvm/test/CodeGen/AMDGPU/fold-readlane.mir b/llvm/test/CodeGen/AMDGPU/fold-readlane.mir
index 099b066cde255e..440bf8d9bc9598 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-readlane.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-readlane.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn -run-pass si-fold-operands -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -passes si-fold-operands -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# GCN-LABEL: name: fold-imm-readfirstlane{{$}}
# GCN: %1:sreg_32_xm0 = S_MOV_B32 123
diff --git a/llvm/test/CodeGen/AMDGPU/fold-sgpr-copy.mir b/llvm/test/CodeGen/AMDGPU/fold-sgpr-copy.mir
index 103c3e3eb8bc64..5e124cb21da6b2 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-sgpr-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-sgpr-copy.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=si-fold-operands,dead-mi-elimination -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes=si-fold-operands,dead-mi-elimination -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
---
diff --git a/llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir b/llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir
index 1f15066264c743..426886df8c0464 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir
@@ -1,5 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass=si-fold-operands -o - %s | FileCheck --check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -passes=si-fold-operands -o - %s | FileCheck --check-prefix=GCN %s
+
---
name: no_fold_fp_64bit_literal_sgpr
diff --git a/llvm/test/CodeGen/AMDGPU/fold-vgpr-phyreg.mir b/llvm/test/CodeGen/AMDGPU/fold-vgpr-phyreg.mir
index 2d5909e3297d2e..264b52039267f4 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-vgpr-phyreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-vgpr-phyreg.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-fold-operands -verify-machineinstrs | FileCheck %s
+# RUN: llc -o - %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -passes=si-fold-operands -verify-machineinstrs | FileCheck %s
---
name: lshl_add_u64_gep
diff --git a/llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-clear-kill-flags.mir b/llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-clear-kill-flags.mir
index baaca76bfd8a89..e31ae4ae397ec2 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-clear-kill-flags.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-clear-kill-flags.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx940 -verify-machineinstrs -run-pass si-fold-operands -o - %s | FileCheck -enable-var-scope -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx940 -verify-machineinstrs -passes si-fold-operands -o - %s | FileCheck -enable-var-scope -check-prefix=GCN %s
---
name: fold_zero_high_bits_src1_alive
diff --git a/llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir b/llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir
index bd1164fe30f3f5..518e14dedafe47 100644
--- a/llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir
+++ b/llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-fold-operands -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -passes=si-fold-operands -o - %s | FileCheck -check-prefix=GCN %s
# The constant is 0xffffffff80000000. It is 64-bit negative constant, but it passes the test
# isInt<32>(). Nonetheless it is not a legal literal for a binary or unsigned operand and
diff --git a/llvm/test/CodeGen/AMDGPU/high-bits-zeroed-16-bit-ops.mir b/llvm/test/CodeGen/AMDGPU/high-bits-zeroed-16-bit-ops.mir
index 5596eceb95d056..2d608a2dc4201c 100644
--- a/llvm/test/CodeGen/AMDGPU/high-bits-zeroed-16-bit-ops.mir
+++ b/llvm/test/CodeGen/AMDGPU/high-bits-zeroed-16-bit-ops.mir
@@ -3,6 +3,9 @@
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -run-pass=si-fold-operands -o - %s | FileCheck -check-prefix=GFX9 %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -run-pass=si-fold-operands -o - %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -passes=si-fold-operands -o - %s | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -passes=si-fold-operands -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -passes=si-fold-operands -o - %s | FileCheck -check-prefix=GFX10 %s
# Test we recognize all forms of and with mask as clearing the high bits.
---
name: v_cvt_f16_f32_altmask
diff --git a/llvm/test/CodeGen/AMDGPU/huge-number-operand-folds.mir b/llvm/test/CodeGen/AMDGPU/huge-number-operand-folds.mir
index 98e191a4bf2a3e..39dffc4d87c62d 100644
--- a/llvm/test/CodeGen/AMDGPU/huge-number-operand-folds.mir
+++ b/llvm/test/CodeGen/AMDGPU/huge-number-operand-folds.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -passes=si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s
# We were storing fold candidate uses in an unsigned char, which this exceeds.
# The use operand overflows and the expected register operand hits the immediate 0.
diff --git a/llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir b/llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
index 91950bffd9df4a..5ca2c472965bc7 100644
--- a/llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
+++ b/llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs -passes si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s
---
diff --git a/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir b/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
index 748775dc2cf1d5..65bdb4bb9511f7 100644
--- a/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -run-pass si-fix-sgpr-copies,si-fold-operands,dead-mi-elimination -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -passes si-fix-sgpr-copies,si-fold-operands,dead-mi-elimination -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
# Check that constant is in SGPR registers
diff --git a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
index 17bed38bd046d7..e0e99bb571bf70 100644
--- a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
+++ b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -passes=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
# Do not use inline constants for f16 pseudo scalar transcendentals.
# But allow literal constants.
diff --git a/llvm/test/CodeGen/AMDGPU/si-fold-aligned-agprs.mir b/llvm/test/CodeGen/AMDGPU/si-fold-aligned-agprs.mir
index a0ea04b1b9c0f9..b18d9a6d0519c7 100644
--- a/llvm/test/CodeGen/AMDGPU/si-fold-aligned-agprs.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-fold-aligned-agprs.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GFX90A %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -passes=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GFX90A %s
# Should fold only the aligned agpr copies with their uses.
diff --git a/llvm/test/CodeGen/AMDGPU/si-fold-aligned-vgprs.mir b/llvm/test/CodeGen/AMDGPU/si-fold-aligned-vgprs.mir
index a54c0accce7834..2ceb1cb3c94441 100644
--- a/llvm/test/CodeGen/AMDGPU/si-fold-aligned-vgprs.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-fold-aligned-vgprs.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GFX908 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -passes=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GFX908 %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GFX90A %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -passes=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GFX90A %s
# Should fold all copies for gfx908. In case of gfx90a, the folding must happen only for the aligned cases.
diff --git a/llvm/test/CodeGen/AMDGPU/si-fold-copy-kills.mir b/llvm/test/CodeGen/AMDGPU/si-fold-copy-kills.mir
index 89f8fb8dae6158..e97657e6fb1b2c 100644
--- a/llvm/test/CodeGen/AMDGPU/si-fold-copy-kills.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-fold-copy-kills.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
---
name: fold_reg_kill
diff --git a/llvm/test/CodeGen/AMDGPU/si-fold-kimm.mir b/llvm/test/CodeGen/AMDGPU/si-fold-kimm.mir
index cfff5e621be535..d55b79e1365455 100644
--- a/llvm/test/CodeGen/AMDGPU/si-fold-kimm.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-fold-kimm.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -passes=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
# Do not fold noninlinable constants in instructions like fmaak and fmamk next
# to kimm16 and kimm32 operands
diff --git a/llvm/test/CodeGen/AMDGPU/si-fold-reg-sequence.mir b/llvm/test/CodeGen/AMDGPU/si-fold-reg-sequence.mir
index 7852f5d0c96f55..9db09ec97ca4d4 100644
--- a/llvm/test/CodeGen/AMDGPU/si-fold-reg-sequence.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-fold-reg-sequence.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=si-fold-operands -verify-machineinstrs -o - %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=si-fold-operands -verify-machineinstrs -o - %s
---
name: fold_reg_sequence
diff --git a/llvm/test/CodeGen/AMDGPU/si-fold-scalar-clamp.mir b/llvm/test/CodeGen/AMDGPU/si-fold-scalar-clamp.mir
index 1f4d046a8739fa..381831ee9b2b4f 100644
--- a/llvm/test/CodeGen/AMDGPU/si-fold-scalar-clamp.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-fold-scalar-clamp.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -passes=si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s
---
name: test
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/AMDGPU/skip-fold-regsequence.mir b/llvm/test/CodeGen/AMDGPU/skip-fold-regsequence.mir
index 4803566441483d..0ea7618df306e9 100644
--- a/llvm/test/CodeGen/AMDGPU/skip-fold-regsequence.mir
+++ b/llvm/test/CodeGen/AMDGPU/skip-fold-regsequence.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass si-fold-operands -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -passes si-fold-operands -o - %s | FileCheck -check-prefix=GCN %s
# Skip folding a REG_SEQUENCE to its user when the regclasses for the user operands can't be
# fully determined from the instruction description.
diff --git a/llvm/test/CodeGen/AMDGPU/swdev282079.mir b/llvm/test/CodeGen/AMDGPU/swdev282079.mir
index e5a9dcb65f7b21..530b41221d1fba 100644
--- a/llvm/test/CodeGen/AMDGPU/swdev282079.mir
+++ b/llvm/test/CodeGen/AMDGPU/swdev282079.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-fold-operands -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -passes=si-fold-operands -o - %s | FileCheck %s
# This was attempting to look back through the REG_SEQUENCE source
# operands and trying to look for physreg defs.
>From bcbe75b0b52c11df616411839778f9a3606f312b Mon Sep 17 00:00:00 2001
From: Akshat Oke <Akshat.Oke at amd.com>
Date: Fri, 23 Aug 2024 11:39:17 +0000
Subject: [PATCH 2/4] Update for comments
---
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 2 +-
llvm/lib/Target/AMDGPU/SIFoldOperands.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 7ed15f392a7d64..9c31966a5b8e97 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -2262,7 +2262,7 @@ PreservedAnalyses SIFoldOperandsPass::run(MachineFunction &MF,
if (!Changed) {
return PreservedAnalyses::all();
}
- PreservedAnalyses PA;
+ auto PA = getMachineFunctionPassPreservedAnalyses();
PA.preserveSet<CFGAnalyses>();
return PA;
}
\ No newline at end of file
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.h b/llvm/lib/Target/AMDGPU/SIFoldOperands.h
index 8ece17d586fe87..3cc62fde4847fa 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.h
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.h
@@ -12,7 +12,7 @@
#include "llvm/CodeGen/MachinePassManager.h"
namespace llvm {
-class SIFoldOperandsPass : public PassInfoMixin<SIFoldOperandsPass> {
+class SIFoldOperandsPass : public MachinePassInfoMixin<SIFoldOperandsPass> {
public:
SIFoldOperandsPass() = default;
PreservedAnalyses run(MachineFunction &MF,
>From e0279c6d013b64e08d621a54ccb5481e3295765a Mon Sep 17 00:00:00 2001
From: Akshat Oke <Akshat.Oke at amd.com>
Date: Mon, 26 Aug 2024 04:14:20 +0000
Subject: [PATCH 3/4] Update tests and newlines
---
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 2 +-
llvm/lib/Target/AMDGPU/SIFoldOperands.h | 2 +-
llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir | 1 -
llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir | 1 -
llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir | 3 ---
llvm/test/CodeGen/AMDGPU/fold-cndmask-wave32.mir | 1 -
llvm/test/CodeGen/AMDGPU/fold-cndmask.mir | 1 -
llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir | 1 -
llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir | 1 -
llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir | 1 -
.../AMDGPU/fold-immediate-operand-shrink-with-carry.mir | 1 -
llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir | 1 -
llvm/test/CodeGen/AMDGPU/fold-implicit-operand.mir | 1 -
llvm/test/CodeGen/AMDGPU/fold-multiple-commute.mir | 1 -
llvm/test/CodeGen/AMDGPU/fold-operands-order.mir | 1 -
llvm/test/CodeGen/AMDGPU/fold-operands-remove-m0-redef.mir | 1 -
llvm/test/CodeGen/AMDGPU/fold-operands-scalar-fmac.mir | 1 -
llvm/test/CodeGen/AMDGPU/fold-over-exec.mir | 1 -
llvm/test/CodeGen/AMDGPU/fold-readlane.mir | 1 -
llvm/test/CodeGen/AMDGPU/fold-sgpr-copy.mir | 1 -
llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir | 2 --
llvm/test/CodeGen/AMDGPU/fold-vgpr-phyreg.mir | 1 -
.../CodeGen/AMDGPU/fold-zero-high-bits-clear-kill-flags.mir | 1 -
llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir | 1 -
llvm/test/CodeGen/AMDGPU/high-bits-zeroed-16-bit-ops.mir | 3 ---
llvm/test/CodeGen/AMDGPU/huge-number-operand-folds.mir | 1 -
llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir | 1 -
llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir | 1 -
llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir | 1 -
llvm/test/CodeGen/AMDGPU/si-fold-aligned-agprs.mir | 1 -
llvm/test/CodeGen/AMDGPU/si-fold-aligned-vgprs.mir | 2 --
llvm/test/CodeGen/AMDGPU/si-fold-copy-kills.mir | 1 -
llvm/test/CodeGen/AMDGPU/si-fold-kimm.mir | 1 -
llvm/test/CodeGen/AMDGPU/si-fold-reg-sequence.mir | 1 -
llvm/test/CodeGen/AMDGPU/swdev282079.mir | 1 -
35 files changed, 2 insertions(+), 41 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 9c31966a5b8e97..8131851e9a2c5c 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -2265,4 +2265,4 @@ PreservedAnalyses SIFoldOperandsPass::run(MachineFunction &MF,
auto PA = getMachineFunctionPassPreservedAnalyses();
PA.preserveSet<CFGAnalyses>();
return PA;
-}
\ No newline at end of file
+}
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.h b/llvm/lib/Target/AMDGPU/SIFoldOperands.h
index 3cc62fde4847fa..8ad8057c2f0f7a 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.h
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.h
@@ -20,4 +20,4 @@ class SIFoldOperandsPass : public MachinePassInfoMixin<SIFoldOperandsPass> {
};
} // namespace llvm
-#endif
\ No newline at end of file
+#endif
diff --git a/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir b/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
index e5c7da6ee98fcc..3db2b6ed9ab4ba 100644
--- a/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
@@ -1,5 +1,4 @@
# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination -o - %s | FileCheck -enable-var-scope -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs -passes si-fold-operands,dead-mi-elimination -o - %s | FileCheck -enable-var-scope -check-prefix=GCN %s
...
# GCN-LABEL: name: s_fold_and_imm_regimm_32{{$}}
diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir b/llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir
index aa34cf8a37fd4d..32c594c796912f 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir
+++ b/llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+enable-flat-scratch -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+enable-flat-scratch -passes=si-fold-operands -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
---
name: test_fold_fi_scratch_load_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir b/llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir
index 4ccafe0b2b5664..e94546fd5e8a51 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir
@@ -3,9 +3,6 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck %s --check-prefixes=GFX90A
# RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck %s --check-prefixes=GFX90A
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -passes si-fold-operands %s -o - | FileCheck %s --check-prefixes=GFX908
-# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -passes si-fold-operands %s -o - | FileCheck %s --check-prefixes=GFX90A
-# RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs -passes si-fold-operands %s -o - | FileCheck %s --check-prefixes=GFX90A
---
name: test_sgpr_init_multiuse
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/AMDGPU/fold-cndmask-wave32.mir b/llvm/test/CodeGen/AMDGPU/fold-cndmask-wave32.mir
index 28e44080de1b5e..dd3c798dcbcfc4 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-cndmask-wave32.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-cndmask-wave32.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -run-pass si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -passes si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s
---
name: fold_cndmask
diff --git a/llvm/test/CodeGen/AMDGPU/fold-cndmask.mir b/llvm/test/CodeGen/AMDGPU/fold-cndmask.mir
index 9b8bb428b01344..4b84c0ec56f4d7 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-cndmask.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-cndmask.mir
@@ -1,5 +1,4 @@
# RUN: llc -mtriple=amdgcn -run-pass si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn -passes si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s
# CHECK: %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
# CHECK: %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir b/llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir
index f11ec3dfbf3794..dcd64f58db201a 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -passes si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s
# Kernels can have no FP
---
diff --git a/llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir b/llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir
index c0808a8a62d11e..2b5ec86244ec2a 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -passes si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s
---
diff --git a/llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir b/llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
index 9f25266ff0814e..5d68c3135a0263 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
@@ -1,5 +1,4 @@
# RUN: llc -mtriple=amdgcn -run-pass si-fold-operands -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn -passes si-fold-operands -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# GCN-LABEL: name: fold-imm-copy
# GCN: V_AND_B32_e32 65535
diff --git a/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir b/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir
index 3c4fe1109f1c04..fc2d4807f72d42 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -passes si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s
---
diff --git a/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir b/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir
index c561e4ec79592c..2bf0ceaa568185 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -passes si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s
---
diff --git a/llvm/test/CodeGen/AMDGPU/fold-implicit-operand.mir b/llvm/test/CodeGen/AMDGPU/fold-implicit-operand.mir
index 282a754efb809d..b8abc3b2e08873 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-implicit-operand.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-implicit-operand.mir
@@ -1,5 +1,4 @@
# RUN: llc -mtriple=amdgcn -run-pass si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn -passes si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s
---
# Make sure there is no crash when trying to fold an immediate into an
# implicit use
diff --git a/llvm/test/CodeGen/AMDGPU/fold-multiple-commute.mir b/llvm/test/CodeGen/AMDGPU/fold-multiple-commute.mir
index 88a9b4bddb98fb..e9c0e50e579824 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-multiple-commute.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-multiple-commute.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -passes si-fold-operands %s -o - | FileCheck %s
# Check that the addc instructions are commuted to allow folding of the constant
# 0 into multiple uses as an inline operand.
diff --git a/llvm/test/CodeGen/AMDGPU/fold-operands-order.mir b/llvm/test/CodeGen/AMDGPU/fold-operands-order.mir
index 2d329114e84b75..b23faff507e320 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-operands-order.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-operands-order.mir
@@ -1,5 +1,4 @@
# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=hawaii -verify-machineinstrs -run-pass si-fold-operands -o - %s | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=hawaii -verify-machineinstrs -passes si-fold-operands -o - %s | FileCheck -check-prefix=GCN %s
...
---
diff --git a/llvm/test/CodeGen/AMDGPU/fold-operands-remove-m0-redef.mir b/llvm/test/CodeGen/AMDGPU/fold-operands-remove-m0-redef.mir
index 9ffd39d429d097..5bb34792ecaa97 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-operands-remove-m0-redef.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-operands-remove-m0-redef.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass=si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs -passes=si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s
--- |
define amdgpu_kernel void @redef_m0_same_copy() { ret void }
diff --git a/llvm/test/CodeGen/AMDGPU/fold-operands-scalar-fmac.mir b/llvm/test/CodeGen/AMDGPU/fold-operands-scalar-fmac.mir
index 9dbdd89b282c90..08693ec9db1d4b 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-operands-scalar-fmac.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-operands-scalar-fmac.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -verify-machineinstrs -run-pass=si-fold-operands %s -o - | FileCheck %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -verify-machineinstrs -passes=si-fold-operands %s -o - | FileCheck %s
---
name: fmac_fold_inlinable_src0_to_fmamk
diff --git a/llvm/test/CodeGen/AMDGPU/fold-over-exec.mir b/llvm/test/CodeGen/AMDGPU/fold-over-exec.mir
index c1397e77faf73b..9cc6c257b029d1 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-over-exec.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-over-exec.mir
@@ -1,5 +1,4 @@
# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck %s
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs -passes si-fold-operands %s -o - | FileCheck %s
# CHECK-LABEL: bb.2:
# CHECK: %I_out
diff --git a/llvm/test/CodeGen/AMDGPU/fold-readlane.mir b/llvm/test/CodeGen/AMDGPU/fold-readlane.mir
index 440bf8d9bc9598..099b066cde255e 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-readlane.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-readlane.mir
@@ -1,5 +1,4 @@
# RUN: llc -mtriple=amdgcn -run-pass si-fold-operands -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn -passes si-fold-operands -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# GCN-LABEL: name: fold-imm-readfirstlane{{$}}
# GCN: %1:sreg_32_xm0 = S_MOV_B32 123
diff --git a/llvm/test/CodeGen/AMDGPU/fold-sgpr-copy.mir b/llvm/test/CodeGen/AMDGPU/fold-sgpr-copy.mir
index 5e124cb21da6b2..103c3e3eb8bc64 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-sgpr-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-sgpr-copy.mir
@@ -1,5 +1,4 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=si-fold-operands,dead-mi-elimination -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes=si-fold-operands,dead-mi-elimination -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
---
diff --git a/llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir b/llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir
index 426886df8c0464..1f15066264c743 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir
@@ -1,7 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass=si-fold-operands -o - %s | FileCheck --check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -passes=si-fold-operands -o - %s | FileCheck --check-prefix=GCN %s
-
---
name: no_fold_fp_64bit_literal_sgpr
diff --git a/llvm/test/CodeGen/AMDGPU/fold-vgpr-phyreg.mir b/llvm/test/CodeGen/AMDGPU/fold-vgpr-phyreg.mir
index 264b52039267f4..2d5909e3297d2e 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-vgpr-phyreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-vgpr-phyreg.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-fold-operands -verify-machineinstrs | FileCheck %s
-# RUN: llc -o - %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -passes=si-fold-operands -verify-machineinstrs | FileCheck %s
---
name: lshl_add_u64_gep
diff --git a/llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-clear-kill-flags.mir b/llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-clear-kill-flags.mir
index e31ae4ae397ec2..baaca76bfd8a89 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-clear-kill-flags.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-clear-kill-flags.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx940 -verify-machineinstrs -run-pass si-fold-operands -o - %s | FileCheck -enable-var-scope -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx940 -verify-machineinstrs -passes si-fold-operands -o - %s | FileCheck -enable-var-scope -check-prefix=GCN %s
---
name: fold_zero_high_bits_src1_alive
diff --git a/llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir b/llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir
index 518e14dedafe47..bd1164fe30f3f5 100644
--- a/llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir
+++ b/llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-fold-operands -o - %s | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -passes=si-fold-operands -o - %s | FileCheck -check-prefix=GCN %s
# The constant is 0xffffffff80000000. It is 64-bit negative constant, but it passes the test
# isInt<32>(). Nonetheless it is not a legal literal for a binary or unsigned operand and
diff --git a/llvm/test/CodeGen/AMDGPU/high-bits-zeroed-16-bit-ops.mir b/llvm/test/CodeGen/AMDGPU/high-bits-zeroed-16-bit-ops.mir
index 2d608a2dc4201c..5596eceb95d056 100644
--- a/llvm/test/CodeGen/AMDGPU/high-bits-zeroed-16-bit-ops.mir
+++ b/llvm/test/CodeGen/AMDGPU/high-bits-zeroed-16-bit-ops.mir
@@ -3,9 +3,6 @@
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -run-pass=si-fold-operands -o - %s | FileCheck -check-prefix=GFX9 %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -run-pass=si-fold-operands -o - %s | FileCheck -check-prefix=GFX10 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -passes=si-fold-operands -o - %s | FileCheck -check-prefix=GFX8 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -passes=si-fold-operands -o - %s | FileCheck -check-prefix=GFX9 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -passes=si-fold-operands -o - %s | FileCheck -check-prefix=GFX10 %s
# Test we recognize all forms of and with mask as clearing the high bits.
---
name: v_cvt_f16_f32_altmask
diff --git a/llvm/test/CodeGen/AMDGPU/huge-number-operand-folds.mir b/llvm/test/CodeGen/AMDGPU/huge-number-operand-folds.mir
index 39dffc4d87c62d..98e191a4bf2a3e 100644
--- a/llvm/test/CodeGen/AMDGPU/huge-number-operand-folds.mir
+++ b/llvm/test/CodeGen/AMDGPU/huge-number-operand-folds.mir
@@ -1,5 +1,4 @@
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -passes=si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s
# We were storing fold candidate uses in an unsigned char, which this exceeds.
# The use operand overflows and the expected register operand hits the immediate 0.
diff --git a/llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir b/llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
index 5ca2c472965bc7..91950bffd9df4a 100644
--- a/llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
+++ b/llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
@@ -1,5 +1,4 @@
# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs -passes si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s
---
diff --git a/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir b/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
index 65bdb4bb9511f7..748775dc2cf1d5 100644
--- a/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -run-pass si-fix-sgpr-copies,si-fold-operands,dead-mi-elimination -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn -passes si-fix-sgpr-copies,si-fold-operands,dead-mi-elimination -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
# Check that constant is in SGPR registers
diff --git a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
index e0e99bb571bf70..17bed38bd046d7 100644
--- a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
+++ b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -passes=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
# Do not use inline constants for f16 pseudo scalar transcendentals.
# But allow literal constants.
diff --git a/llvm/test/CodeGen/AMDGPU/si-fold-aligned-agprs.mir b/llvm/test/CodeGen/AMDGPU/si-fold-aligned-agprs.mir
index b18d9a6d0519c7..a0ea04b1b9c0f9 100644
--- a/llvm/test/CodeGen/AMDGPU/si-fold-aligned-agprs.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-fold-aligned-agprs.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GFX90A %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -passes=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GFX90A %s
# Should fold only the aligned agpr copies with their uses.
diff --git a/llvm/test/CodeGen/AMDGPU/si-fold-aligned-vgprs.mir b/llvm/test/CodeGen/AMDGPU/si-fold-aligned-vgprs.mir
index 2ceb1cb3c94441..a54c0accce7834 100644
--- a/llvm/test/CodeGen/AMDGPU/si-fold-aligned-vgprs.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-fold-aligned-vgprs.mir
@@ -1,8 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GFX908 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -passes=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GFX908 %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GFX90A %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -passes=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GFX90A %s
# Should fold all copies for gfx908. In case of gfx90a, the folding must happen only for the aligned cases.
diff --git a/llvm/test/CodeGen/AMDGPU/si-fold-copy-kills.mir b/llvm/test/CodeGen/AMDGPU/si-fold-copy-kills.mir
index e97657e6fb1b2c..89f8fb8dae6158 100644
--- a/llvm/test/CodeGen/AMDGPU/si-fold-copy-kills.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-fold-copy-kills.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
---
name: fold_reg_kill
diff --git a/llvm/test/CodeGen/AMDGPU/si-fold-kimm.mir b/llvm/test/CodeGen/AMDGPU/si-fold-kimm.mir
index d55b79e1365455..cfff5e621be535 100644
--- a/llvm/test/CodeGen/AMDGPU/si-fold-kimm.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-fold-kimm.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -passes=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
# Do not fold noninlinable constants in instructions like fmaak and fmamk next
# to kimm16 and kimm32 operands
diff --git a/llvm/test/CodeGen/AMDGPU/si-fold-reg-sequence.mir b/llvm/test/CodeGen/AMDGPU/si-fold-reg-sequence.mir
index 9db09ec97ca4d4..7852f5d0c96f55 100644
--- a/llvm/test/CodeGen/AMDGPU/si-fold-reg-sequence.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-fold-reg-sequence.mir
@@ -1,5 +1,4 @@
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=si-fold-operands -verify-machineinstrs -o - %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=si-fold-operands -verify-machineinstrs -o - %s
---
name: fold_reg_sequence
diff --git a/llvm/test/CodeGen/AMDGPU/swdev282079.mir b/llvm/test/CodeGen/AMDGPU/swdev282079.mir
index 530b41221d1fba..e5a9dcb65f7b21 100644
--- a/llvm/test/CodeGen/AMDGPU/swdev282079.mir
+++ b/llvm/test/CodeGen/AMDGPU/swdev282079.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-fold-operands -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -passes=si-fold-operands -o - %s | FileCheck %s
# This was attempting to look back through the REG_SEQUENCE source
# operands and trying to look for physreg defs.
>From ed725d001740bddf86b090d46751627b359fcaa2 Mon Sep 17 00:00:00 2001
From: Akshat Oke <Akshat.Oke at amd.com>
Date: Mon, 26 Aug 2024 05:05:09 +0000
Subject: [PATCH 4/4] Use PassInfoMixin not MachinePassInfoMixin
---
llvm/lib/Target/AMDGPU/SIFoldOperands.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.h b/llvm/lib/Target/AMDGPU/SIFoldOperands.h
index 8ad8057c2f0f7a..fd876062315df5 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.h
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.h
@@ -12,7 +12,7 @@
#include "llvm/CodeGen/MachinePassManager.h"
namespace llvm {
-class SIFoldOperandsPass : public MachinePassInfoMixin<SIFoldOperandsPass> {
+class SIFoldOperandsPass : public PassInfoMixin<SIFoldOperandsPass> {
public:
SIFoldOperandsPass() = default;
PreservedAnalyses run(MachineFunction &MF,
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