[llvm] [SelectionDAG] WIP (PR #105968)

[via llvm-commits]

https://github.com/c8ef created https://github.com/llvm/llvm-project/pull/105968

None

>From 76a7d84b55f598ddcf4c69e6717b80623d3bf61e Mon Sep 17 00:00:00 2001
From: c8ef <c8ef at outlook.com>
Date: Sun, 25 Aug 2024 10:39:59 +0800
Subject: [PATCH] fold sext(fptosi x to i32) => fptosi x to i64

---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp |  6 ++++
 llvm/test/CodeGen/X86/fptosi-sext.ll          | 33 +++++++++++++++++++
 2 files changed, 39 insertions(+)
 create mode 100644 llvm/test/CodeGen/X86/fptosi-sext.ll

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index b27f06f94ff0e7..6fb312b19913ff 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -13776,6 +13776,12 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
   if (SDValue Res = tryToFoldExtendSelectLoad(N, TLI, DAG, DL, Level))
     return Res;
 
+  if (N0.getOpcode() == ISD::FP_TO_SINT &&
+      N0.getScalarValueSizeInBits() <= VT.getScalarSizeInBits() &&
+      (!LegalOperations || TLI.isOperationLegal(N0.getOpcode(), VT))) {
+    return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0));
+  }
+
   return SDValue();
 }
 
diff --git a/llvm/test/CodeGen/X86/fptosi-sext.ll b/llvm/test/CodeGen/X86/fptosi-sext.ll
new file mode 100644
index 00000000000000..3ebcc5eb72d65c
--- /dev/null
+++ b/llvm/test/CodeGen/X86/fptosi-sext.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64 | FileCheck %s
+
+define i16 @sext_i8_i16(float %0) {
+; CHECK-LABEL: sext_i8_i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cvttss2si %xmm0, %eax
+; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT:    retq
+  %2 = fptosi float %0 to i8
+  %3 = sext i8 %2 to i16
+  ret i16 %3
+}
+
+define i32 @sext_i16_i32(float %0) {
+; CHECK-LABEL: sext_i16_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cvttss2si %xmm0, %eax
+; CHECK-NEXT:    retq
+  %2 = fptosi float %0 to i16
+  %3 = sext i16 %2 to i32
+  ret i32 %3
+}
+
+define i64 @sext_i32_i64(float %0) {
+; CHECK-LABEL: sext_i32_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cvttss2si %xmm0, %rax
+; CHECK-NEXT:    retq
+  %2 = fptosi float %0 to i32
+  %3 = sext i32 %2 to i64
+  ret i64 %3
+}