[llvm] b9a0276 - [ARM] Add VECTOR_REG_CAST identity fold.

[David Green via llvm-commits]

Author: David Green
Date: 2024-08-24T21:21:27+01:00
New Revision: b9a02765504f8b83701ffffc097531638c4fc22e

URL: https://github.com/llvm/llvm-project/commit/b9a02765504f8b83701ffffc097531638c4fc22e
DIFF: https://github.com/llvm/llvm-project/commit/b9a02765504f8b83701ffffc097531638c4fc22e.diff

LOG: [ARM] Add VECTOR_REG_CAST identity fold.

v16i8 VECTOR_REG_CAST (v16i8 Op) can use v16i8 Op directly, as the
VECTOR_REG_CAST is a noop.

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMISelLowering.cpp
    llvm/test/CodeGen/Thumb2/mve-be.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 1e8bb8a495e68b..4ab0433069ae66 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -15444,6 +15444,9 @@ static SDValue PerformVECTOR_REG_CASTCombine(SDNode *N, SelectionDAG &DAG,
   if (ST->isLittle())
     return DAG.getNode(ISD::BITCAST, dl, VT, Op);
 
+  // VT VECTOR_REG_CAST (VT Op) -> Op
+  if (Op.getValueType() == VT)
+    return Op;
   // VECTOR_REG_CAST undef -> undef
   if (Op.isUndef())
     return DAG.getUNDEF(VT);

diff  --git a/llvm/test/CodeGen/Thumb2/mve-be.ll b/llvm/test/CodeGen/Thumb2/mve-be.ll
index 522d6f8704b6af..2f2ecc76472374 100644
--- a/llvm/test/CodeGen/Thumb2/mve-be.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-be.ll
@@ -278,10 +278,9 @@ define arm_aapcs_vfpcc <4 x i32> @test(ptr %data) {
 ;
 ; CHECK-BE-LABEL: test:
 ; CHECK-BE:       @ %bb.0: @ %entry
-; CHECK-BE-NEXT:    movs r1, #1
-; CHECK-BE-NEXT:    vldrw.u32 q1, [r0, #32]
-; CHECK-BE-NEXT:    vdup.32 q0, r1
-; CHECK-BE-NEXT:    vadd.i32 q0, q1, q0
+; CHECK-BE-NEXT:    vldrw.u32 q0, [r0, #32]
+; CHECK-BE-NEXT:    movs r0, #1
+; CHECK-BE-NEXT:    vadd.i32 q0, q0, r0
 ; CHECK-BE-NEXT:    vrev32.8 q0, q0
 ; CHECK-BE-NEXT:    @APP
 ; CHECK-BE-NEXT:    vmullb.s32 q1, q0, q0