[llvm] [llvm][NVPTX] Fix RAUW bug in NVPTXProxyRegErasure (PR #105871)
Jeff Niu via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 23 20:36:42 PDT 2024
https://github.com/Mogball updated https://github.com/llvm/llvm-project/pull/105871
>From 2a50cb17baac0449bf6b21e981fa786d52dea390 Mon Sep 17 00:00:00 2001
From: Mogball <jeff at modular.com>
Date: Fri, 23 Aug 2024 14:28:36 -0400
Subject: [PATCH 1/4] [llvm][NVPTX] Fix RAUW bug in NVPTXProxyRegErasure
Fix bug introduced in #105730
---
llvm/lib/Target/NVPTX/NVPTXProxyRegErasure.cpp | 6 +++++-
llvm/test/CodeGen/NVPTX/bug105730.ll | 17 +++++++++++++++++
2 files changed, 22 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/NVPTX/bug105730.ll
diff --git a/llvm/lib/Target/NVPTX/NVPTXProxyRegErasure.cpp b/llvm/lib/Target/NVPTX/NVPTXProxyRegErasure.cpp
index f3a3362addb0ea..16c2b307efabfb 100644
--- a/llvm/lib/Target/NVPTX/NVPTXProxyRegErasure.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXProxyRegErasure.cpp
@@ -78,7 +78,11 @@ bool NVPTXProxyRegErasure::runOnMachineFunction(MachineFunction &MF) {
assert(InOp.isReg() && "ProxyReg input should be a register.");
assert(OutOp.isReg() && "ProxyReg output should be a register.");
RemoveList.push_back(&MI);
- RAUWBatch.try_emplace(OutOp.getReg(), InOp.getReg());
+ Register replacement = InOp.getReg();
+ // Check if the replacement itself has been replaced.
+ if (auto it = RAUWBatch.find(replacement); it != RAUWBatch.end())
+ replacement = it->second;
+ RAUWBatch.try_emplace(OutOp.getReg(), replacement);
break;
}
}
diff --git a/llvm/test/CodeGen/NVPTX/bug105730.ll b/llvm/test/CodeGen/NVPTX/bug105730.ll
new file mode 100644
index 00000000000000..718e7ca6b80fd8
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/bug105730.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -verify-machineinstrs
+
+; Check that llc doesn't crash.
+
+target triple = "nvptx64-nvidia-cuda"
+
+define void @__builtin_splat_i8(i32 %0) {
+.lr.ph:
+ %1 = trunc i32 %0 to i8
+ %broadcast.splatinsert = insertelement <4 x i8> poison, i8 %1, i64 0
+ %broadcast.splat = shufflevector <4 x i8> %broadcast.splatinsert, <4 x i8> poison, <4 x i32> zeroinitializer
+ br label %vector.body
+
+vector.body:
+ store <4 x i8> %broadcast.splat, ptr addrspace(1) poison, align 1
+ br label %vector.body
+}
>From 29fd526f2ed796c9152a1266bd08f37d1f1e9810 Mon Sep 17 00:00:00 2001
From: Mogball <jeff at modular.com>
Date: Fri, 23 Aug 2024 14:54:12 -0400
Subject: [PATCH 2/4] move test to proxy-reg-erasure.ll
---
llvm/test/CodeGen/NVPTX/bug105730.ll | 17 -----------------
.../CodeGen/NVPTX/proxy-reg-erasure-mir.ll | 19 +++++++++++++++++++
2 files changed, 19 insertions(+), 17 deletions(-)
delete mode 100644 llvm/test/CodeGen/NVPTX/bug105730.ll
diff --git a/llvm/test/CodeGen/NVPTX/bug105730.ll b/llvm/test/CodeGen/NVPTX/bug105730.ll
deleted file mode 100644
index 718e7ca6b80fd8..00000000000000
--- a/llvm/test/CodeGen/NVPTX/bug105730.ll
+++ /dev/null
@@ -1,17 +0,0 @@
-; RUN: llc < %s -verify-machineinstrs
-
-; Check that llc doesn't crash.
-
-target triple = "nvptx64-nvidia-cuda"
-
-define void @__builtin_splat_i8(i32 %0) {
-.lr.ph:
- %1 = trunc i32 %0 to i8
- %broadcast.splatinsert = insertelement <4 x i8> poison, i8 %1, i64 0
- %broadcast.splat = shufflevector <4 x i8> %broadcast.splatinsert, <4 x i8> poison, <4 x i32> zeroinitializer
- br label %vector.body
-
-vector.body:
- store <4 x i8> %broadcast.splat, ptr addrspace(1) poison, align 1
- br label %vector.body
-}
diff --git a/llvm/test/CodeGen/NVPTX/proxy-reg-erasure-mir.ll b/llvm/test/CodeGen/NVPTX/proxy-reg-erasure-mir.ll
index 6bfbe2aea8196c..600e1de73690f7 100644
--- a/llvm/test/CodeGen/NVPTX/proxy-reg-erasure-mir.ll
+++ b/llvm/test/CodeGen/NVPTX/proxy-reg-erasure-mir.ll
@@ -7,6 +7,9 @@
; Check ProxyRegErasure pass MIR manipulation.
declare <4 x i32> @callee_vec_i32()
+declare void @use_vec_i32(<4 x i32>)
+
+; MIR: check_vec_i32
define <4 x i32> @check_vec_i32() {
; MIR: body:
; MIR-DAG: Callseq_Start {{[0-9]+}}, {{[0-9]+}}
@@ -23,3 +26,19 @@ define <4 x i32> @check_vec_i32() {
%ret = call <4 x i32> @callee_vec_i32()
ret <4 x i32> %ret
}
+
+; MIR: check_chained_proxy
+define void @check_chained_proxy(i8 %0) {
+ ; MIR: body:
+ ; MIR-BEFORE: %0:int32regs = ProxyRegI32 killed %4
+ %broadcast.splatinsert = insertelement <4 x i8> poison, i8 %0, i64 0
+ %broadcast.splat = shufflevector <4 x i8> %broadcast.splatinsert, <4 x i8> poison, <4 x i32> zeroinitializer
+ br label %vector.body
+
+vector.body:
+ ; MIR-BEFORE: %5:int32regs = ProxyRegI32 %0
+ ; MIR-BEFORE: SRLi32ri %5,
+ ; MIR-AFTER: SRLi32ri %4,
+ store <4 x i8> %broadcast.splat, ptr poison, align 1
+ br label %vector.body
+}
>From b7304a63b80989d1506c8b2a51572c703fe80fd5 Mon Sep 17 00:00:00 2001
From: Mogball <jeff at modular.com>
Date: Fri, 23 Aug 2024 14:54:50 -0400
Subject: [PATCH 3/4] remove unused func in test
---
llvm/test/CodeGen/NVPTX/proxy-reg-erasure-mir.ll | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/test/CodeGen/NVPTX/proxy-reg-erasure-mir.ll b/llvm/test/CodeGen/NVPTX/proxy-reg-erasure-mir.ll
index 600e1de73690f7..95cb05b6c981b5 100644
--- a/llvm/test/CodeGen/NVPTX/proxy-reg-erasure-mir.ll
+++ b/llvm/test/CodeGen/NVPTX/proxy-reg-erasure-mir.ll
@@ -7,7 +7,6 @@
; Check ProxyRegErasure pass MIR manipulation.
declare <4 x i32> @callee_vec_i32()
-declare void @use_vec_i32(<4 x i32>)
; MIR: check_vec_i32
define <4 x i32> @check_vec_i32() {
>From ba406ff13f152c2da4b79a731c4c63029d89602e Mon Sep 17 00:00:00 2001
From: Mogball <jeff at modular.com>
Date: Fri, 23 Aug 2024 23:36:29 -0400
Subject: [PATCH 4/4] convert test to MIR
---
.../CodeGen/NVPTX/proxy-reg-erasure-mir.ll | 43 --------
llvm/test/CodeGen/NVPTX/proxy-reg-erasure.mir | 98 +++++++++++++++++++
2 files changed, 98 insertions(+), 43 deletions(-)
delete mode 100644 llvm/test/CodeGen/NVPTX/proxy-reg-erasure-mir.ll
create mode 100644 llvm/test/CodeGen/NVPTX/proxy-reg-erasure.mir
diff --git a/llvm/test/CodeGen/NVPTX/proxy-reg-erasure-mir.ll b/llvm/test/CodeGen/NVPTX/proxy-reg-erasure-mir.ll
deleted file mode 100644
index 95cb05b6c981b5..00000000000000
--- a/llvm/test/CodeGen/NVPTX/proxy-reg-erasure-mir.ll
+++ /dev/null
@@ -1,43 +0,0 @@
-; RUN: llc -march=nvptx64 -stop-before=nvptx-proxyreg-erasure < %s 2>&1 \
-; RUN: | FileCheck %s --check-prefix=MIR --check-prefix=MIR-BEFORE
-
-; RUN: llc -march=nvptx64 -stop-after=nvptx-proxyreg-erasure < %s 2>&1 \
-; RUN: | FileCheck %s --check-prefix=MIR --check-prefix=MIR-AFTER
-
-; Check ProxyRegErasure pass MIR manipulation.
-
-declare <4 x i32> @callee_vec_i32()
-
-; MIR: check_vec_i32
-define <4 x i32> @check_vec_i32() {
- ; MIR: body:
- ; MIR-DAG: Callseq_Start {{[0-9]+}}, {{[0-9]+}}
- ; MIR-DAG: %0:int32regs, %1:int32regs, %2:int32regs, %3:int32regs = LoadParamMemV4I32 0
- ; MIR-DAG: Callseq_End {{[0-9]+}}
-
- ; MIR-BEFORE-DAG: %4:int32regs = ProxyRegI32 killed %0
- ; MIR-BEFORE-DAG: %5:int32regs = ProxyRegI32 killed %1
- ; MIR-BEFORE-DAG: %6:int32regs = ProxyRegI32 killed %2
- ; MIR-BEFORE-DAG: %7:int32regs = ProxyRegI32 killed %3
- ; MIR-BEFORE-DAG: StoreRetvalV4I32 killed %4, killed %5, killed %6, killed %7, 0
- ; MIR-AFTER-DAG: StoreRetvalV4I32 killed %0, killed %1, killed %2, killed %3, 0
-
- %ret = call <4 x i32> @callee_vec_i32()
- ret <4 x i32> %ret
-}
-
-; MIR: check_chained_proxy
-define void @check_chained_proxy(i8 %0) {
- ; MIR: body:
- ; MIR-BEFORE: %0:int32regs = ProxyRegI32 killed %4
- %broadcast.splatinsert = insertelement <4 x i8> poison, i8 %0, i64 0
- %broadcast.splat = shufflevector <4 x i8> %broadcast.splatinsert, <4 x i8> poison, <4 x i32> zeroinitializer
- br label %vector.body
-
-vector.body:
- ; MIR-BEFORE: %5:int32regs = ProxyRegI32 %0
- ; MIR-BEFORE: SRLi32ri %5,
- ; MIR-AFTER: SRLi32ri %4,
- store <4 x i8> %broadcast.splat, ptr poison, align 1
- br label %vector.body
-}
diff --git a/llvm/test/CodeGen/NVPTX/proxy-reg-erasure.mir b/llvm/test/CodeGen/NVPTX/proxy-reg-erasure.mir
new file mode 100644
index 00000000000000..7f80d011901d34
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/proxy-reg-erasure.mir
@@ -0,0 +1,98 @@
+# RUN: llc %s --run-pass=nvptx-proxyreg-erasure -march=nvptx64 -o - | FileCheck %s
+
+--- |
+ ; ModuleID = 'third-party/llvm-project/llvm/test/CodeGen/NVPTX/proxy-reg-erasure-mir.ll'
+ source_filename = "third-party/llvm-project/llvm/test/CodeGen/NVPTX/proxy-reg-erasure-mir.ll"
+ target datalayout = "e-i64:64-i128:128-v16:16-v32:32-n16:32:64"
+
+ declare <4 x i32> @callee_vec_i32()
+
+ define <4 x i32> @check_vec_i32() {
+ %ret = call <4 x i32> @callee_vec_i32()
+ ret <4 x i32> %ret
+ }
+
+...
+---
+name: check_vec_i32
+alignment: 1
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+hasWinCFI: false
+callsEHReturn: false
+callsUnwindInit: false
+hasEHCatchret: false
+hasEHScopes: false
+hasEHFunclets: false
+isOutlined: false
+debugInstrRef: false
+failsVerification: false
+tracksDebugUserValues: false
+registers:
+ - { id: 0, class: int32regs, preferred-register: '' }
+ - { id: 1, class: int32regs, preferred-register: '' }
+ - { id: 2, class: int32regs, preferred-register: '' }
+ - { id: 3, class: int32regs, preferred-register: '' }
+ - { id: 4, class: int32regs, preferred-register: '' }
+ - { id: 5, class: int32regs, preferred-register: '' }
+ - { id: 6, class: int32regs, preferred-register: '' }
+ - { id: 7, class: int32regs, preferred-register: '' }
+ - { id: 8, class: int32regs, preferred-register: '' }
+ - { id: 9, class: int32regs, preferred-register: '' }
+ - { id: 10, class: int32regs, preferred-register: '' }
+ - { id: 11, class: int32regs, preferred-register: '' }
+liveins: []
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: true
+ stackProtector: ''
+ functionContext: ''
+ maxCallFrameSize: 4294967295
+ cvBytesOfCalleeSavedRegisters: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ hasTailCall: false
+ isCalleeSavedInfoValid: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack: []
+stack: []
+entry_values: []
+callSites: []
+debugValueSubstitutions: []
+constants: []
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ %0:int32regs, %1:int32regs, %2:int32regs, %3:int32regs = LoadParamMemV4I32 0
+ ; CHECK-NOT: ProxyReg
+ %4:int32regs = ProxyRegI32 killed %0
+ %5:int32regs = ProxyRegI32 killed %1
+ %6:int32regs = ProxyRegI32 killed %2
+ %7:int32regs = ProxyRegI32 killed %3
+ ; CHECK: StoreRetvalV4I32 killed %0, killed %1, killed %2, killed %3
+ StoreRetvalV4I32 killed %4, killed %5, killed %6, killed %7, 0
+
+ %8:int32regs = LoadParamMemI32 0
+ ; CHECK-NOT: ProxyReg
+ %9:int32regs = ProxyRegI32 killed %8
+ %10:int32regs = ProxyRegI32 killed %9
+ %11:int32regs = ProxyRegI32 killed %10
+ ; CHECK: StoreRetvalI32 killed %8
+ StoreRetvalI32 killed %11, 0
+ Return
+
+...
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