[llvm] [llvm][NVPTX] Fix RAUW bug in NVPTXProxyRegErasure (PR #105871)

[Artem Belevich via llvm-commits]

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@@ -23,3 +25,19 @@ define  <4 x i32> @check_vec_i32() {
   %ret = call <4 x i32> @callee_vec_i32()
   ret <4 x i32> %ret
 }
+
+; MIR: check_chained_proxy
+define void @check_chained_proxy(i8 %0) {
+  ; MIR: body:
+  ; MIR-BEFORE: %0:int32regs = ProxyRegI32 killed %4
+  %broadcast.splatinsert = insertelement <4 x i8> poison, i8 %0, i64 0
+  %broadcast.splat = shufflevector <4 x i8> %broadcast.splatinsert, <4 x i8> poison, <4 x i32> zeroinitializer
+  br label %vector.body
+
+vector.body:
+  ; MIR-BEFORE: %5:int32regs = ProxyRegI32 %0
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Artem-B wrote:

It would be great to convert the test to pure MIR test.
I.e. dump MIR with `llc -print-before=nvptx-proxyreg-erasure` and then use `llc -run-pass=nvptx-proxyreg-erasure` on the MIR.

This will allow us to precisely construct MIR we want to test, instead of indirectly relying on IR to give us MIR which has relevant bits. 

https://github.com/llvm/llvm-project/pull/105871