[llvm] 646478f - [AArch64] Scalarize i128 add/sub/mul/and/or/xor vectors
David Green via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 23 02:53:37 PDT 2024
Author: David Green
Date: 2024-08-23T10:53:31+01:00
New Revision: 646478f38b03cbc861ae17533c641c2a944118b3
URL: https://github.com/llvm/llvm-project/commit/646478f38b03cbc861ae17533c641c2a944118b3
DIFF: https://github.com/llvm/llvm-project/commit/646478f38b03cbc861ae17533c641c2a944118b3.diff
LOG: [AArch64] Scalarize i128 add/sub/mul/and/or/xor vectors
This mirrors what we do for SDAG, scalarizing i128 vectors with
add/sub/mul/and/or/xor operators.
Added:
Modified:
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/add.ll
llvm/test/CodeGen/AArch64/andorxor.ll
llvm/test/CodeGen/AArch64/mul.ll
llvm/test/CodeGen/AArch64/sub.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 35d73d36df46fe..7eaf6a84bd204f 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -149,6 +149,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
return Query.Types[0].getNumElements() <= 16;
},
0, s8)
+ .scalarizeIf(scalarOrEltWiderThan(0, 64), 0)
.moreElementsToNextPow2(0);
getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR})
diff --git a/llvm/test/CodeGen/AArch64/add.ll b/llvm/test/CodeGen/AArch64/add.ll
index 39d1933f0e7b97..ee15445a7bbd62 100644
--- a/llvm/test/CodeGen/AArch64/add.ll
+++ b/llvm/test/CodeGen/AArch64/add.ll
@@ -1,10 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=aarch64-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc -mtriple=aarch64-none-eabi -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-
-; CHECK-GI: warning: Instruction selection used fallback path for v2i128
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v3i128
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v4i128
+; RUN: llc -mtriple=aarch64-none-eabi -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define i8 @i8(i8 %a, i8 %b) {
; CHECK-LABEL: i8:
@@ -480,21 +476,37 @@ entry:
}
define <4 x i128> @v4i128(<4 x i128> %d, <4 x i128> %e) {
-; CHECK-LABEL: v4i128:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ldp x8, x9, [sp]
-; CHECK-NEXT: ldp x11, x10, [sp, #16]
-; CHECK-NEXT: ldp x13, x12, [sp, #32]
-; CHECK-NEXT: adds x0, x0, x8
-; CHECK-NEXT: adc x1, x1, x9
-; CHECK-NEXT: ldp x8, x9, [sp, #48]
-; CHECK-NEXT: adds x2, x2, x11
-; CHECK-NEXT: adc x3, x3, x10
-; CHECK-NEXT: adds x4, x4, x13
-; CHECK-NEXT: adc x5, x5, x12
-; CHECK-NEXT: adds x6, x6, x8
-; CHECK-NEXT: adc x7, x7, x9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: v4i128:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ldp x8, x9, [sp]
+; CHECK-SD-NEXT: ldp x11, x10, [sp, #16]
+; CHECK-SD-NEXT: ldp x13, x12, [sp, #32]
+; CHECK-SD-NEXT: adds x0, x0, x8
+; CHECK-SD-NEXT: adc x1, x1, x9
+; CHECK-SD-NEXT: ldp x8, x9, [sp, #48]
+; CHECK-SD-NEXT: adds x2, x2, x11
+; CHECK-SD-NEXT: adc x3, x3, x10
+; CHECK-SD-NEXT: adds x4, x4, x13
+; CHECK-SD-NEXT: adc x5, x5, x12
+; CHECK-SD-NEXT: adds x6, x6, x8
+; CHECK-SD-NEXT: adc x7, x7, x9
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: v4i128:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ldp x8, x9, [sp]
+; CHECK-GI-NEXT: ldp x10, x11, [sp, #16]
+; CHECK-GI-NEXT: ldp x12, x13, [sp, #32]
+; CHECK-GI-NEXT: adds x0, x0, x8
+; CHECK-GI-NEXT: adc x1, x1, x9
+; CHECK-GI-NEXT: ldp x8, x9, [sp, #48]
+; CHECK-GI-NEXT: adds x2, x2, x10
+; CHECK-GI-NEXT: adc x3, x3, x11
+; CHECK-GI-NEXT: adds x4, x4, x12
+; CHECK-GI-NEXT: adc x5, x5, x13
+; CHECK-GI-NEXT: adds x6, x6, x8
+; CHECK-GI-NEXT: adc x7, x7, x9
+; CHECK-GI-NEXT: ret
entry:
%s = add <4 x i128> %d, %e
ret <4 x i128> %s
diff --git a/llvm/test/CodeGen/AArch64/andorxor.ll b/llvm/test/CodeGen/AArch64/andorxor.ll
index efa4be707ceda9..1176c98ce44e34 100644
--- a/llvm/test/CodeGen/AArch64/andorxor.ll
+++ b/llvm/test/CodeGen/AArch64/andorxor.ll
@@ -1,16 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=aarch64-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc -mtriple=aarch64-none-eabi -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-
-; CHECK-GI: warning: Instruction selection used fallback path for and_v2i128
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for or_v2i128
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for xor_v2i128
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for and_v3i128
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for or_v3i128
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for xor_v3i128
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for and_v4i128
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for or_v4i128
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for xor_v4i128
+; RUN: llc -mtriple=aarch64-none-eabi -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define i8 @and_i8(i8 %a, i8 %b) {
; CHECK-LABEL: and_i8:
@@ -1369,153 +1359,261 @@ entry:
}
define <2 x i128> @and_v2i128(<2 x i128> %d, <2 x i128> %e) {
-; CHECK-LABEL: and_v2i128:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: and x2, x2, x6
-; CHECK-NEXT: and x0, x0, x4
-; CHECK-NEXT: and x1, x1, x5
-; CHECK-NEXT: and x3, x3, x7
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: and_v2i128:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: and x2, x2, x6
+; CHECK-SD-NEXT: and x0, x0, x4
+; CHECK-SD-NEXT: and x1, x1, x5
+; CHECK-SD-NEXT: and x3, x3, x7
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: and_v2i128:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: and x0, x0, x4
+; CHECK-GI-NEXT: and x1, x1, x5
+; CHECK-GI-NEXT: and x2, x2, x6
+; CHECK-GI-NEXT: and x3, x3, x7
+; CHECK-GI-NEXT: ret
entry:
%s = and <2 x i128> %d, %e
ret <2 x i128> %s
}
define <2 x i128> @or_v2i128(<2 x i128> %d, <2 x i128> %e) {
-; CHECK-LABEL: or_v2i128:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: orr x2, x2, x6
-; CHECK-NEXT: orr x0, x0, x4
-; CHECK-NEXT: orr x1, x1, x5
-; CHECK-NEXT: orr x3, x3, x7
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: or_v2i128:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: orr x2, x2, x6
+; CHECK-SD-NEXT: orr x0, x0, x4
+; CHECK-SD-NEXT: orr x1, x1, x5
+; CHECK-SD-NEXT: orr x3, x3, x7
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: or_v2i128:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: orr x0, x0, x4
+; CHECK-GI-NEXT: orr x1, x1, x5
+; CHECK-GI-NEXT: orr x2, x2, x6
+; CHECK-GI-NEXT: orr x3, x3, x7
+; CHECK-GI-NEXT: ret
entry:
%s = or <2 x i128> %d, %e
ret <2 x i128> %s
}
define <2 x i128> @xor_v2i128(<2 x i128> %d, <2 x i128> %e) {
-; CHECK-LABEL: xor_v2i128:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: eor x2, x2, x6
-; CHECK-NEXT: eor x0, x0, x4
-; CHECK-NEXT: eor x1, x1, x5
-; CHECK-NEXT: eor x3, x3, x7
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: xor_v2i128:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: eor x2, x2, x6
+; CHECK-SD-NEXT: eor x0, x0, x4
+; CHECK-SD-NEXT: eor x1, x1, x5
+; CHECK-SD-NEXT: eor x3, x3, x7
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: xor_v2i128:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: eor x0, x0, x4
+; CHECK-GI-NEXT: eor x1, x1, x5
+; CHECK-GI-NEXT: eor x2, x2, x6
+; CHECK-GI-NEXT: eor x3, x3, x7
+; CHECK-GI-NEXT: ret
entry:
%s = xor <2 x i128> %d, %e
ret <2 x i128> %s
}
define <3 x i128> @and_v3i128(<3 x i128> %d, <3 x i128> %e) {
-; CHECK-LABEL: and_v3i128:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ldp x8, x9, [sp]
-; CHECK-NEXT: and x0, x0, x6
-; CHECK-NEXT: ldp x11, x10, [sp, #16]
-; CHECK-NEXT: and x1, x1, x7
-; CHECK-NEXT: and x2, x2, x8
-; CHECK-NEXT: and x3, x3, x9
-; CHECK-NEXT: and x4, x4, x11
-; CHECK-NEXT: and x5, x5, x10
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: and_v3i128:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ldp x8, x9, [sp]
+; CHECK-SD-NEXT: and x0, x0, x6
+; CHECK-SD-NEXT: ldp x11, x10, [sp, #16]
+; CHECK-SD-NEXT: and x1, x1, x7
+; CHECK-SD-NEXT: and x2, x2, x8
+; CHECK-SD-NEXT: and x3, x3, x9
+; CHECK-SD-NEXT: and x4, x4, x11
+; CHECK-SD-NEXT: and x5, x5, x10
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: and_v3i128:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ldp x8, x9, [sp]
+; CHECK-GI-NEXT: and x0, x0, x6
+; CHECK-GI-NEXT: ldp x10, x11, [sp, #16]
+; CHECK-GI-NEXT: and x1, x1, x7
+; CHECK-GI-NEXT: and x2, x2, x8
+; CHECK-GI-NEXT: and x3, x3, x9
+; CHECK-GI-NEXT: and x4, x4, x10
+; CHECK-GI-NEXT: and x5, x5, x11
+; CHECK-GI-NEXT: ret
entry:
%s = and <3 x i128> %d, %e
ret <3 x i128> %s
}
define <3 x i128> @or_v3i128(<3 x i128> %d, <3 x i128> %e) {
-; CHECK-LABEL: or_v3i128:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ldp x8, x9, [sp]
-; CHECK-NEXT: orr x0, x0, x6
-; CHECK-NEXT: ldp x11, x10, [sp, #16]
-; CHECK-NEXT: orr x1, x1, x7
-; CHECK-NEXT: orr x2, x2, x8
-; CHECK-NEXT: orr x3, x3, x9
-; CHECK-NEXT: orr x4, x4, x11
-; CHECK-NEXT: orr x5, x5, x10
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: or_v3i128:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ldp x8, x9, [sp]
+; CHECK-SD-NEXT: orr x0, x0, x6
+; CHECK-SD-NEXT: ldp x11, x10, [sp, #16]
+; CHECK-SD-NEXT: orr x1, x1, x7
+; CHECK-SD-NEXT: orr x2, x2, x8
+; CHECK-SD-NEXT: orr x3, x3, x9
+; CHECK-SD-NEXT: orr x4, x4, x11
+; CHECK-SD-NEXT: orr x5, x5, x10
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: or_v3i128:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ldp x8, x9, [sp]
+; CHECK-GI-NEXT: orr x0, x0, x6
+; CHECK-GI-NEXT: ldp x10, x11, [sp, #16]
+; CHECK-GI-NEXT: orr x1, x1, x7
+; CHECK-GI-NEXT: orr x2, x2, x8
+; CHECK-GI-NEXT: orr x3, x3, x9
+; CHECK-GI-NEXT: orr x4, x4, x10
+; CHECK-GI-NEXT: orr x5, x5, x11
+; CHECK-GI-NEXT: ret
entry:
%s = or <3 x i128> %d, %e
ret <3 x i128> %s
}
define <3 x i128> @xor_v3i128(<3 x i128> %d, <3 x i128> %e) {
-; CHECK-LABEL: xor_v3i128:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ldp x8, x9, [sp]
-; CHECK-NEXT: eor x0, x0, x6
-; CHECK-NEXT: ldp x11, x10, [sp, #16]
-; CHECK-NEXT: eor x1, x1, x7
-; CHECK-NEXT: eor x2, x2, x8
-; CHECK-NEXT: eor x3, x3, x9
-; CHECK-NEXT: eor x4, x4, x11
-; CHECK-NEXT: eor x5, x5, x10
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: xor_v3i128:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ldp x8, x9, [sp]
+; CHECK-SD-NEXT: eor x0, x0, x6
+; CHECK-SD-NEXT: ldp x11, x10, [sp, #16]
+; CHECK-SD-NEXT: eor x1, x1, x7
+; CHECK-SD-NEXT: eor x2, x2, x8
+; CHECK-SD-NEXT: eor x3, x3, x9
+; CHECK-SD-NEXT: eor x4, x4, x11
+; CHECK-SD-NEXT: eor x5, x5, x10
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: xor_v3i128:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ldp x8, x9, [sp]
+; CHECK-GI-NEXT: eor x0, x0, x6
+; CHECK-GI-NEXT: ldp x10, x11, [sp, #16]
+; CHECK-GI-NEXT: eor x1, x1, x7
+; CHECK-GI-NEXT: eor x2, x2, x8
+; CHECK-GI-NEXT: eor x3, x3, x9
+; CHECK-GI-NEXT: eor x4, x4, x10
+; CHECK-GI-NEXT: eor x5, x5, x11
+; CHECK-GI-NEXT: ret
entry:
%s = xor <3 x i128> %d, %e
ret <3 x i128> %s
}
define <4 x i128> @and_v4i128(<4 x i128> %d, <4 x i128> %e) {
-; CHECK-LABEL: and_v4i128:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ldp x9, x8, [sp, #32]
-; CHECK-NEXT: ldp x11, x10, [sp]
-; CHECK-NEXT: ldp x13, x12, [sp, #16]
-; CHECK-NEXT: ldp x15, x14, [sp, #48]
-; CHECK-NEXT: and x4, x4, x9
-; CHECK-NEXT: and x0, x0, x11
-; CHECK-NEXT: and x1, x1, x10
-; CHECK-NEXT: and x5, x5, x8
-; CHECK-NEXT: and x2, x2, x13
-; CHECK-NEXT: and x3, x3, x12
-; CHECK-NEXT: and x6, x6, x15
-; CHECK-NEXT: and x7, x7, x14
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: and_v4i128:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ldp x9, x8, [sp, #32]
+; CHECK-SD-NEXT: ldp x11, x10, [sp]
+; CHECK-SD-NEXT: ldp x13, x12, [sp, #16]
+; CHECK-SD-NEXT: ldp x15, x14, [sp, #48]
+; CHECK-SD-NEXT: and x4, x4, x9
+; CHECK-SD-NEXT: and x0, x0, x11
+; CHECK-SD-NEXT: and x1, x1, x10
+; CHECK-SD-NEXT: and x5, x5, x8
+; CHECK-SD-NEXT: and x2, x2, x13
+; CHECK-SD-NEXT: and x3, x3, x12
+; CHECK-SD-NEXT: and x6, x6, x15
+; CHECK-SD-NEXT: and x7, x7, x14
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: and_v4i128:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ldp x8, x9, [sp]
+; CHECK-GI-NEXT: ldp x10, x11, [sp, #16]
+; CHECK-GI-NEXT: ldp x12, x13, [sp, #32]
+; CHECK-GI-NEXT: ldp x14, x15, [sp, #48]
+; CHECK-GI-NEXT: and x0, x0, x8
+; CHECK-GI-NEXT: and x1, x1, x9
+; CHECK-GI-NEXT: and x2, x2, x10
+; CHECK-GI-NEXT: and x3, x3, x11
+; CHECK-GI-NEXT: and x4, x4, x12
+; CHECK-GI-NEXT: and x5, x5, x13
+; CHECK-GI-NEXT: and x6, x6, x14
+; CHECK-GI-NEXT: and x7, x7, x15
+; CHECK-GI-NEXT: ret
entry:
%s = and <4 x i128> %d, %e
ret <4 x i128> %s
}
define <4 x i128> @or_v4i128(<4 x i128> %d, <4 x i128> %e) {
-; CHECK-LABEL: or_v4i128:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ldp x9, x8, [sp, #32]
-; CHECK-NEXT: ldp x11, x10, [sp]
-; CHECK-NEXT: ldp x13, x12, [sp, #16]
-; CHECK-NEXT: ldp x15, x14, [sp, #48]
-; CHECK-NEXT: orr x4, x4, x9
-; CHECK-NEXT: orr x0, x0, x11
-; CHECK-NEXT: orr x1, x1, x10
-; CHECK-NEXT: orr x5, x5, x8
-; CHECK-NEXT: orr x2, x2, x13
-; CHECK-NEXT: orr x3, x3, x12
-; CHECK-NEXT: orr x6, x6, x15
-; CHECK-NEXT: orr x7, x7, x14
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: or_v4i128:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ldp x9, x8, [sp, #32]
+; CHECK-SD-NEXT: ldp x11, x10, [sp]
+; CHECK-SD-NEXT: ldp x13, x12, [sp, #16]
+; CHECK-SD-NEXT: ldp x15, x14, [sp, #48]
+; CHECK-SD-NEXT: orr x4, x4, x9
+; CHECK-SD-NEXT: orr x0, x0, x11
+; CHECK-SD-NEXT: orr x1, x1, x10
+; CHECK-SD-NEXT: orr x5, x5, x8
+; CHECK-SD-NEXT: orr x2, x2, x13
+; CHECK-SD-NEXT: orr x3, x3, x12
+; CHECK-SD-NEXT: orr x6, x6, x15
+; CHECK-SD-NEXT: orr x7, x7, x14
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: or_v4i128:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ldp x8, x9, [sp]
+; CHECK-GI-NEXT: ldp x10, x11, [sp, #16]
+; CHECK-GI-NEXT: ldp x12, x13, [sp, #32]
+; CHECK-GI-NEXT: ldp x14, x15, [sp, #48]
+; CHECK-GI-NEXT: orr x0, x0, x8
+; CHECK-GI-NEXT: orr x1, x1, x9
+; CHECK-GI-NEXT: orr x2, x2, x10
+; CHECK-GI-NEXT: orr x3, x3, x11
+; CHECK-GI-NEXT: orr x4, x4, x12
+; CHECK-GI-NEXT: orr x5, x5, x13
+; CHECK-GI-NEXT: orr x6, x6, x14
+; CHECK-GI-NEXT: orr x7, x7, x15
+; CHECK-GI-NEXT: ret
entry:
%s = or <4 x i128> %d, %e
ret <4 x i128> %s
}
define <4 x i128> @xor_v4i128(<4 x i128> %d, <4 x i128> %e) {
-; CHECK-LABEL: xor_v4i128:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ldp x9, x8, [sp, #32]
-; CHECK-NEXT: ldp x11, x10, [sp]
-; CHECK-NEXT: ldp x13, x12, [sp, #16]
-; CHECK-NEXT: ldp x15, x14, [sp, #48]
-; CHECK-NEXT: eor x4, x4, x9
-; CHECK-NEXT: eor x0, x0, x11
-; CHECK-NEXT: eor x1, x1, x10
-; CHECK-NEXT: eor x5, x5, x8
-; CHECK-NEXT: eor x2, x2, x13
-; CHECK-NEXT: eor x3, x3, x12
-; CHECK-NEXT: eor x6, x6, x15
-; CHECK-NEXT: eor x7, x7, x14
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: xor_v4i128:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ldp x9, x8, [sp, #32]
+; CHECK-SD-NEXT: ldp x11, x10, [sp]
+; CHECK-SD-NEXT: ldp x13, x12, [sp, #16]
+; CHECK-SD-NEXT: ldp x15, x14, [sp, #48]
+; CHECK-SD-NEXT: eor x4, x4, x9
+; CHECK-SD-NEXT: eor x0, x0, x11
+; CHECK-SD-NEXT: eor x1, x1, x10
+; CHECK-SD-NEXT: eor x5, x5, x8
+; CHECK-SD-NEXT: eor x2, x2, x13
+; CHECK-SD-NEXT: eor x3, x3, x12
+; CHECK-SD-NEXT: eor x6, x6, x15
+; CHECK-SD-NEXT: eor x7, x7, x14
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: xor_v4i128:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ldp x8, x9, [sp]
+; CHECK-GI-NEXT: ldp x10, x11, [sp, #16]
+; CHECK-GI-NEXT: ldp x12, x13, [sp, #32]
+; CHECK-GI-NEXT: ldp x14, x15, [sp, #48]
+; CHECK-GI-NEXT: eor x0, x0, x8
+; CHECK-GI-NEXT: eor x1, x1, x9
+; CHECK-GI-NEXT: eor x2, x2, x10
+; CHECK-GI-NEXT: eor x3, x3, x11
+; CHECK-GI-NEXT: eor x4, x4, x12
+; CHECK-GI-NEXT: eor x5, x5, x13
+; CHECK-GI-NEXT: eor x6, x6, x14
+; CHECK-GI-NEXT: eor x7, x7, x15
+; CHECK-GI-NEXT: ret
entry:
%s = xor <4 x i128> %d, %e
ret <4 x i128> %s
diff --git a/llvm/test/CodeGen/AArch64/mul.ll b/llvm/test/CodeGen/AArch64/mul.ll
index d2804329f1e255..02258bc47c54d4 100644
--- a/llvm/test/CodeGen/AArch64/mul.ll
+++ b/llvm/test/CodeGen/AArch64/mul.ll
@@ -1,10 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=aarch64-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc -mtriple=aarch64-none-eabi -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-
-; CHECK-GI: warning: Instruction selection used fallback path for v2i128
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v3i128
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v4i128
+; RUN: llc -mtriple=aarch64-none-eabi -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define i8 @i8(i8 %a, i8 %b) {
; CHECK-LABEL: i8:
@@ -531,69 +527,139 @@ entry:
}
define <2 x i128> @v2i128(<2 x i128> %d, <2 x i128> %e) {
-; CHECK-LABEL: v2i128:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: umulh x8, x2, x6
-; CHECK-NEXT: umulh x9, x0, x4
-; CHECK-NEXT: madd x8, x2, x7, x8
-; CHECK-NEXT: madd x9, x0, x5, x9
-; CHECK-NEXT: madd x3, x3, x6, x8
-; CHECK-NEXT: madd x1, x1, x4, x9
-; CHECK-NEXT: mul x0, x0, x4
-; CHECK-NEXT: mul x2, x2, x6
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: v2i128:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: umulh x8, x2, x6
+; CHECK-SD-NEXT: umulh x9, x0, x4
+; CHECK-SD-NEXT: madd x8, x2, x7, x8
+; CHECK-SD-NEXT: madd x9, x0, x5, x9
+; CHECK-SD-NEXT: madd x3, x3, x6, x8
+; CHECK-SD-NEXT: madd x1, x1, x4, x9
+; CHECK-SD-NEXT: mul x0, x0, x4
+; CHECK-SD-NEXT: mul x2, x2, x6
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: v2i128:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mul x9, x0, x5
+; CHECK-GI-NEXT: mul x12, x2, x7
+; CHECK-GI-NEXT: mul x8, x0, x4
+; CHECK-GI-NEXT: umulh x10, x0, x4
+; CHECK-GI-NEXT: madd x11, x1, x4, x9
+; CHECK-GI-NEXT: mov x0, x8
+; CHECK-GI-NEXT: mul x9, x2, x6
+; CHECK-GI-NEXT: umulh x13, x2, x6
+; CHECK-GI-NEXT: add x1, x11, x10
+; CHECK-GI-NEXT: madd x12, x3, x6, x12
+; CHECK-GI-NEXT: mov x2, x9
+; CHECK-GI-NEXT: add x3, x12, x13
+; CHECK-GI-NEXT: ret
entry:
%s = mul <2 x i128> %d, %e
ret <2 x i128> %s
}
define <3 x i128> @v3i128(<3 x i128> %d, <3 x i128> %e) {
-; CHECK-LABEL: v3i128:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: umulh x9, x0, x6
-; CHECK-NEXT: ldp x8, x10, [sp]
-; CHECK-NEXT: madd x9, x0, x7, x9
-; CHECK-NEXT: umulh x11, x2, x8
-; CHECK-NEXT: madd x1, x1, x6, x9
-; CHECK-NEXT: ldp x9, x12, [sp, #16]
-; CHECK-NEXT: madd x10, x2, x10, x11
-; CHECK-NEXT: umulh x13, x4, x9
-; CHECK-NEXT: madd x3, x3, x8, x10
-; CHECK-NEXT: madd x11, x4, x12, x13
-; CHECK-NEXT: mul x0, x0, x6
-; CHECK-NEXT: madd x5, x5, x9, x11
-; CHECK-NEXT: mul x2, x2, x8
-; CHECK-NEXT: mul x4, x4, x9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: v3i128:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: umulh x9, x0, x6
+; CHECK-SD-NEXT: ldp x8, x10, [sp]
+; CHECK-SD-NEXT: madd x9, x0, x7, x9
+; CHECK-SD-NEXT: umulh x11, x2, x8
+; CHECK-SD-NEXT: madd x1, x1, x6, x9
+; CHECK-SD-NEXT: ldp x9, x12, [sp, #16]
+; CHECK-SD-NEXT: madd x10, x2, x10, x11
+; CHECK-SD-NEXT: umulh x13, x4, x9
+; CHECK-SD-NEXT: madd x3, x3, x8, x10
+; CHECK-SD-NEXT: madd x11, x4, x12, x13
+; CHECK-SD-NEXT: mul x0, x0, x6
+; CHECK-SD-NEXT: madd x5, x5, x9, x11
+; CHECK-SD-NEXT: mul x2, x2, x8
+; CHECK-SD-NEXT: mul x4, x4, x9
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: v3i128:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ldp x10, x13, [sp]
+; CHECK-GI-NEXT: mul x9, x0, x7
+; CHECK-GI-NEXT: mul x8, x0, x6
+; CHECK-GI-NEXT: mul x13, x2, x13
+; CHECK-GI-NEXT: madd x12, x1, x6, x9
+; CHECK-GI-NEXT: mul x9, x2, x10
+; CHECK-GI-NEXT: umulh x14, x2, x10
+; CHECK-GI-NEXT: madd x10, x3, x10, x13
+; CHECK-GI-NEXT: ldp x13, x15, [sp, #16]
+; CHECK-GI-NEXT: mov x2, x9
+; CHECK-GI-NEXT: umulh x11, x0, x6
+; CHECK-GI-NEXT: mov x0, x8
+; CHECK-GI-NEXT: mul x15, x4, x15
+; CHECK-GI-NEXT: add x3, x10, x14
+; CHECK-GI-NEXT: umulh x16, x4, x13
+; CHECK-GI-NEXT: add x1, x12, x11
+; CHECK-GI-NEXT: madd x15, x5, x13, x15
+; CHECK-GI-NEXT: mul x4, x4, x13
+; CHECK-GI-NEXT: add x5, x15, x16
+; CHECK-GI-NEXT: ret
entry:
%s = mul <3 x i128> %d, %e
ret <3 x i128> %s
}
define <4 x i128> @v4i128(<4 x i128> %d, <4 x i128> %e) {
-; CHECK-LABEL: v4i128:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ldp x8, x9, [sp]
-; CHECK-NEXT: ldp x11, x12, [sp, #16]
-; CHECK-NEXT: umulh x10, x0, x8
-; CHECK-NEXT: umulh x13, x2, x11
-; CHECK-NEXT: madd x9, x0, x9, x10
-; CHECK-NEXT: madd x10, x2, x12, x13
-; CHECK-NEXT: ldp x13, x14, [sp, #48]
-; CHECK-NEXT: madd x1, x1, x8, x9
-; CHECK-NEXT: madd x3, x3, x11, x10
-; CHECK-NEXT: ldp x9, x10, [sp, #32]
-; CHECK-NEXT: umulh x15, x6, x13
-; CHECK-NEXT: umulh x12, x4, x9
-; CHECK-NEXT: mul x0, x0, x8
-; CHECK-NEXT: madd x10, x4, x10, x12
-; CHECK-NEXT: madd x12, x6, x14, x15
-; CHECK-NEXT: madd x5, x5, x9, x10
-; CHECK-NEXT: madd x7, x7, x13, x12
-; CHECK-NEXT: mul x2, x2, x11
-; CHECK-NEXT: mul x4, x4, x9
-; CHECK-NEXT: mul x6, x6, x13
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: v4i128:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ldp x8, x9, [sp]
+; CHECK-SD-NEXT: ldp x11, x12, [sp, #16]
+; CHECK-SD-NEXT: umulh x10, x0, x8
+; CHECK-SD-NEXT: umulh x13, x2, x11
+; CHECK-SD-NEXT: madd x9, x0, x9, x10
+; CHECK-SD-NEXT: madd x10, x2, x12, x13
+; CHECK-SD-NEXT: ldp x13, x14, [sp, #48]
+; CHECK-SD-NEXT: madd x1, x1, x8, x9
+; CHECK-SD-NEXT: madd x3, x3, x11, x10
+; CHECK-SD-NEXT: ldp x9, x10, [sp, #32]
+; CHECK-SD-NEXT: umulh x15, x6, x13
+; CHECK-SD-NEXT: umulh x12, x4, x9
+; CHECK-SD-NEXT: mul x0, x0, x8
+; CHECK-SD-NEXT: madd x10, x4, x10, x12
+; CHECK-SD-NEXT: madd x12, x6, x14, x15
+; CHECK-SD-NEXT: madd x5, x5, x9, x10
+; CHECK-SD-NEXT: madd x7, x7, x13, x12
+; CHECK-SD-NEXT: mul x2, x2, x11
+; CHECK-SD-NEXT: mul x4, x4, x9
+; CHECK-SD-NEXT: mul x6, x6, x13
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: v4i128:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ldp x9, x10, [sp]
+; CHECK-GI-NEXT: ldp x15, x16, [sp, #32]
+; CHECK-GI-NEXT: mul x10, x0, x10
+; CHECK-GI-NEXT: mul x16, x4, x16
+; CHECK-GI-NEXT: madd x12, x1, x9, x10
+; CHECK-GI-NEXT: ldp x10, x13, [sp, #16]
+; CHECK-GI-NEXT: mul x8, x0, x9
+; CHECK-GI-NEXT: mul x13, x2, x13
+; CHECK-GI-NEXT: umulh x11, x0, x9
+; CHECK-GI-NEXT: mul x9, x2, x10
+; CHECK-GI-NEXT: umulh x14, x2, x10
+; CHECK-GI-NEXT: add x1, x12, x11
+; CHECK-GI-NEXT: madd x13, x3, x10, x13
+; CHECK-GI-NEXT: mov x2, x9
+; CHECK-GI-NEXT: mul x10, x4, x15
+; CHECK-GI-NEXT: umulh x17, x4, x15
+; CHECK-GI-NEXT: add x3, x13, x14
+; CHECK-GI-NEXT: madd x15, x5, x15, x16
+; CHECK-GI-NEXT: ldp x16, x18, [sp, #48]
+; CHECK-GI-NEXT: mov x4, x10
+; CHECK-GI-NEXT: mul x18, x6, x18
+; CHECK-GI-NEXT: umulh x0, x6, x16
+; CHECK-GI-NEXT: add x5, x15, x17
+; CHECK-GI-NEXT: madd x18, x7, x16, x18
+; CHECK-GI-NEXT: mul x6, x6, x16
+; CHECK-GI-NEXT: add x7, x18, x0
+; CHECK-GI-NEXT: mov x0, x8
+; CHECK-GI-NEXT: ret
entry:
%s = mul <4 x i128> %d, %e
ret <4 x i128> %s
diff --git a/llvm/test/CodeGen/AArch64/sub.ll b/llvm/test/CodeGen/AArch64/sub.ll
index 0f18ed1006fac5..907605494dfbd0 100644
--- a/llvm/test/CodeGen/AArch64/sub.ll
+++ b/llvm/test/CodeGen/AArch64/sub.ll
@@ -1,10 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=aarch64-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc -mtriple=aarch64-none-eabi -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-
-; CHECK-GI: warning: Instruction selection used fallback path for v2i128
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v3i128
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v4i128
+; RUN: llc -mtriple=aarch64-none-eabi -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define i8 @i8(i8 %a, i8 %b) {
; CHECK-LABEL: i8:
@@ -480,21 +476,37 @@ entry:
}
define <4 x i128> @v4i128(<4 x i128> %d, <4 x i128> %e) {
-; CHECK-LABEL: v4i128:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ldp x8, x9, [sp]
-; CHECK-NEXT: ldp x11, x10, [sp, #16]
-; CHECK-NEXT: ldp x13, x12, [sp, #32]
-; CHECK-NEXT: subs x0, x0, x8
-; CHECK-NEXT: sbc x1, x1, x9
-; CHECK-NEXT: ldp x8, x9, [sp, #48]
-; CHECK-NEXT: subs x2, x2, x11
-; CHECK-NEXT: sbc x3, x3, x10
-; CHECK-NEXT: subs x4, x4, x13
-; CHECK-NEXT: sbc x5, x5, x12
-; CHECK-NEXT: subs x6, x6, x8
-; CHECK-NEXT: sbc x7, x7, x9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: v4i128:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ldp x8, x9, [sp]
+; CHECK-SD-NEXT: ldp x11, x10, [sp, #16]
+; CHECK-SD-NEXT: ldp x13, x12, [sp, #32]
+; CHECK-SD-NEXT: subs x0, x0, x8
+; CHECK-SD-NEXT: sbc x1, x1, x9
+; CHECK-SD-NEXT: ldp x8, x9, [sp, #48]
+; CHECK-SD-NEXT: subs x2, x2, x11
+; CHECK-SD-NEXT: sbc x3, x3, x10
+; CHECK-SD-NEXT: subs x4, x4, x13
+; CHECK-SD-NEXT: sbc x5, x5, x12
+; CHECK-SD-NEXT: subs x6, x6, x8
+; CHECK-SD-NEXT: sbc x7, x7, x9
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: v4i128:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ldp x8, x9, [sp]
+; CHECK-GI-NEXT: ldp x10, x11, [sp, #16]
+; CHECK-GI-NEXT: ldp x12, x13, [sp, #32]
+; CHECK-GI-NEXT: subs x0, x0, x8
+; CHECK-GI-NEXT: sbc x1, x1, x9
+; CHECK-GI-NEXT: ldp x8, x9, [sp, #48]
+; CHECK-GI-NEXT: subs x2, x2, x10
+; CHECK-GI-NEXT: sbc x3, x3, x11
+; CHECK-GI-NEXT: subs x4, x4, x12
+; CHECK-GI-NEXT: sbc x5, x5, x13
+; CHECK-GI-NEXT: subs x6, x6, x8
+; CHECK-GI-NEXT: sbc x7, x7, x9
+; CHECK-GI-NEXT: ret
entry:
%s = sub <4 x i128> %d, %e
ret <4 x i128> %s
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