[llvm] [AMDGPU][NFCI] Reorder AGPRs to allow skipping over them (PR #105633)

[Matt Arsenault via llvm-commits]

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@@ -3365,6 +3365,24 @@ SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO,
   return nullptr;
 }
 
+unsigned SIRegisterInfo::getNumSupportedRegs(const MachineFunction &MF) const {
+#ifndef NDEBUG
+  for (unsigned K = AMDGPU::AGPR0; K < AMDGPU::NUM_TARGET_REGS; ++K) {
+    // Skip lo16 registers, they're "fake" and don't have a regclass assigned.
+    if (K >= AMDGPU::AGPR0_HI16 && K <= AMDGPU::AGPR255_HI16)
+      continue;
+    if (!isAGPR(MF.getRegInfo(), K))
+      report_fatal_error("register at index " + Twine(K) + " is not an AGPR!");
+  }
+#endif
+
+  // Don't include AGPRs on targets that don't have them.
+  // This cuts about 4000 register (almost half of all registers) off.
+  return MF.getInfo<SIMachineFunctionInfo>()->mayUseAGPRs(MF.getFunction())
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arsenm wrote:

Actually this is bugged. You should probably just start with considering ST.hasGFX90AInsts(), but you want MFI::usesAGPRs, not mayUseAGPRs which looks at the underlying IR attribute.

I would also hope you wouldn't need to special case this. All the registers are reserved in the case where they are unavailable. 

The second possible bug is amdgpu-no-agprs means the IR doesn't require the kernel to allocate AGPRs. But AGPRs may still appear as a result of the occupancy bounds (we probably should fix the inference logic to consider that case) 

https://github.com/llvm/llvm-project/pull/105633