[llvm] [AArch64] optimise SVE cmp intrinsics with no active lanes (PR #104779)

[via llvm-commits]

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@@ -0,0 +1,245 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -S -passes=instcombine < %s | FileCheck %s
+target triple = "aarch64-unknown-linux-gnu"
+
+define <vscale x 16 x i1> @test_cmpeq(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b){
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Lukacma wrote:

The reason is that all different element types will in the end map to the same intrinsic anyway. So if this optimisation works for one type it will work for all. 

https://github.com/llvm/llvm-project/pull/104779