[llvm] 8863685 - [RISCV][GISel] Correct registers classes in vector sext/zext.mir tests. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 21 20:42:44 PDT 2024
Author: Craig Topper
Date: 2024-08-21T20:37:37-07:00
New Revision: 88636854b007affdbe324369b26c9ded66934b22
URL: https://github.com/llvm/llvm-project/commit/88636854b007affdbe324369b26c9ded66934b22
DIFF: https://github.com/llvm/llvm-project/commit/88636854b007affdbe324369b26c9ded66934b22.diff
LOG: [RISCV][GISel] Correct registers classes in vector sext/zext.mir tests. NFC
The liveins were always for an LMUL=1 register class even if the
first instruction used a larger regsister class.
One test in zext.mir used the wrong class for the first instruction.
Added:
Modified:
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sext.mir
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/zext.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sext.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sext.mir
index 382166fb20544e..a52e7203761ab9 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sext.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sext.mir
@@ -393,10 +393,10 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $v8
+ liveins: $v8m2
; RV32I-LABEL: name: sext_nxv16i16_nxv16i8
- ; RV32I: liveins: $v8
+ ; RV32I: liveins: $v8m2
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
@@ -405,7 +405,7 @@ body: |
; RV32I-NEXT: PseudoRET implicit $v8m4
;
; RV64I-LABEL: name: sext_nxv16i16_nxv16i8
- ; RV64I: liveins: $v8
+ ; RV64I: liveins: $v8m2
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
@@ -425,10 +425,10 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $v8
+ liveins: $v8m2
; RV32I-LABEL: name: sext_nxv16i32_nxv16i8
- ; RV32I: liveins: $v8
+ ; RV32I: liveins: $v8m2
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -437,7 +437,7 @@ body: |
; RV32I-NEXT: PseudoRET implicit $v8m8
;
; RV64I-LABEL: name: sext_nxv16i32_nxv16i8
- ; RV64I: liveins: $v8
+ ; RV64I: liveins: $v8m2
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -457,10 +457,10 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $v8
+ liveins: $v8m4
; RV32I-LABEL: name: sext_nxv32i16_nxv32i8
- ; RV32I: liveins: $v8
+ ; RV32I: liveins: $v8m4
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -469,7 +469,7 @@ body: |
; RV32I-NEXT: PseudoRET implicit $v8m8
;
; RV64I-LABEL: name: sext_nxv32i16_nxv32i8
- ; RV64I: liveins: $v8
+ ; RV64I: liveins: $v8m4
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -681,10 +681,10 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $v8
+ liveins: $v8m2
; RV32I-LABEL: name: sext_nxv8i32_nxv8i16
- ; RV32I: liveins: $v8
+ ; RV32I: liveins: $v8m2
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
@@ -693,7 +693,7 @@ body: |
; RV32I-NEXT: PseudoRET implicit $v8m4
;
; RV64I-LABEL: name: sext_nxv8i32_nxv8i16
- ; RV64I: liveins: $v8
+ ; RV64I: liveins: $v8m2
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
@@ -713,10 +713,10 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $v8
+ liveins: $v8m2
; RV32I-LABEL: name: sext_nxv8i64_nxv8i16
- ; RV32I: liveins: $v8
+ ; RV32I: liveins: $v8m2
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -725,7 +725,7 @@ body: |
; RV32I-NEXT: PseudoRET implicit $v8m8
;
; RV64I-LABEL: name: sext_nxv8i64_nxv8i16
- ; RV64I: liveins: $v8
+ ; RV64I: liveins: $v8m2
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -745,10 +745,10 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $v8
+ liveins: $v8m4
; RV32I-LABEL: name: sext_nxv16i32_nxv16i16
- ; RV32I: liveins: $v8
+ ; RV32I: liveins: $v8m4
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -757,7 +757,7 @@ body: |
; RV32I-NEXT: PseudoRET implicit $v8m8
;
; RV64I-LABEL: name: sext_nxv16i32_nxv16i16
- ; RV64I: liveins: $v8
+ ; RV64I: liveins: $v8m4
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -841,10 +841,10 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $v8
+ liveins: $v8m2
; RV32I-LABEL: name: sext_nxv4i64_nxv4i32
- ; RV32I: liveins: $v8
+ ; RV32I: liveins: $v8m2
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
@@ -853,7 +853,7 @@ body: |
; RV32I-NEXT: PseudoRET implicit $v8m4
;
; RV64I-LABEL: name: sext_nxv4i64_nxv4i32
- ; RV64I: liveins: $v8
+ ; RV64I: liveins: $v8m2
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
@@ -873,10 +873,10 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $v8
+ liveins: $v8m4
; RV32I-LABEL: name: sext_nxv8i64_nxv8i32
- ; RV32I: liveins: $v8
+ ; RV32I: liveins: $v8m4
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -885,7 +885,7 @@ body: |
; RV32I-NEXT: PseudoRET implicit $v8m8
;
; RV64I-LABEL: name: sext_nxv8i64_nxv8i32
- ; RV64I: liveins: $v8
+ ; RV64I: liveins: $v8m4
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/zext.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/zext.mir
index 2fc9e05602a8b0..ad151b4d9c7fee 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/zext.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/zext.mir
@@ -393,10 +393,10 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $v8
+ liveins: $v8m2
; RV32I-LABEL: name: zext_nxv16i16_nxv16i8
- ; RV32I: liveins: $v8
+ ; RV32I: liveins: $v8m2
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
@@ -405,7 +405,7 @@ body: |
; RV32I-NEXT: PseudoRET implicit $v8m4
;
; RV64I-LABEL: name: zext_nxv16i16_nxv16i8
- ; RV64I: liveins: $v8
+ ; RV64I: liveins: $v8m2
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
@@ -425,10 +425,10 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $v8
+ liveins: $v8m2
; RV32I-LABEL: name: zext_nxv16i32_nxv16i8
- ; RV32I: liveins: $v8
+ ; RV32I: liveins: $v8m2
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -437,7 +437,7 @@ body: |
; RV32I-NEXT: PseudoRET implicit $v8m8
;
; RV64I-LABEL: name: zext_nxv16i32_nxv16i8
- ; RV64I: liveins: $v8
+ ; RV64I: liveins: $v8m2
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -457,10 +457,10 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $v8
+ liveins: $v8m4
; RV32I-LABEL: name: zext_nxv32i16_nxv32i8
- ; RV32I: liveins: $v8
+ ; RV32I: liveins: $v8m4
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -469,7 +469,7 @@ body: |
; RV32I-NEXT: PseudoRET implicit $v8m8
;
; RV64I-LABEL: name: zext_nxv32i16_nxv32i8
- ; RV64I: liveins: $v8
+ ; RV64I: liveins: $v8m4
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -681,10 +681,10 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $v8
+ liveins: $v8m2
; RV32I-LABEL: name: zext_nxv8i32_nxv8i16
- ; RV32I: liveins: $v8
+ ; RV32I: liveins: $v8m2
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
@@ -693,7 +693,7 @@ body: |
; RV32I-NEXT: PseudoRET implicit $v8m4
;
; RV64I-LABEL: name: zext_nxv8i32_nxv8i16
- ; RV64I: liveins: $v8
+ ; RV64I: liveins: $v8m2
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
@@ -713,26 +713,26 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $v8
+ liveins: $v8m2
; RV32I-LABEL: name: zext_nxv8i64_nxv8i16
- ; RV32I: liveins: $v8
+ ; RV32I: liveins: $v8m2
; RV32I-NEXT: {{ $}}
- ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m4
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */
; RV32I-NEXT: $v8m8 = COPY %1
; RV32I-NEXT: PseudoRET implicit $v8m8
;
; RV64I-LABEL: name: zext_nxv8i64_nxv8i16
- ; RV64I: liveins: $v8
+ ; RV64I: liveins: $v8m2
; RV64I-NEXT: {{ $}}
- ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m4
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */
; RV64I-NEXT: $v8m8 = COPY %1
; RV64I-NEXT: PseudoRET implicit $v8m8
- %0:vrb(<vscale x 8 x s16>) = COPY $v8m4
+ %0:vrb(<vscale x 8 x s16>) = COPY $v8m2
%1:vrb(<vscale x 8 x s64>) = G_ZEXT %0(<vscale x 8 x s16>)
$v8m8 = COPY %1(<vscale x 8 x s64>)
PseudoRET implicit $v8m8
@@ -745,10 +745,10 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $v8
+ liveins: $v8m4
; RV32I-LABEL: name: zext_nxv16i32_nxv16i16
- ; RV32I: liveins: $v8
+ ; RV32I: liveins: $v8m4
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -757,7 +757,7 @@ body: |
; RV32I-NEXT: PseudoRET implicit $v8m8
;
; RV64I-LABEL: name: zext_nxv16i32_nxv16i16
- ; RV64I: liveins: $v8
+ ; RV64I: liveins: $v8m4
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -841,10 +841,10 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $v8
+ liveins: $v8m2
; RV32I-LABEL: name: zext_nxv4i64_nxv4i32
- ; RV32I: liveins: $v8
+ ; RV32I: liveins: $v8m2
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
@@ -853,7 +853,7 @@ body: |
; RV32I-NEXT: PseudoRET implicit $v8m4
;
; RV64I-LABEL: name: zext_nxv4i64_nxv4i32
- ; RV64I: liveins: $v8
+ ; RV64I: liveins: $v8m2
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
@@ -873,10 +873,10 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $v8
+ liveins: $v8m4
; RV32I-LABEL: name: zext_nxv8i64_nxv8i32
- ; RV32I: liveins: $v8
+ ; RV32I: liveins: $v8m4
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -885,7 +885,7 @@ body: |
; RV32I-NEXT: PseudoRET implicit $v8m8
;
; RV64I-LABEL: name: zext_nxv8i64_nxv8i32
- ; RV64I: liveins: $v8
+ ; RV64I: liveins: $v8m4
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
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