[llvm] [SPIR-V] Rework usage of virtual registers' types and classes (PR #104104)

[Farzon Lotfi via llvm-commits]

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@@ -1451,3 +1438,61 @@ Register SPIRVGlobalRegistry::getOrCreateUndef(MachineInstr &I,
                                    *ST.getRegisterInfo(), *ST.getRegBankInfo());
   return Res;
 }
+
+const TargetRegisterClass *
+SPIRVGlobalRegistry::getRegClass(SPIRVType *SpvType) const {
+  unsigned Opcode = SpvType->getOpcode();
+  switch (Opcode) {
+  case SPIRV::OpTypeFloat:
+    return &SPIRV::fIDRegClass;
+  case SPIRV::OpTypePointer:
+    return &SPIRV::pIDRegClass;
+  case SPIRV::OpTypeVector: {
+    SPIRVType *ElemType = getSPIRVTypeForVReg(SpvType->getOperand(1).getReg());
+    unsigned ElemOpcode = ElemType ? ElemType->getOpcode() : 0;
+    if (ElemOpcode == SPIRV::OpTypeFloat)
+      return &SPIRV::vfIDRegClass;
+    if (ElemOpcode == SPIRV::OpTypePointer)
+      return &SPIRV::vpIDRegClass;
+    return &SPIRV::vIDRegClass;
+  }
+  }
+  return &SPIRV::iIDRegClass;
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farzonl wrote:

maybe add an assert for `SPIRV::OpTypeInt`?

https://github.com/llvm/llvm-project/pull/104104