[llvm] [X86] Shrink width of masked loads/stores (PR #105451)

[via llvm-commits]

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@@ -12128,6 +12128,24 @@ bool llvm::isAllOnesOrAllOnesSplat(SDValue N, bool AllowUndefs) {
   return C && C->isAllOnes() && C->getValueSizeInBits(0) == BitWidth;
 }
 
+APInt llvm::getDemandedEltsForMaskedOp(SDValue Mask, unsigned NumElts,
+                                       SmallVector<SDValue> *MaskEltsOut) {
+  if (!ISD::isBuildVectorOfConstantSDNodes(Mask.getNode()))
+    return APInt::getAllOnes(NumElts);
+  APInt Demanded = APInt::getZero(NumElts);
+  BuildVectorSDNode *MaskBV = cast<BuildVectorSDNode>(Mask);
+  for (unsigned i = 0; i < MaskBV->getNumOperands(); ++i) {
+    APInt V;
+    if (!sd_match(MaskBV->getOperand(i), m_ConstInt(V)))
+      return APInt::getAllOnes(NumElts);
+    if (V.isNegative())
----------------
goldsteinn wrote:

Negative is "more" correct I think.
For example:
```
  // If the mask value has been legalized to a non-boolean vector, try to
  // simplify ops leading up to it. We only demand the MSB of each lane.
  if (Mask.getScalarValueSizeInBits() != 1) {
    const TargetLowering &TLI = DAG.getTargetLoweringInfo();
    APInt DemandedBits(APInt::getSignMask(VT.getScalarSizeInBits()));
    if (TLI.SimplifyDemandedBits(Mask, DemandedBits, DCI)) {
      if (N->getOpcode() != ISD::DELETED_NODE)
        DCI.AddToWorklist(N);
      return SDValue(N, 0);
    }
    if (SDValue NewMask =
            TLI.SimplifyMultipleUseDemandedBits(Mask, DemandedBits, DAG))
      return DAG.getMaskedLoad(
          VT, SDLoc(N), Mld->getChain(), Mld->getBasePtr(), Mld->getOffset(),
          NewMask, Mld->getPassThru(), Mld->getMemoryVT(), Mld->getMemOperand(),
          Mld->getAddressingMode(), Mld->getExtensionType());
  }
```

https://github.com/llvm/llvm-project/pull/105451