[llvm] [X86] Allow speculative BSR/BSF instructions on targets with CMOV (PR #102885)

[Simon Pilgrim via llvm-commits]

RKSimon wrote:

> > Hmm, we already have TuningLZCNTFalseDeps - would it be worth a separate PR adding TuningBitScanFalseDeps and zeroing out the destination register?
> 
> FalseDep is somewhat incorrect, it preserves the destination so its an actual dep. Also FWIW Intel is going to change the documentation on BSF/BSR soon to state that it leaves the destination unchanged as opposed to undefined (i.e same as AMD).

In case Intel do make this change - I've started a patch that would allow us to support this behaviour pretty easily: https://github.com/RKSimon/llvm-project/tree/x86-bitscan-fallthrough

I'd like to get this PR in first though as long as nobody has any outstanding concerns.

https://github.com/llvm/llvm-project/pull/102885