[llvm] c9ba6d3 - [RISCV] Add coverage for fp reductions of <2^N-1 x FP> vectors
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 21 07:59:23 PDT 2024
Author: Philip Reames
Date: 2024-08-21T07:58:21-07:00
New Revision: c9ba6d35c19022a582516e9455af3f0d79101adf
URL: https://github.com/llvm/llvm-project/commit/c9ba6d35c19022a582516e9455af3f0d79101adf
DIFF: https://github.com/llvm/llvm-project/commit/c9ba6d35c19022a582516e9455af3f0d79101adf.diff
LOG: [RISCV] Add coverage for fp reductions of <2^N-1 x FP> vectors
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
index a6763fa22822ed..e9e147861df564 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
@@ -91,6 +91,26 @@ define half @vreduce_ord_fadd_v4f16(ptr %x, half %s) {
ret half %red
}
+declare half @llvm.vector.reduce.fadd.v7f16(half, <7 x half>)
+
+define half @vreduce_fadd_v7f16(ptr %x, half %s) {
+; CHECK-LABEL: vreduce_fadd_v7f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 7, e16, m1, ta, ma
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: lui a0, 1048568
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v9, 7
+; CHECK-NEXT: vfmv.s.f v9, fa0
+; CHECK-NEXT: vfredusum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <7 x half>, ptr %x
+ %red = call reassoc half @llvm.vector.reduce.fadd.v7f16(half %s, <7 x half> %v)
+ ret half %red
+}
+
declare half @llvm.vector.reduce.fadd.v8f16(half, <8 x half>)
define half @vreduce_fadd_v8f16(ptr %x, half %s) {
@@ -443,6 +463,45 @@ define float @vreduce_ord_fwadd_v4f32(ptr %x, float %s) {
ret float %red
}
+declare float @llvm.vector.reduce.fadd.v7f32(float, <7 x float>)
+
+define float @vreduce_fadd_v7f32(ptr %x, float %s) {
+; CHECK-LABEL: vreduce_fadd_v7f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: lui a0, 524288
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 7
+; CHECK-NEXT: vfmv.s.f v10, fa0
+; CHECK-NEXT: vfredusum.vs v8, v8, v10
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <7 x float>, ptr %x
+ %red = call reassoc float @llvm.vector.reduce.fadd.v7f32(float %s, <7 x float> %v)
+ ret float %red
+}
+
+define float @vreduce_ord_fadd_v7f32(ptr %x, float %s) {
+; CHECK-LABEL: vreduce_ord_fadd_v7f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: lui a0, 524288
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 7
+; CHECK-NEXT: vfmv.s.f v10, fa0
+; CHECK-NEXT: vfredosum.vs v8, v8, v10
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <7 x float>, ptr %x
+ %red = call float @llvm.vector.reduce.fadd.v7f32(float %s, <7 x float> %v)
+ ret float %red
+}
+
+
declare float @llvm.vector.reduce.fadd.v8f32(float, <8 x float>)
define float @vreduce_fadd_v8f32(ptr %x, float %s) {
@@ -1250,6 +1309,26 @@ define float @vreduce_fmin_v4f32_nonans_noinfs(ptr %x) {
ret float %red
}
+declare float @llvm.vector.reduce.fmin.v7f32(<7 x float>)
+
+define float @vreduce_fmin_v7f32(ptr %x) {
+; CHECK-LABEL: vreduce_fmin_v7f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: lui a0, 523264
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: vmv.v.v v12, v8
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v12, v10, 7
+; CHECK-NEXT: vfredmin.vs v8, v12, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <7 x float>, ptr %x
+ %red = call float @llvm.vector.reduce.fmin.v7f32(<7 x float> %v)
+ ret float %red
+}
+
declare float @llvm.vector.reduce.fmin.v128f32(<128 x float>)
define float @vreduce_fmin_v128f32(ptr %x) {
@@ -1480,6 +1559,26 @@ define float @vreduce_fmax_v4f32_nonans_noinfs(ptr %x) {
ret float %red
}
+declare float @llvm.vector.reduce.fmax.v7f32(<7 x float>)
+
+define float @vreduce_fmax_v7f32(ptr %x) {
+; CHECK-LABEL: vreduce_fmax_v7f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: lui a0, 1047552
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: vmv.v.v v12, v8
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v12, v10, 7
+; CHECK-NEXT: vfredmax.vs v8, v12, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <7 x float>, ptr %x
+ %red = call float @llvm.vector.reduce.fmax.v7f32(<7 x float> %v)
+ ret float %red
+}
+
declare float @llvm.vector.reduce.fmax.v128f32(<128 x float>)
define float @vreduce_fmax_v128f32(ptr %x) {
@@ -1602,12 +1701,12 @@ define float @vreduce_fminimum_v2f32(ptr %x) {
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vv v9, v8, v8
; CHECK-NEXT: vcpop.m a0, v9
-; CHECK-NEXT: beqz a0, .LBB99_2
+; CHECK-NEXT: beqz a0, .LBB104_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lui a0, 523264
; CHECK-NEXT: fmv.w.x fa0, a0
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB99_2:
+; CHECK-NEXT: .LBB104_2:
; CHECK-NEXT: vfredmin.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@@ -1638,12 +1737,12 @@ define float @vreduce_fminimum_v4f32(ptr %x) {
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vv v9, v8, v8
; CHECK-NEXT: vcpop.m a0, v9
-; CHECK-NEXT: beqz a0, .LBB101_2
+; CHECK-NEXT: beqz a0, .LBB106_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lui a0, 523264
; CHECK-NEXT: fmv.w.x fa0, a0
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB101_2:
+; CHECK-NEXT: .LBB106_2:
; CHECK-NEXT: vfredmin.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@@ -1665,6 +1764,52 @@ define float @vreduce_fminimum_v4f32_nonans(ptr %x) {
ret float %red
}
+declare float @llvm.vector.reduce.fminimum.v7f32(<7 x float>)
+
+define float @vreduce_fminimum_v7f32(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v7f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: lui a0, 522240
+; CHECK-NEXT: vmv.s.x v12, a0
+; CHECK-NEXT: vmv.v.v v10, v8
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v10, v12, 7
+; CHECK-NEXT: vmfne.vv v9, v10, v10
+; CHECK-NEXT: vcpop.m a0, v9
+; CHECK-NEXT: beqz a0, .LBB108_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: lui a0, 523264
+; CHECK-NEXT: fmv.w.x fa0, a0
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB108_2:
+; CHECK-NEXT: vfredmin.vs v8, v10, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <7 x float>, ptr %x
+ %red = call float @llvm.vector.reduce.fminimum.v7f32(<7 x float> %v)
+ ret float %red
+}
+
+define float @vreduce_fminimum_v7f32_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v7f32_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: lui a0, 522240
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: vmv.v.v v12, v8
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v12, v10, 7
+; CHECK-NEXT: vfredmin.vs v8, v12, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <7 x float>, ptr %x
+ %red = call nnan float @llvm.vector.reduce.fminimum.v7f32(<7 x float> %v)
+ ret float %red
+}
+
declare float @llvm.vector.reduce.fminimum.v8f32(<8 x float>)
define float @vreduce_fminimum_v8f32(ptr %x) {
@@ -1674,12 +1819,12 @@ define float @vreduce_fminimum_v8f32(ptr %x) {
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vv v10, v8, v8
; CHECK-NEXT: vcpop.m a0, v10
-; CHECK-NEXT: beqz a0, .LBB103_2
+; CHECK-NEXT: beqz a0, .LBB110_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lui a0, 523264
; CHECK-NEXT: fmv.w.x fa0, a0
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB103_2:
+; CHECK-NEXT: .LBB110_2:
; CHECK-NEXT: vfredmin.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@@ -1710,12 +1855,12 @@ define float @vreduce_fminimum_v16f32(ptr %x) {
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vv v12, v8, v8
; CHECK-NEXT: vcpop.m a0, v12
-; CHECK-NEXT: beqz a0, .LBB105_2
+; CHECK-NEXT: beqz a0, .LBB112_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lui a0, 523264
; CHECK-NEXT: fmv.w.x fa0, a0
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB105_2:
+; CHECK-NEXT: .LBB112_2:
; CHECK-NEXT: vfredmin.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@@ -1747,12 +1892,12 @@ define float @vreduce_fminimum_v32f32(ptr %x) {
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vv v16, v8, v8
; CHECK-NEXT: vcpop.m a0, v16
-; CHECK-NEXT: beqz a0, .LBB107_2
+; CHECK-NEXT: beqz a0, .LBB114_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lui a0, 523264
; CHECK-NEXT: fmv.w.x fa0, a0
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB107_2:
+; CHECK-NEXT: .LBB114_2:
; CHECK-NEXT: vfredmin.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@@ -1802,15 +1947,15 @@ define float @vreduce_fminimum_v64f32(ptr %x) {
; CHECK-NEXT: vfmin.vv v8, v8, v16
; CHECK-NEXT: vmfne.vv v16, v8, v8
; CHECK-NEXT: vcpop.m a0, v16
-; CHECK-NEXT: beqz a0, .LBB109_2
+; CHECK-NEXT: beqz a0, .LBB116_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lui a0, 523264
; CHECK-NEXT: fmv.w.x fa0, a0
-; CHECK-NEXT: j .LBB109_3
-; CHECK-NEXT: .LBB109_2:
+; CHECK-NEXT: j .LBB116_3
+; CHECK-NEXT: .LBB116_2:
; CHECK-NEXT: vfredmin.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: .LBB109_3:
+; CHECK-NEXT: .LBB116_3:
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0
@@ -1924,15 +2069,15 @@ define float @vreduce_fminimum_v128f32(ptr %x) {
; CHECK-NEXT: vfmin.vv v8, v8, v16
; CHECK-NEXT: vmfne.vv v16, v8, v8
; CHECK-NEXT: vcpop.m a0, v16
-; CHECK-NEXT: beqz a0, .LBB111_2
+; CHECK-NEXT: beqz a0, .LBB118_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lui a0, 523264
; CHECK-NEXT: fmv.w.x fa0, a0
-; CHECK-NEXT: j .LBB111_3
-; CHECK-NEXT: .LBB111_2:
+; CHECK-NEXT: j .LBB118_3
+; CHECK-NEXT: .LBB118_2:
; CHECK-NEXT: vfredmin.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: .LBB111_3:
+; CHECK-NEXT: .LBB118_3:
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: mv a1, a0
@@ -1978,12 +2123,12 @@ define double @vreduce_fminimum_v2f64(ptr %x) {
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfne.vv v9, v8, v8
; CHECK-NEXT: vcpop.m a0, v9
-; CHECK-NEXT: beqz a0, .LBB113_2
+; CHECK-NEXT: beqz a0, .LBB120_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: lui a0, %hi(.LCPI113_0)
-; CHECK-NEXT: fld fa0, %lo(.LCPI113_0)(a0)
+; CHECK-NEXT: lui a0, %hi(.LCPI120_0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI120_0)(a0)
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB113_2:
+; CHECK-NEXT: .LBB120_2:
; CHECK-NEXT: vfredmin.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@@ -2014,12 +2159,12 @@ define double @vreduce_fminimum_v4f64(ptr %x) {
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfne.vv v10, v8, v8
; CHECK-NEXT: vcpop.m a0, v10
-; CHECK-NEXT: beqz a0, .LBB115_2
+; CHECK-NEXT: beqz a0, .LBB122_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: lui a0, %hi(.LCPI115_0)
-; CHECK-NEXT: fld fa0, %lo(.LCPI115_0)(a0)
+; CHECK-NEXT: lui a0, %hi(.LCPI122_0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI122_0)(a0)
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB115_2:
+; CHECK-NEXT: .LBB122_2:
; CHECK-NEXT: vfredmin.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@@ -2050,12 +2195,12 @@ define double @vreduce_fminimum_v8f64(ptr %x) {
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfne.vv v12, v8, v8
; CHECK-NEXT: vcpop.m a0, v12
-; CHECK-NEXT: beqz a0, .LBB117_2
+; CHECK-NEXT: beqz a0, .LBB124_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: lui a0, %hi(.LCPI117_0)
-; CHECK-NEXT: fld fa0, %lo(.LCPI117_0)(a0)
+; CHECK-NEXT: lui a0, %hi(.LCPI124_0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI124_0)(a0)
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB117_2:
+; CHECK-NEXT: .LBB124_2:
; CHECK-NEXT: vfredmin.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@@ -2086,12 +2231,12 @@ define double @vreduce_fminimum_v16f64(ptr %x) {
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfne.vv v16, v8, v8
; CHECK-NEXT: vcpop.m a0, v16
-; CHECK-NEXT: beqz a0, .LBB119_2
+; CHECK-NEXT: beqz a0, .LBB126_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: lui a0, %hi(.LCPI119_0)
-; CHECK-NEXT: fld fa0, %lo(.LCPI119_0)(a0)
+; CHECK-NEXT: lui a0, %hi(.LCPI126_0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI126_0)(a0)
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB119_2:
+; CHECK-NEXT: .LBB126_2:
; CHECK-NEXT: vfredmin.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@@ -2139,15 +2284,15 @@ define double @vreduce_fminimum_v32f64(ptr %x) {
; CHECK-NEXT: vfmin.vv v8, v8, v16
; CHECK-NEXT: vmfne.vv v16, v8, v8
; CHECK-NEXT: vcpop.m a0, v16
-; CHECK-NEXT: beqz a0, .LBB121_2
+; CHECK-NEXT: beqz a0, .LBB128_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: lui a0, %hi(.LCPI121_0)
-; CHECK-NEXT: fld fa0, %lo(.LCPI121_0)(a0)
-; CHECK-NEXT: j .LBB121_3
-; CHECK-NEXT: .LBB121_2:
+; CHECK-NEXT: lui a0, %hi(.LCPI128_0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI128_0)(a0)
+; CHECK-NEXT: j .LBB128_3
+; CHECK-NEXT: .LBB128_2:
; CHECK-NEXT: vfredmin.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: .LBB121_3:
+; CHECK-NEXT: .LBB128_3:
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0
@@ -2259,15 +2404,15 @@ define double @vreduce_fminimum_v64f64(ptr %x) {
; CHECK-NEXT: vfmin.vv v8, v8, v16
; CHECK-NEXT: vmfne.vv v16, v8, v8
; CHECK-NEXT: vcpop.m a0, v16
-; CHECK-NEXT: beqz a0, .LBB123_2
+; CHECK-NEXT: beqz a0, .LBB130_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: lui a0, %hi(.LCPI123_0)
-; CHECK-NEXT: fld fa0, %lo(.LCPI123_0)(a0)
-; CHECK-NEXT: j .LBB123_3
-; CHECK-NEXT: .LBB123_2:
+; CHECK-NEXT: lui a0, %hi(.LCPI130_0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI130_0)(a0)
+; CHECK-NEXT: j .LBB130_3
+; CHECK-NEXT: .LBB130_2:
; CHECK-NEXT: vfredmin.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: .LBB123_3:
+; CHECK-NEXT: .LBB130_3:
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: mv a1, a0
@@ -2312,12 +2457,12 @@ define float @vreduce_fmaximum_v2f32(ptr %x) {
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vv v9, v8, v8
; CHECK-NEXT: vcpop.m a0, v9
-; CHECK-NEXT: beqz a0, .LBB125_2
+; CHECK-NEXT: beqz a0, .LBB132_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lui a0, 523264
; CHECK-NEXT: fmv.w.x fa0, a0
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB125_2:
+; CHECK-NEXT: .LBB132_2:
; CHECK-NEXT: vfredmax.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@@ -2348,12 +2493,12 @@ define float @vreduce_fmaximum_v4f32(ptr %x) {
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vv v9, v8, v8
; CHECK-NEXT: vcpop.m a0, v9
-; CHECK-NEXT: beqz a0, .LBB127_2
+; CHECK-NEXT: beqz a0, .LBB134_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lui a0, 523264
; CHECK-NEXT: fmv.w.x fa0, a0
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB127_2:
+; CHECK-NEXT: .LBB134_2:
; CHECK-NEXT: vfredmax.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@@ -2375,6 +2520,52 @@ define float @vreduce_fmaximum_v4f32_nonans(ptr %x) {
ret float %red
}
+declare float @llvm.vector.reduce.fmaximum.v7f32(<7 x float>)
+
+define float @vreduce_fmaximum_v7f32(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v7f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: lui a0, 1046528
+; CHECK-NEXT: vmv.s.x v12, a0
+; CHECK-NEXT: vmv.v.v v10, v8
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v10, v12, 7
+; CHECK-NEXT: vmfne.vv v9, v10, v10
+; CHECK-NEXT: vcpop.m a0, v9
+; CHECK-NEXT: beqz a0, .LBB136_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: lui a0, 523264
+; CHECK-NEXT: fmv.w.x fa0, a0
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB136_2:
+; CHECK-NEXT: vfredmax.vs v8, v10, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <7 x float>, ptr %x
+ %red = call float @llvm.vector.reduce.fmaximum.v7f32(<7 x float> %v)
+ ret float %red
+}
+
+define float @vreduce_fmaximum_v7f32_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v7f32_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: lui a0, 1046528
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: vmv.v.v v12, v8
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v12, v10, 7
+; CHECK-NEXT: vfredmax.vs v8, v12, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <7 x float>, ptr %x
+ %red = call nnan float @llvm.vector.reduce.fmaximum.v7f32(<7 x float> %v)
+ ret float %red
+}
+
declare float @llvm.vector.reduce.fmaximum.v8f32(<8 x float>)
define float @vreduce_fmaximum_v8f32(ptr %x) {
@@ -2384,12 +2575,12 @@ define float @vreduce_fmaximum_v8f32(ptr %x) {
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vv v10, v8, v8
; CHECK-NEXT: vcpop.m a0, v10
-; CHECK-NEXT: beqz a0, .LBB129_2
+; CHECK-NEXT: beqz a0, .LBB138_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lui a0, 523264
; CHECK-NEXT: fmv.w.x fa0, a0
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB129_2:
+; CHECK-NEXT: .LBB138_2:
; CHECK-NEXT: vfredmax.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@@ -2420,12 +2611,12 @@ define float @vreduce_fmaximum_v16f32(ptr %x) {
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vv v12, v8, v8
; CHECK-NEXT: vcpop.m a0, v12
-; CHECK-NEXT: beqz a0, .LBB131_2
+; CHECK-NEXT: beqz a0, .LBB140_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lui a0, 523264
; CHECK-NEXT: fmv.w.x fa0, a0
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB131_2:
+; CHECK-NEXT: .LBB140_2:
; CHECK-NEXT: vfredmax.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@@ -2457,12 +2648,12 @@ define float @vreduce_fmaximum_v32f32(ptr %x) {
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vv v16, v8, v8
; CHECK-NEXT: vcpop.m a0, v16
-; CHECK-NEXT: beqz a0, .LBB133_2
+; CHECK-NEXT: beqz a0, .LBB142_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lui a0, 523264
; CHECK-NEXT: fmv.w.x fa0, a0
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB133_2:
+; CHECK-NEXT: .LBB142_2:
; CHECK-NEXT: vfredmax.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@@ -2512,15 +2703,15 @@ define float @vreduce_fmaximum_v64f32(ptr %x) {
; CHECK-NEXT: vfmax.vv v8, v8, v16
; CHECK-NEXT: vmfne.vv v16, v8, v8
; CHECK-NEXT: vcpop.m a0, v16
-; CHECK-NEXT: beqz a0, .LBB135_2
+; CHECK-NEXT: beqz a0, .LBB144_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lui a0, 523264
; CHECK-NEXT: fmv.w.x fa0, a0
-; CHECK-NEXT: j .LBB135_3
-; CHECK-NEXT: .LBB135_2:
+; CHECK-NEXT: j .LBB144_3
+; CHECK-NEXT: .LBB144_2:
; CHECK-NEXT: vfredmax.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: .LBB135_3:
+; CHECK-NEXT: .LBB144_3:
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0
@@ -2634,15 +2825,15 @@ define float @vreduce_fmaximum_v128f32(ptr %x) {
; CHECK-NEXT: vfmax.vv v8, v8, v16
; CHECK-NEXT: vmfne.vv v16, v8, v8
; CHECK-NEXT: vcpop.m a0, v16
-; CHECK-NEXT: beqz a0, .LBB137_2
+; CHECK-NEXT: beqz a0, .LBB146_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lui a0, 523264
; CHECK-NEXT: fmv.w.x fa0, a0
-; CHECK-NEXT: j .LBB137_3
-; CHECK-NEXT: .LBB137_2:
+; CHECK-NEXT: j .LBB146_3
+; CHECK-NEXT: .LBB146_2:
; CHECK-NEXT: vfredmax.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: .LBB137_3:
+; CHECK-NEXT: .LBB146_3:
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: mv a1, a0
@@ -2688,12 +2879,12 @@ define double @vreduce_fmaximum_v2f64(ptr %x) {
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfne.vv v9, v8, v8
; CHECK-NEXT: vcpop.m a0, v9
-; CHECK-NEXT: beqz a0, .LBB139_2
+; CHECK-NEXT: beqz a0, .LBB148_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: lui a0, %hi(.LCPI139_0)
-; CHECK-NEXT: fld fa0, %lo(.LCPI139_0)(a0)
+; CHECK-NEXT: lui a0, %hi(.LCPI148_0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI148_0)(a0)
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB139_2:
+; CHECK-NEXT: .LBB148_2:
; CHECK-NEXT: vfredmax.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@@ -2724,12 +2915,12 @@ define double @vreduce_fmaximum_v4f64(ptr %x) {
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfne.vv v10, v8, v8
; CHECK-NEXT: vcpop.m a0, v10
-; CHECK-NEXT: beqz a0, .LBB141_2
+; CHECK-NEXT: beqz a0, .LBB150_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: lui a0, %hi(.LCPI141_0)
-; CHECK-NEXT: fld fa0, %lo(.LCPI141_0)(a0)
+; CHECK-NEXT: lui a0, %hi(.LCPI150_0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI150_0)(a0)
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB141_2:
+; CHECK-NEXT: .LBB150_2:
; CHECK-NEXT: vfredmax.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@@ -2760,12 +2951,12 @@ define double @vreduce_fmaximum_v8f64(ptr %x) {
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfne.vv v12, v8, v8
; CHECK-NEXT: vcpop.m a0, v12
-; CHECK-NEXT: beqz a0, .LBB143_2
+; CHECK-NEXT: beqz a0, .LBB152_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: lui a0, %hi(.LCPI143_0)
-; CHECK-NEXT: fld fa0, %lo(.LCPI143_0)(a0)
+; CHECK-NEXT: lui a0, %hi(.LCPI152_0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI152_0)(a0)
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB143_2:
+; CHECK-NEXT: .LBB152_2:
; CHECK-NEXT: vfredmax.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@@ -2796,12 +2987,12 @@ define double @vreduce_fmaximum_v16f64(ptr %x) {
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfne.vv v16, v8, v8
; CHECK-NEXT: vcpop.m a0, v16
-; CHECK-NEXT: beqz a0, .LBB145_2
+; CHECK-NEXT: beqz a0, .LBB154_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: lui a0, %hi(.LCPI145_0)
-; CHECK-NEXT: fld fa0, %lo(.LCPI145_0)(a0)
+; CHECK-NEXT: lui a0, %hi(.LCPI154_0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI154_0)(a0)
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB145_2:
+; CHECK-NEXT: .LBB154_2:
; CHECK-NEXT: vfredmax.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@@ -2849,15 +3040,15 @@ define double @vreduce_fmaximum_v32f64(ptr %x) {
; CHECK-NEXT: vfmax.vv v8, v8, v16
; CHECK-NEXT: vmfne.vv v16, v8, v8
; CHECK-NEXT: vcpop.m a0, v16
-; CHECK-NEXT: beqz a0, .LBB147_2
+; CHECK-NEXT: beqz a0, .LBB156_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: lui a0, %hi(.LCPI147_0)
-; CHECK-NEXT: fld fa0, %lo(.LCPI147_0)(a0)
-; CHECK-NEXT: j .LBB147_3
-; CHECK-NEXT: .LBB147_2:
+; CHECK-NEXT: lui a0, %hi(.LCPI156_0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI156_0)(a0)
+; CHECK-NEXT: j .LBB156_3
+; CHECK-NEXT: .LBB156_2:
; CHECK-NEXT: vfredmax.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: .LBB147_3:
+; CHECK-NEXT: .LBB156_3:
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0
@@ -2969,15 +3160,15 @@ define double @vreduce_fmaximum_v64f64(ptr %x) {
; CHECK-NEXT: vfmax.vv v8, v8, v16
; CHECK-NEXT: vmfne.vv v16, v8, v8
; CHECK-NEXT: vcpop.m a0, v16
-; CHECK-NEXT: beqz a0, .LBB149_2
+; CHECK-NEXT: beqz a0, .LBB158_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: lui a0, %hi(.LCPI149_0)
-; CHECK-NEXT: fld fa0, %lo(.LCPI149_0)(a0)
-; CHECK-NEXT: j .LBB149_3
-; CHECK-NEXT: .LBB149_2:
+; CHECK-NEXT: lui a0, %hi(.LCPI158_0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI158_0)(a0)
+; CHECK-NEXT: j .LBB158_3
+; CHECK-NEXT: .LBB158_2:
; CHECK-NEXT: vfredmax.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: .LBB149_3:
+; CHECK-NEXT: .LBB158_3:
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: mv a1, a0
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