[llvm] [AMDGPU] Split GCNSubtarget into its own file. NFC. (PR #105525)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 21 06:35:41 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Jay Foad (jayfoad)
<details>
<summary>Changes</summary>
---
Patch is 67.99 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/105525.diff
9 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp (-761)
- (modified) llvm/lib/Target/AMDGPU/CMakeLists.txt (+1)
- (added) llvm/lib/Target/AMDGPU/GCNSubtarget.cpp (+796)
- (modified) llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-any.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-disabled.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-enabled.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-any.ll (+7-7)
- (modified) llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-disabled.ll (+7-7)
- (modified) llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-enabled.ll (+7-7)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
index 2e1bdf46924783..67d8715d3f1c26 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
@@ -17,7 +17,6 @@
#include "AMDGPULegalizerInfo.h"
#include "AMDGPURegisterBankInfo.h"
#include "AMDGPUTargetMachine.h"
-#include "GCNSubtarget.h"
#include "R600Subtarget.h"
#include "SIMachineFunctionInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
@@ -36,308 +35,12 @@ using namespace llvm;
#define DEBUG_TYPE "amdgpu-subtarget"
-#define GET_SUBTARGETINFO_TARGET_DESC
-#define GET_SUBTARGETINFO_CTOR
-#define AMDGPUSubtarget GCNSubtarget
-#include "AMDGPUGenSubtargetInfo.inc"
-#undef AMDGPUSubtarget
-
-static cl::opt<bool> EnablePowerSched(
- "amdgpu-enable-power-sched",
- cl::desc("Enable scheduling to minimize mAI power bursts"),
- cl::init(false));
-
-static cl::opt<bool> EnableVGPRIndexMode(
- "amdgpu-vgpr-index-mode",
- cl::desc("Use GPR indexing mode instead of movrel for vector indexing"),
- cl::init(false));
-
-static cl::opt<bool> UseAA("amdgpu-use-aa-in-codegen",
- cl::desc("Enable the use of AA during codegen."),
- cl::init(true));
-
-static cl::opt<unsigned> NSAThreshold("amdgpu-nsa-threshold",
- cl::desc("Number of addresses from which to enable MIMG NSA."),
- cl::init(3), cl::Hidden);
-
-GCNSubtarget::~GCNSubtarget() = default;
-
-GCNSubtarget &
-GCNSubtarget::initializeSubtargetDependencies(const Triple &TT,
- StringRef GPU, StringRef FS) {
- // Determine default and user-specified characteristics
- //
- // We want to be able to turn these off, but making this a subtarget feature
- // for SI has the unhelpful behavior that it unsets everything else if you
- // disable it.
- //
- // Similarly we want enable-prt-strict-null to be on by default and not to
- // unset everything else if it is disabled
-
- SmallString<256> FullFS("+promote-alloca,+load-store-opt,+enable-ds128,");
-
- // Turn on features that HSA ABI requires. Also turn on FlatForGlobal by default
- if (isAmdHsaOS())
- FullFS += "+flat-for-global,+unaligned-access-mode,+trap-handler,";
-
- FullFS += "+enable-prt-strict-null,"; // This is overridden by a disable in FS
-
- // Disable mutually exclusive bits.
- if (FS.contains_insensitive("+wavefrontsize")) {
- if (!FS.contains_insensitive("wavefrontsize16"))
- FullFS += "-wavefrontsize16,";
- if (!FS.contains_insensitive("wavefrontsize32"))
- FullFS += "-wavefrontsize32,";
- if (!FS.contains_insensitive("wavefrontsize64"))
- FullFS += "-wavefrontsize64,";
- }
-
- FullFS += FS;
-
- ParseSubtargetFeatures(GPU, /*TuneCPU*/ GPU, FullFS);
-
- // Implement the "generic" processors, which acts as the default when no
- // generation features are enabled (e.g for -mcpu=''). HSA OS defaults to
- // the first amdgcn target that supports flat addressing. Other OSes defaults
- // to the first amdgcn target.
- if (Gen == AMDGPUSubtarget::INVALID) {
- Gen = TT.getOS() == Triple::AMDHSA ? AMDGPUSubtarget::SEA_ISLANDS
- : AMDGPUSubtarget::SOUTHERN_ISLANDS;
- }
-
- if (!hasFeature(AMDGPU::FeatureWavefrontSize32) &&
- !hasFeature(AMDGPU::FeatureWavefrontSize64)) {
- // If there is no default wave size it must be a generation before gfx10,
- // these have FeatureWavefrontSize64 in their definition already. For gfx10+
- // set wave32 as a default.
- ToggleFeature(AMDGPU::FeatureWavefrontSize32);
- }
-
- // We don't support FP64 for EG/NI atm.
- assert(!hasFP64() || (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS));
-
- // Targets must either support 64-bit offsets for MUBUF instructions, and/or
- // support flat operations, otherwise they cannot access a 64-bit global
- // address space
- assert(hasAddr64() || hasFlat());
- // Unless +-flat-for-global is specified, turn on FlatForGlobal for targets
- // that do not support ADDR64 variants of MUBUF instructions. Such targets
- // cannot use a 64 bit offset with a MUBUF instruction to access the global
- // address space
- if (!hasAddr64() && !FS.contains("flat-for-global") && !FlatForGlobal) {
- ToggleFeature(AMDGPU::FeatureFlatForGlobal);
- FlatForGlobal = true;
- }
- // Unless +-flat-for-global is specified, use MUBUF instructions for global
- // address space access if flat operations are not available.
- if (!hasFlat() && !FS.contains("flat-for-global") && FlatForGlobal) {
- ToggleFeature(AMDGPU::FeatureFlatForGlobal);
- FlatForGlobal = false;
- }
-
- // Set defaults if needed.
- if (MaxPrivateElementSize == 0)
- MaxPrivateElementSize = 4;
-
- if (LDSBankCount == 0)
- LDSBankCount = 32;
-
- if (TT.getArch() == Triple::amdgcn) {
- if (LocalMemorySize == 0)
- LocalMemorySize = 32768;
-
- // Do something sensible for unspecified target.
- if (!HasMovrel && !HasVGPRIndexMode)
- HasMovrel = true;
- }
-
- AddressableLocalMemorySize = LocalMemorySize;
-
- if (AMDGPU::isGFX10Plus(*this) &&
- !getFeatureBits().test(AMDGPU::FeatureCuMode))
- LocalMemorySize *= 2;
-
- // Don't crash on invalid devices.
- if (WavefrontSizeLog2 == 0)
- WavefrontSizeLog2 = 5;
-
- HasFminFmaxLegacy = getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS;
- HasSMulHi = getGeneration() >= AMDGPUSubtarget::GFX9;
-
- TargetID.setTargetIDFromFeaturesString(FS);
-
- LLVM_DEBUG(dbgs() << "xnack setting for subtarget: "
- << TargetID.getXnackSetting() << '\n');
- LLVM_DEBUG(dbgs() << "sramecc setting for subtarget: "
- << TargetID.getSramEccSetting() << '\n');
-
- return *this;
-}
-
-void GCNSubtarget::checkSubtargetFeatures(const Function &F) const {
- LLVMContext &Ctx = F.getContext();
- if (hasFeature(AMDGPU::FeatureWavefrontSize32) ==
- hasFeature(AMDGPU::FeatureWavefrontSize64)) {
- Ctx.diagnose(DiagnosticInfoUnsupported(
- F, "must specify exactly one of wavefrontsize32 and wavefrontsize64"));
- }
-}
-
AMDGPUSubtarget::AMDGPUSubtarget(Triple TT) : TargetTriple(std::move(TT)) {}
bool AMDGPUSubtarget::useRealTrue16Insts() const {
return hasTrue16BitInsts() && EnableRealTrue16Insts;
}
-GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
- const GCNTargetMachine &TM)
- : // clang-format off
- AMDGPUGenSubtargetInfo(TT, GPU, /*TuneCPU*/ GPU, FS),
- AMDGPUSubtarget(TT),
- TargetTriple(TT),
- TargetID(*this),
- InstrItins(getInstrItineraryForCPU(GPU)),
- InstrInfo(initializeSubtargetDependencies(TT, GPU, FS)),
- TLInfo(TM, *this),
- FrameLowering(TargetFrameLowering::StackGrowsUp, getStackAlignment(), 0) {
- // clang-format on
- MaxWavesPerEU = AMDGPU::IsaInfo::getMaxWavesPerEU(this);
- EUsPerCU = AMDGPU::IsaInfo::getEUsPerCU(this);
- CallLoweringInfo = std::make_unique<AMDGPUCallLowering>(*getTargetLowering());
- InlineAsmLoweringInfo =
- std::make_unique<InlineAsmLowering>(getTargetLowering());
- Legalizer = std::make_unique<AMDGPULegalizerInfo>(*this, TM);
- RegBankInfo = std::make_unique<AMDGPURegisterBankInfo>(*this);
- InstSelector =
- std::make_unique<AMDGPUInstructionSelector>(*this, *RegBankInfo, TM);
-}
-
-unsigned GCNSubtarget::getConstantBusLimit(unsigned Opcode) const {
- if (getGeneration() < GFX10)
- return 1;
-
- switch (Opcode) {
- case AMDGPU::V_LSHLREV_B64_e64:
- case AMDGPU::V_LSHLREV_B64_gfx10:
- case AMDGPU::V_LSHLREV_B64_e64_gfx11:
- case AMDGPU::V_LSHLREV_B64_e32_gfx12:
- case AMDGPU::V_LSHLREV_B64_e64_gfx12:
- case AMDGPU::V_LSHL_B64_e64:
- case AMDGPU::V_LSHRREV_B64_e64:
- case AMDGPU::V_LSHRREV_B64_gfx10:
- case AMDGPU::V_LSHRREV_B64_e64_gfx11:
- case AMDGPU::V_LSHRREV_B64_e64_gfx12:
- case AMDGPU::V_LSHR_B64_e64:
- case AMDGPU::V_ASHRREV_I64_e64:
- case AMDGPU::V_ASHRREV_I64_gfx10:
- case AMDGPU::V_ASHRREV_I64_e64_gfx11:
- case AMDGPU::V_ASHRREV_I64_e64_gfx12:
- case AMDGPU::V_ASHR_I64_e64:
- return 1;
- }
-
- return 2;
-}
-
-/// This list was mostly derived from experimentation.
-bool GCNSubtarget::zeroesHigh16BitsOfDest(unsigned Opcode) const {
- switch (Opcode) {
- case AMDGPU::V_CVT_F16_F32_e32:
- case AMDGPU::V_CVT_F16_F32_e64:
- case AMDGPU::V_CVT_F16_U16_e32:
- case AMDGPU::V_CVT_F16_U16_e64:
- case AMDGPU::V_CVT_F16_I16_e32:
- case AMDGPU::V_CVT_F16_I16_e64:
- case AMDGPU::V_RCP_F16_e64:
- case AMDGPU::V_RCP_F16_e32:
- case AMDGPU::V_RSQ_F16_e64:
- case AMDGPU::V_RSQ_F16_e32:
- case AMDGPU::V_SQRT_F16_e64:
- case AMDGPU::V_SQRT_F16_e32:
- case AMDGPU::V_LOG_F16_e64:
- case AMDGPU::V_LOG_F16_e32:
- case AMDGPU::V_EXP_F16_e64:
- case AMDGPU::V_EXP_F16_e32:
- case AMDGPU::V_SIN_F16_e64:
- case AMDGPU::V_SIN_F16_e32:
- case AMDGPU::V_COS_F16_e64:
- case AMDGPU::V_COS_F16_e32:
- case AMDGPU::V_FLOOR_F16_e64:
- case AMDGPU::V_FLOOR_F16_e32:
- case AMDGPU::V_CEIL_F16_e64:
- case AMDGPU::V_CEIL_F16_e32:
- case AMDGPU::V_TRUNC_F16_e64:
- case AMDGPU::V_TRUNC_F16_e32:
- case AMDGPU::V_RNDNE_F16_e64:
- case AMDGPU::V_RNDNE_F16_e32:
- case AMDGPU::V_FRACT_F16_e64:
- case AMDGPU::V_FRACT_F16_e32:
- case AMDGPU::V_FREXP_MANT_F16_e64:
- case AMDGPU::V_FREXP_MANT_F16_e32:
- case AMDGPU::V_FREXP_EXP_I16_F16_e64:
- case AMDGPU::V_FREXP_EXP_I16_F16_e32:
- case AMDGPU::V_LDEXP_F16_e64:
- case AMDGPU::V_LDEXP_F16_e32:
- case AMDGPU::V_LSHLREV_B16_e64:
- case AMDGPU::V_LSHLREV_B16_e32:
- case AMDGPU::V_LSHRREV_B16_e64:
- case AMDGPU::V_LSHRREV_B16_e32:
- case AMDGPU::V_ASHRREV_I16_e64:
- case AMDGPU::V_ASHRREV_I16_e32:
- case AMDGPU::V_ADD_U16_e64:
- case AMDGPU::V_ADD_U16_e32:
- case AMDGPU::V_SUB_U16_e64:
- case AMDGPU::V_SUB_U16_e32:
- case AMDGPU::V_SUBREV_U16_e64:
- case AMDGPU::V_SUBREV_U16_e32:
- case AMDGPU::V_MUL_LO_U16_e64:
- case AMDGPU::V_MUL_LO_U16_e32:
- case AMDGPU::V_ADD_F16_e64:
- case AMDGPU::V_ADD_F16_e32:
- case AMDGPU::V_SUB_F16_e64:
- case AMDGPU::V_SUB_F16_e32:
- case AMDGPU::V_SUBREV_F16_e64:
- case AMDGPU::V_SUBREV_F16_e32:
- case AMDGPU::V_MUL_F16_e64:
- case AMDGPU::V_MUL_F16_e32:
- case AMDGPU::V_MAX_F16_e64:
- case AMDGPU::V_MAX_F16_e32:
- case AMDGPU::V_MIN_F16_e64:
- case AMDGPU::V_MIN_F16_e32:
- case AMDGPU::V_MAX_U16_e64:
- case AMDGPU::V_MAX_U16_e32:
- case AMDGPU::V_MIN_U16_e64:
- case AMDGPU::V_MIN_U16_e32:
- case AMDGPU::V_MAX_I16_e64:
- case AMDGPU::V_MAX_I16_e32:
- case AMDGPU::V_MIN_I16_e64:
- case AMDGPU::V_MIN_I16_e32:
- case AMDGPU::V_MAD_F16_e64:
- case AMDGPU::V_MAD_U16_e64:
- case AMDGPU::V_MAD_I16_e64:
- case AMDGPU::V_FMA_F16_e64:
- case AMDGPU::V_DIV_FIXUP_F16_e64:
- // On gfx10, all 16-bit instructions preserve the high bits.
- return getGeneration() <= AMDGPUSubtarget::GFX9;
- case AMDGPU::V_MADAK_F16:
- case AMDGPU::V_MADMK_F16:
- case AMDGPU::V_MAC_F16_e64:
- case AMDGPU::V_MAC_F16_e32:
- case AMDGPU::V_FMAMK_F16:
- case AMDGPU::V_FMAAK_F16:
- case AMDGPU::V_FMAC_F16_e64:
- case AMDGPU::V_FMAC_F16_e32:
- // In gfx9, the preferred handling of the unused high 16-bits changed. Most
- // instructions maintain the legacy behavior of 0ing. Some instructions
- // changed to preserving the high bits.
- return getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS;
- case AMDGPU::V_MAD_MIXLO_F16:
- case AMDGPU::V_MAD_MIXHI_F16:
- default:
- return false;
- }
-}
-
// Returns the maximum per-workgroup LDS allocation size (in bytes) that still
// allows the given function to achieve an occupancy of NWaves waves per
// SIMD / EU, taking into account only the function's *maximum* workgroup size.
@@ -650,391 +353,6 @@ AMDGPUDwarfFlavour AMDGPUSubtarget::getAMDGPUDwarfFlavour() const {
: AMDGPUDwarfFlavour::Wave64;
}
-void GCNSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
- unsigned NumRegionInstrs) const {
- // Track register pressure so the scheduler can try to decrease
- // pressure once register usage is above the threshold defined by
- // SIRegisterInfo::getRegPressureSetLimit()
- Policy.ShouldTrackPressure = true;
-
- // Enabling both top down and bottom up scheduling seems to give us less
- // register spills than just using one of these approaches on its own.
- Policy.OnlyTopDown = false;
- Policy.OnlyBottomUp = false;
-
- // Enabling ShouldTrackLaneMasks crashes the SI Machine Scheduler.
- if (!enableSIScheduler())
- Policy.ShouldTrackLaneMasks = true;
-}
-
-void GCNSubtarget::mirFileLoaded(MachineFunction &MF) const {
- if (isWave32()) {
- // Fix implicit $vcc operands after MIParser has verified that they match
- // the instruction definitions.
- for (auto &MBB : MF) {
- for (auto &MI : MBB)
- InstrInfo.fixImplicitOperands(MI);
- }
- }
-}
-
-bool GCNSubtarget::hasMadF16() const {
- return InstrInfo.pseudoToMCOpcode(AMDGPU::V_MAD_F16_e64) != -1;
-}
-
-bool GCNSubtarget::useVGPRIndexMode() const {
- return !hasMovrel() || (EnableVGPRIndexMode && hasVGPRIndexMode());
-}
-
-bool GCNSubtarget::useAA() const { return UseAA; }
-
-unsigned GCNSubtarget::getOccupancyWithNumSGPRs(unsigned SGPRs) const {
- return AMDGPU::IsaInfo::getOccupancyWithNumSGPRs(SGPRs, getMaxWavesPerEU(),
- getGeneration());
-}
-
-unsigned GCNSubtarget::getOccupancyWithNumVGPRs(unsigned NumVGPRs) const {
- return AMDGPU::IsaInfo::getNumWavesPerEUWithNumVGPRs(this, NumVGPRs);
-}
-
-unsigned
-GCNSubtarget::getBaseReservedNumSGPRs(const bool HasFlatScratch) const {
- if (getGeneration() >= AMDGPUSubtarget::GFX10)
- return 2; // VCC. FLAT_SCRATCH and XNACK are no longer in SGPRs.
-
- if (HasFlatScratch || HasArchitectedFlatScratch) {
- if (getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
- return 6; // FLAT_SCRATCH, XNACK, VCC (in that order).
- if (getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
- return 4; // FLAT_SCRATCH, VCC (in that order).
- }
-
- if (isXNACKEnabled())
- return 4; // XNACK, VCC (in that order).
- return 2; // VCC.
-}
-
-unsigned GCNSubtarget::getReservedNumSGPRs(const MachineFunction &MF) const {
- const SIMachineFunctionInfo &MFI = *MF.getInfo<SIMachineFunctionInfo>();
- return getBaseReservedNumSGPRs(MFI.getUserSGPRInfo().hasFlatScratchInit());
-}
-
-unsigned GCNSubtarget::getReservedNumSGPRs(const Function &F) const {
- // In principle we do not need to reserve SGPR pair used for flat_scratch if
- // we know flat instructions do not access the stack anywhere in the
- // program. For now assume it's needed if we have flat instructions.
- const bool KernelUsesFlatScratch = hasFlatAddressSpace();
- return getBaseReservedNumSGPRs(KernelUsesFlatScratch);
-}
-
-unsigned GCNSubtarget::computeOccupancy(const Function &F, unsigned LDSSize,
- unsigned NumSGPRs,
- unsigned NumVGPRs) const {
- unsigned Occupancy =
- std::min(getMaxWavesPerEU(),
- getOccupancyWithLocalMemSize(LDSSize, F));
- if (NumSGPRs)
- Occupancy = std::min(Occupancy, getOccupancyWithNumSGPRs(NumSGPRs));
- if (NumVGPRs)
- Occupancy = std::min(Occupancy, getOccupancyWithNumVGPRs(NumVGPRs));
- return Occupancy;
-}
-
-unsigned GCNSubtarget::getBaseMaxNumSGPRs(
- const Function &F, std::pair<unsigned, unsigned> WavesPerEU,
- unsigned PreloadedSGPRs, unsigned ReservedNumSGPRs) const {
- // Compute maximum number of SGPRs function can use using default/requested
- // minimum number of waves per execution unit.
- unsigned MaxNumSGPRs = getMaxNumSGPRs(WavesPerEU.first, false);
- unsigned MaxAddressableNumSGPRs = getMaxNumSGPRs(WavesPerEU.first, true);
-
- // Check if maximum number of SGPRs was explicitly requested using
- // "amdgpu-num-sgpr" attribute.
- if (F.hasFnAttribute("amdgpu-num-sgpr")) {
- unsigned Requested =
- F.getFnAttributeAsParsedInteger("amdgpu-num-sgpr", MaxNumSGPRs);
-
- // Make sure requested value does not violate subtarget's specifications.
- if (Requested && (Requested <= ReservedNumSGPRs))
- Requested = 0;
-
- // If more SGPRs are required to support the input user/system SGPRs,
- // increase to accommodate them.
- //
- // FIXME: This really ends up using the requested number of SGPRs + number
- // of reserved special registers in total. Theoretically you could re-use
- // the last input registers for these special registers, but this would
- // require a lot of complexity to deal with the weird aliasing.
- unsigned InputNumSGPRs = PreloadedSGPRs;
- if (Requested && Requested < InputNumSGPRs)
- Requested = InputNumSGPRs;
-
- // Make sure requested value is compatible with values implied by
- // default/requested minimum/maximum number of waves per execution unit.
- if (Requested && Requested > getMaxNumSGPRs(WavesPerEU.first, false))
- Requested = 0;
- if (WavesPerEU.second &&
- Requested && Requested < getMinNumSGPRs(WavesPerEU.second))
- Requested = 0;
-
- if (Requested)
- MaxNumSGPRs = Requested;
- }
-
- if (hasSGPRInitBug())
- MaxNumSGPRs = AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
-
- return std::min(MaxNumSGPRs - ReservedNumSGPRs, MaxAddressableNumSGPRs);
-}
-
-unsigned GCNSubtarget::getMaxNumSGPRs(const MachineFunction &MF) const {
- const Function &F = MF.getFunction();
- const SIMachineFunctionInfo &MFI = *MF.getInfo<SIMachineFunctionInfo>();
- return getBaseMaxNumSGPRs(F, MFI.getWavesPerEU(), MFI.getNumPreloadedSGPRs(),
- getReservedNumSGPRs(MF));
-}
-
-static unsigned getMaxNumPreloadedSGPRs() {
- using USI = GCNUserSGPRUsageInfo;
- // Max number of user SGPRs
- const unsigned MaxUserSGPRs =
- USI::getNumUserSGPRForField(USI::PrivateSegmentBufferID) +
- USI::getNumUserSGPRForField(USI::DispatchPtrID) +
- USI::getNumUserSGPRForField(USI::QueuePtrID) +
- USI::getNumUserSGPRForField(USI::KernargSegmentPtrID) +
- USI::getNumUserSGPRForField(USI::DispatchIdID) +
- USI::getNumUserSGPRForField(USI::FlatScratchInitID) +
- USI::getNumUserSGPRForField(USI::ImplicitBufferPtrID);
-
- // Max number of system SGPRs
- const unsigned MaxSystemSGPRs = 1 + // WorkGroupIDX
- 1 + // WorkGroupIDY
- 1 + // WorkGroupIDZ
- 1 + // WorkGroupInfo
- 1; // private segment wave byte offset
-
- // Max number of synthetic SGPRs
- const unsigned SyntheticSGPRs = 1; // LDSKernelId
-
- return MaxUserSGPRs + MaxSystemSGPRs + SyntheticSGPRs;
-}
-
-unsigned GCNSubtarget::getMaxNumSGPRs(const Function &F) const {
- return getBaseMaxNumSGPRs(F, getWavesPerEU(F), getMaxNumPreloadedSGPRs(),
- getReservedNumSGPRs(F));
-}
-
-unsigned GCNSubtarget::getBaseMaxNumVGPRs(
- const Function &F, std::pair<unsigned, unsigned> WavesPerEU) const {
- // Compute maximum number of VGPRs function can use using default/requested
- // minimum number of waves per execution unit.
- unsigned MaxNumVGPRs = getMaxNumVGPRs(WavesPerEU.first);
-
- // Check if maximum number of VGPRs was explicitly requested using
- // "amdgpu-num-vgpr" attribute.
- if (F.hasFnAttribute("amdgpu-num-vgpr")) {
- unsigned Requested =
- F.getFnAttributeAsParsedInteger("amdgpu-num-vgpr", MaxNumVGPRs);
-
- if (hasGFX90AInsts())
- Requested *= 2;
-
- // Make sure requested value is compatible with values implied by
- // default/requested minimum/maximum number of waves per execution unit.
- if (Requested && Requested > getMaxNumVGPRs(WavesPerEU.first))
- Requested = 0;
- if (WavesPerEU.second &&
- Requested && Requested < getMinNumVGPRs(WavesPerEU.second))
- Requested = 0;
-
- if (Requested)
- MaxNumVGPRs = Requested;
- }
-
- return MaxNumVGPRs;
-}
-
-unsigned GCNSubtarget::getMaxNumVGPRs(const Function &F) const {
- return getBaseMaxNumVGPRs(F, getWavesPerEU(F));
-}
-
-unsigned GCNSubtarget::getMaxNumVGPRs(const MachineFunction &MF) const {
- const Function &F = MF.getFunction();
- const SIMachineFunctionInfo &MFI = *MF.getInfo<SIMachineFunctionInfo>();
- return getBaseMaxNumVGPRs(F, MFI.getWavesPerEU());
-...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/105525
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