[llvm] [AArch64]Fix invalid use of ld1/st1 in stack alloc (PR #105518)

[Sander de Smalen via llvm-commits]

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@@ -3354,10 +3360,21 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
           MachinePointerInfo::getFixedStack(MF, FrameIdxReg2),
           MachineMemOperand::MOStore, Size, Alignment));
       MIB.addReg(PnReg);
-      MIB.addReg(AArch64::SP)
-          .addImm(RPI.Offset) // [sp, #offset*scale],
-                              // where factor*scale is implicit
-          .setMIFlag(MachineInstr::FrameSetup);
+      MIB.addReg(AArch64::SP);
+      if (RPI.Offset >= -8 && RPI.Offset <= 7)
+        MIB.addImm(RPI.Offset);
+      else {
+        // When stack offset out of range for st1b scalar + imm variant,
+        // store offset in register for use in scalar + scalar variant.
+        Register ScratchReg = findScratchNonCalleeSaveRegister(&MBB);
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sdesmalen-arm wrote:

For the paired spills/fills where the offset is insufficient, it's probably simpler to just use the regular (single vector) spill/fill (LDR/STR) instructions, rather than having to find a scratch register and fiddle with the offsets.

https://github.com/llvm/llvm-project/pull/105518