[llvm] [AArch64]Fix invalid use of ld1/st1 in stack alloc (PR #105518)

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``````````bash
git-clang-format --diff 7efa068f7a7ed4f42ba09cce73e8c09bb8b4e8ce d7fbd115be1afc57c46973fd5ebd974151cac307 --extensions cpp -- llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index e2648ed1da..280c945ff1 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -3363,7 +3363,7 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
       MIB.addReg(AArch64::SP);
       if (RPI.Offset >= -8 && RPI.Offset <= 7)
         MIB.addImm(RPI.Offset);
-      else{
+      else {
         // When stack offset out of range for st1b scalar + imm variant,
         // store offset in register for use in scalar + scalar variant.
         Register ScratchReg = findScratchNonCalleeSaveRegister(&MBB);
@@ -3547,7 +3547,7 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters(
       MIB.addReg(AArch64::SP);
       if (RPI.Offset >= -8 && RPI.Offset <= 7)
         MIB.addImm(RPI.Offset);
-      else{
+      else {
         // When stack offset out of range for ld1b scalar + imm variant,
         // store offset in register for use in scalar + scalar variant.
         Register ScratchReg = findScratchNonCalleeSaveRegister(&MBB);

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https://github.com/llvm/llvm-project/pull/105518