[llvm] 2b84fe6 - RISC-V: Add fminimumnum and fmaximumnum support (#104411)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 20 18:10:58 PDT 2024
Author: YunQiang Su
Date: 2024-08-21T09:10:55+08:00
New Revision: 2b84fe6f16bf2beb78e48e40db3752143ded6228
URL: https://github.com/llvm/llvm-project/commit/2b84fe6f16bf2beb78e48e40db3752143ded6228
DIFF: https://github.com/llvm/llvm-project/commit/2b84fe6f16bf2beb78e48e40db3752143ded6228.diff
LOG: RISC-V: Add fminimumnum and fmaximumnum support (#104411)
Since 2.2, `fmin.s/fmax.s` instructions follow the IEEE754-2019, if F
extension is avaiable; and `fmin.d/fmax.d` also follow the IEEE754-2019
if D extension is avaiable.
So, let's mark them as Legal.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoD.td
llvm/lib/Target/RISCV/RISCVInstrInfoF.td
llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
llvm/test/CodeGen/RISCV/double-intrinsics.ll
llvm/test/CodeGen/RISCV/float-intrinsics.ll
llvm/test/CodeGen/RISCV/half-intrinsics.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 62980ae71d60b..66ea6423097ab 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -365,12 +365,13 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SELECT, XLenVT, Custom);
static const unsigned FPLegalNodeTypes[] = {
- ISD::FMINNUM, ISD::FMAXNUM, ISD::LRINT,
- ISD::LLRINT, ISD::LROUND, ISD::LLROUND,
- ISD::STRICT_LRINT, ISD::STRICT_LLRINT, ISD::STRICT_LROUND,
- ISD::STRICT_LLROUND, ISD::STRICT_FMA, ISD::STRICT_FADD,
- ISD::STRICT_FSUB, ISD::STRICT_FMUL, ISD::STRICT_FDIV,
- ISD::STRICT_FSQRT, ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS};
+ ISD::FMINNUM, ISD::FMAXNUM, ISD::FMINIMUMNUM,
+ ISD::FMAXIMUMNUM, ISD::LRINT, ISD::LLRINT,
+ ISD::LROUND, ISD::LLROUND, ISD::STRICT_LRINT,
+ ISD::STRICT_LLRINT, ISD::STRICT_LROUND, ISD::STRICT_LLROUND,
+ ISD::STRICT_FMA, ISD::STRICT_FADD, ISD::STRICT_FSUB,
+ ISD::STRICT_FMUL, ISD::STRICT_FDIV, ISD::STRICT_FSQRT,
+ ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS};
static const ISD::CondCode FPCCToExpand[] = {
ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT,
@@ -389,15 +390,20 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::BITCAST, MVT::i16, Custom);
static const unsigned ZfhminZfbfminPromoteOps[] = {
- ISD::FMINNUM, ISD::FMAXNUM, ISD::FADD,
- ISD::FSUB, ISD::FMUL, ISD::FMA,
- ISD::FDIV, ISD::FSQRT, ISD::FABS,
- ISD::FNEG, ISD::STRICT_FMA, ISD::STRICT_FADD,
- ISD::STRICT_FSUB, ISD::STRICT_FMUL, ISD::STRICT_FDIV,
- ISD::STRICT_FSQRT, ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS,
- ISD::SETCC, ISD::FCEIL, ISD::FFLOOR,
- ISD::FTRUNC, ISD::FRINT, ISD::FROUND,
- ISD::FROUNDEVEN, ISD::SELECT};
+ ISD::FMINNUM, ISD::FMAXNUM,
+ ISD::FMAXIMUMNUM, ISD::FMINIMUMNUM,
+ ISD::FADD, ISD::FSUB,
+ ISD::FMUL, ISD::FMA,
+ ISD::FDIV, ISD::FSQRT,
+ ISD::FABS, ISD::FNEG,
+ ISD::STRICT_FMA, ISD::STRICT_FADD,
+ ISD::STRICT_FSUB, ISD::STRICT_FMUL,
+ ISD::STRICT_FDIV, ISD::STRICT_FSQRT,
+ ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS,
+ ISD::SETCC, ISD::FCEIL,
+ ISD::FFLOOR, ISD::FTRUNC,
+ ISD::FRINT, ISD::FROUND,
+ ISD::FROUNDEVEN, ISD::SELECT};
if (Subtarget.hasStdExtZfbfmin()) {
setOperationAction(ISD::BITCAST, MVT::i16, Custom);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
index 35ab277fa3505..57c18791cc43b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
@@ -392,6 +392,8 @@ def : Pat<(fneg (any_fma_nsz FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3))
foreach Ext = DExts in {
defm : PatFprFpr_m<fminnum, FMIN_D, Ext>;
defm : PatFprFpr_m<fmaxnum, FMAX_D, Ext>;
+ defm : PatFprFpr_m<fminimumnum, FMIN_D, Ext>;
+ defm : PatFprFpr_m<fmaximumnum, FMAX_D, Ext>;
defm : PatFprFpr_m<riscv_fmin, FMIN_D, Ext>;
defm : PatFprFpr_m<riscv_fmax, FMAX_D, Ext>;
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
index e6c25e0844fb2..24a72f480f788 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -603,6 +603,8 @@ def : Pat<(fneg (any_fma_nsz FPR32INX:$rs1, FPR32INX:$rs2, FPR32INX:$rs3)),
foreach Ext = FExts in {
defm : PatFprFpr_m<fminnum, FMIN_S, Ext>;
defm : PatFprFpr_m<fmaxnum, FMAX_S, Ext>;
+ defm : PatFprFpr_m<fminimumnum, FMIN_S, Ext>;
+ defm : PatFprFpr_m<fmaximumnum, FMAX_S, Ext>;
defm : PatFprFpr_m<riscv_fmin, FMIN_S, Ext>;
defm : PatFprFpr_m<riscv_fmax, FMAX_S, Ext>;
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
index abdd366741eb0..6c5375bb927c5 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
@@ -347,6 +347,8 @@ def : Pat<(fneg (any_fma_nsz FPR16INX:$rs1, FPR16INX:$rs2, FPR16INX:$rs3)),
foreach Ext = ZfhExts in {
defm : PatFprFpr_m<fminnum, FMIN_H, Ext>;
defm : PatFprFpr_m<fmaxnum, FMAX_H, Ext>;
+ defm : PatFprFpr_m<fminimumnum, FMIN_H, Ext>;
+ defm : PatFprFpr_m<fmaximumnum, FMAX_H, Ext>;
defm : PatFprFpr_m<riscv_fmin, FMIN_H, Ext>;
defm : PatFprFpr_m<riscv_fmax, FMAX_H, Ext>;
}
diff --git a/llvm/test/CodeGen/RISCV/double-intrinsics.ll b/llvm/test/CodeGen/RISCV/double-intrinsics.ll
index 52c49cfbfb30a..eef48d1eafbfe 100644
--- a/llvm/test/CodeGen/RISCV/double-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/double-intrinsics.ll
@@ -1545,3 +1545,89 @@ define i1 @isnan_d_fpclass(double %x) {
%1 = call i1 @llvm.is.fpclass.f64(double %x, i32 3) ; nan
ret i1 %1
}
+
+declare double @llvm.maximumnum.f64(double, double)
+
+define double @maximumnum_double(double %x, double %y) {
+; CHECKIFD-LABEL: maximumnum_double:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fmax.d fa0, fa0, fa1
+; CHECKIFD-NEXT: ret
+;
+; RV32IZFINXZDINX-LABEL: maximumnum_double:
+; RV32IZFINXZDINX: # %bb.0:
+; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a2
+; RV32IZFINXZDINX-NEXT: ret
+;
+; RV64IZFINXZDINX-LABEL: maximumnum_double:
+; RV64IZFINXZDINX: # %bb.0:
+; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a1
+; RV64IZFINXZDINX-NEXT: ret
+;
+; RV32I-LABEL: maximumnum_double:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: call fmaximum_num
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: maximumnum_double:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: .cfi_def_cfa_offset 16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: call fmaximum_num
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+ %z = call double @llvm.maximumnum.f64(double %x, double %y)
+ ret double %z
+}
+
+declare double @llvm.minimumnum.f64(double, double)
+
+define double @minimumnum_double(double %x, double %y) {
+; CHECKIFD-LABEL: minimumnum_double:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fmin.d fa0, fa0, fa1
+; CHECKIFD-NEXT: ret
+;
+; RV32IZFINXZDINX-LABEL: minimumnum_double:
+; RV32IZFINXZDINX: # %bb.0:
+; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
+; RV32IZFINXZDINX-NEXT: ret
+;
+; RV64IZFINXZDINX-LABEL: minimumnum_double:
+; RV64IZFINXZDINX: # %bb.0:
+; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a1
+; RV64IZFINXZDINX-NEXT: ret
+;
+; RV32I-LABEL: minimumnum_double:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: call fminimum_num
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: minimumnum_double:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: .cfi_def_cfa_offset 16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: call fminimum_num
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+ %z = call double @llvm.minimumnum.f64(double %x, double %y)
+ ret double %z
+}
diff --git a/llvm/test/CodeGen/RISCV/float-intrinsics.ll b/llvm/test/CodeGen/RISCV/float-intrinsics.ll
index a00d82942cabe..918791423a3aa 100644
--- a/llvm/test/CodeGen/RISCV/float-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/float-intrinsics.ll
@@ -2185,3 +2185,99 @@ define i1 @isnotfinite_fpclass(float %x) {
%1 = call i1 @llvm.is.fpclass.f32(float %x, i32 519) ; ox207 = "inf|nan"
ret i1 %1
}
+
+declare float @llvm.maximumnum.f32(float, float)
+
+define float @maximumnum_float(float %x, float %y) {
+; RV32IF-LABEL: maximumnum_float:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmax.s fa0, fa0, fa1
+; RV32IF-NEXT: ret
+;
+; RV32IZFINX-LABEL: maximumnum_float:
+; RV32IZFINX: # %bb.0:
+; RV32IZFINX-NEXT: fmax.s a0, a0, a1
+; RV32IZFINX-NEXT: ret
+;
+; RV64IF-LABEL: maximumnum_float:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmax.s fa0, fa0, fa1
+; RV64IF-NEXT: ret
+;
+; RV64IZFINX-LABEL: maximumnum_float:
+; RV64IZFINX: # %bb.0:
+; RV64IZFINX-NEXT: fmax.s a0, a0, a1
+; RV64IZFINX-NEXT: ret
+;
+; RV32I-LABEL: maximumnum_float:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: call fmaximum_numf
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: maximumnum_float:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: .cfi_def_cfa_offset 16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: call fmaximum_numf
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+ %z = call float @llvm.maximumnum.f32(float %x, float %y)
+ ret float %z
+}
+
+declare float @llvm.minimumnum.f32(float, float)
+
+define float @minimumnum_float(float %x, float %y) {
+; RV32IF-LABEL: minimumnum_float:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmin.s fa0, fa0, fa1
+; RV32IF-NEXT: ret
+;
+; RV32IZFINX-LABEL: minimumnum_float:
+; RV32IZFINX: # %bb.0:
+; RV32IZFINX-NEXT: fmin.s a0, a0, a1
+; RV32IZFINX-NEXT: ret
+;
+; RV64IF-LABEL: minimumnum_float:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmin.s fa0, fa0, fa1
+; RV64IF-NEXT: ret
+;
+; RV64IZFINX-LABEL: minimumnum_float:
+; RV64IZFINX: # %bb.0:
+; RV64IZFINX-NEXT: fmin.s a0, a0, a1
+; RV64IZFINX-NEXT: ret
+;
+; RV32I-LABEL: minimumnum_float:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: call fminimum_numf
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: minimumnum_float:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: .cfi_def_cfa_offset 16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: call fminimum_numf
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+ %z = call float @llvm.minimumnum.f32(float %x, float %y)
+ ret float %z
+}
diff --git a/llvm/test/CodeGen/RISCV/half-intrinsics.ll b/llvm/test/CodeGen/RISCV/half-intrinsics.ll
index bfc26b0d65980..4587c442cda5b 100644
--- a/llvm/test/CodeGen/RISCV/half-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/half-intrinsics.ll
@@ -2982,3 +2982,191 @@ define half @tan_f16(half %a) nounwind {
%1 = call half @llvm.tan.f16(half %a)
ret half %1
}
+
+declare half @llvm.maximumnum.f16(half, half)
+
+define half @maximumnum_half(half %x, half %y) {
+; CHECKIZFH-LABEL: maximumnum_half:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fmax.h fa0, fa0, fa1
+; CHECKIZFH-NEXT: ret
+;
+; CHECKIZHINX-LABEL: maximumnum_half:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fmax.h a0, a0, a1
+; CHECKIZHINX-NEXT: ret
+;
+; RV32I-LABEL: maximumnum_half:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
+; RV32I-NEXT: .cfi_offset s1, -12
+; RV32I-NEXT: .cfi_offset s2, -16
+; RV32I-NEXT: mv s0, a1
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi s2, a1, -1
+; RV32I-NEXT: and a0, a0, s2
+; RV32I-NEXT: call __extendhfsf2
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: and a0, s0, s2
+; RV32I-NEXT: call __extendhfsf2
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call fmaximum_numf
+; RV32I-NEXT: call __truncsfhf2
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: maximumnum_half:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: .cfi_def_cfa_offset 32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: .cfi_offset s0, -16
+; RV64I-NEXT: .cfi_offset s1, -24
+; RV64I-NEXT: .cfi_offset s2, -32
+; RV64I-NEXT: mv s0, a1
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw s2, a1, -1
+; RV64I-NEXT: and a0, a0, s2
+; RV64I-NEXT: call __extendhfsf2
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: and a0, s0, s2
+; RV64I-NEXT: call __extendhfsf2
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call fmaximum_numf
+; RV64I-NEXT: call __truncsfhf2
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
+;
+; CHECKIZFHMIN-LABEL: maximumnum_half:
+; CHECKIZFHMIN: # %bb.0:
+; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
+; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0
+; CHECKIZFHMIN-NEXT: fmax.s fa5, fa4, fa5
+; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
+; CHECKIZFHMIN-NEXT: ret
+;
+; CHECKIZHINXMIN-LABEL: maximumnum_half:
+; CHECKIZHINXMIN: # %bb.0:
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT: fmax.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: ret
+ %z = call half @llvm.maximumnum.f16(half %x, half %y)
+ ret half %z
+}
+
+declare half @llvm.minimumnum.f16(half, half)
+
+define half @minimumnum_half(half %x, half %y) {
+; CHECKIZFH-LABEL: minimumnum_half:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fmin.h fa0, fa0, fa1
+; CHECKIZFH-NEXT: ret
+;
+; CHECKIZHINX-LABEL: minimumnum_half:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fmin.h a0, a0, a1
+; CHECKIZHINX-NEXT: ret
+;
+; RV32I-LABEL: minimumnum_half:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
+; RV32I-NEXT: .cfi_offset s1, -12
+; RV32I-NEXT: .cfi_offset s2, -16
+; RV32I-NEXT: mv s0, a1
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi s2, a1, -1
+; RV32I-NEXT: and a0, a0, s2
+; RV32I-NEXT: call __extendhfsf2
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: and a0, s0, s2
+; RV32I-NEXT: call __extendhfsf2
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call fminimum_numf
+; RV32I-NEXT: call __truncsfhf2
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: minimumnum_half:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: .cfi_def_cfa_offset 32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: .cfi_offset s0, -16
+; RV64I-NEXT: .cfi_offset s1, -24
+; RV64I-NEXT: .cfi_offset s2, -32
+; RV64I-NEXT: mv s0, a1
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw s2, a1, -1
+; RV64I-NEXT: and a0, a0, s2
+; RV64I-NEXT: call __extendhfsf2
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: and a0, s0, s2
+; RV64I-NEXT: call __extendhfsf2
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call fminimum_numf
+; RV64I-NEXT: call __truncsfhf2
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
+;
+; CHECKIZFHMIN-LABEL: minimumnum_half:
+; CHECKIZFHMIN: # %bb.0:
+; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
+; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0
+; CHECKIZFHMIN-NEXT: fmin.s fa5, fa4, fa5
+; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
+; CHECKIZFHMIN-NEXT: ret
+;
+; CHECKIZHINXMIN-LABEL: minimumnum_half:
+; CHECKIZHINXMIN: # %bb.0:
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT: fmin.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: ret
+ %z = call half @llvm.minimumnum.f16(half %x, half %y)
+ ret half %z
+}
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