[llvm] 381a803 - [RISCV][GISel] Merge RISCVCallLowering::lowerReturnVal into RISCVCallLowering::lowerReturn. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-08-20T17:21:46-07:00
New Revision: 381a803da253b75c8b7b10bb732e9e90925185e8

URL: https://github.com/llvm/llvm-project/commit/381a803da253b75c8b7b10bb732e9e90925185e8
DIFF: https://github.com/llvm/llvm-project/commit/381a803da253b75c8b7b10bb732e9e90925185e8.diff

LOG: [RISCV][GISel] Merge RISCVCallLowering::lowerReturnVal into RISCVCallLowering::lowerReturn. NFC

This is similar to X86 and AArch64 structure.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
    llvm/lib/Target/RISCV/GISel/RISCVCallLowering.h

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
index f7fa0e170fd297..33371512706469 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
@@ -388,47 +388,39 @@ static bool isSupportedReturnType(Type *T, const RISCVSubtarget &Subtarget,
   return false;
 }
 
-bool RISCVCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
-                                       const Value *Val,
-                                       ArrayRef<Register> VRegs,
-                                       MachineInstrBuilder &Ret) const {
-  if (!Val)
-    return true;
-
-  const RISCVSubtarget &Subtarget =
-      MIRBuilder.getMF().getSubtarget<RISCVSubtarget>();
-  if (!isSupportedReturnType(Val->getType(), Subtarget, /*IsLowerRetVal=*/true))
-    return false;
-
-  MachineFunction &MF = MIRBuilder.getMF();
-  const DataLayout &DL = MF.getDataLayout();
-  const Function &F = MF.getFunction();
-  CallingConv::ID CC = F.getCallingConv();
-
-  ArgInfo OrigRetInfo(VRegs, Val->getType(), 0);
-  setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F);
-
-  SmallVector<ArgInfo, 4> SplitRetInfos;
-  splitToValueTypes(OrigRetInfo, SplitRetInfos, DL, CC);
-
-  RVVArgDispatcher Dispatcher{&MF, getTLI<RISCVTargetLowering>(),
-                              ArrayRef(F.getReturnType())};
-  RISCVOutgoingValueAssigner Assigner(
-      CC == CallingConv::Fast ? RISCV::CC_RISCV_FastCC : RISCV::CC_RISCV,
-      /*IsRet=*/true, Dispatcher);
-  RISCVOutgoingValueHandler Handler(MIRBuilder, MF.getRegInfo(), Ret);
-  return determineAndHandleAssignments(Handler, Assigner, SplitRetInfos,
-                                       MIRBuilder, CC, F.isVarArg());
-}
-
 bool RISCVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
                                     const Value *Val, ArrayRef<Register> VRegs,
                                     FunctionLoweringInfo &FLI) const {
   assert(!Val == VRegs.empty() && "Return value without a vreg");
   MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(RISCV::PseudoRET);
 
-  if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret))
-    return false;
+  if (!VRegs.empty()) {
+    const RISCVSubtarget &Subtarget =
+        MIRBuilder.getMF().getSubtarget<RISCVSubtarget>();
+    if (!isSupportedReturnType(Val->getType(), Subtarget, /*IsLowerRetVal=*/true))
+      return false;
+
+    MachineFunction &MF = MIRBuilder.getMF();
+    const DataLayout &DL = MF.getDataLayout();
+    const Function &F = MF.getFunction();
+    CallingConv::ID CC = F.getCallingConv();
+
+    ArgInfo OrigRetInfo(VRegs, Val->getType(), 0);
+    setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F);
+
+    SmallVector<ArgInfo, 4> SplitRetInfos;
+    splitToValueTypes(OrigRetInfo, SplitRetInfos, DL, CC);
+
+    RVVArgDispatcher Dispatcher{&MF, getTLI<RISCVTargetLowering>(),
+                                ArrayRef(F.getReturnType())};
+    RISCVOutgoingValueAssigner Assigner(
+        CC == CallingConv::Fast ? RISCV::CC_RISCV_FastCC : RISCV::CC_RISCV,
+        /*IsRet=*/true, Dispatcher);
+    RISCVOutgoingValueHandler Handler(MIRBuilder, MF.getRegInfo(), Ret);
+    if (!determineAndHandleAssignments(Handler, Assigner, SplitRetInfos,
+                                         MIRBuilder, CC, F.isVarArg()))
+      return false;
+  }
 
   MIRBuilder.insertInstr(Ret);
   return true;

diff  --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.h b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.h
index abe704b4a64518..ec7fdbc26e24e8 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.h
+++ b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.h
@@ -40,9 +40,6 @@ class RISCVCallLowering : public CallLowering {
                  CallLoweringInfo &Info) const override;
 
 private:
-  bool lowerReturnVal(MachineIRBuilder &MIRBuilder, const Value *Val,
-                      ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const;
-
   void saveVarArgRegisters(MachineIRBuilder &MIRBuilder,
                            CallLowering::IncomingValueHandler &Handler,
                            IncomingValueAssigner &Assigner,