[llvm] [X86] Shrink width of masked loads/stores (PR #105451)

[via llvm-commits]

github-actions[bot] wrote:

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git-clang-format --diff a16f0dc9c2f0690e28622b0d80bd154fb0e6a30a b6fc529b33ed1e4787f214a9532141a5bbf5d840 --extensions h,cpp -- llvm/include/llvm/CodeGen/SelectionDAGNodes.h llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/lib/Target/X86/X86ISelLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index e8bbfaa41b..ba7cc276c5 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -51711,8 +51711,6 @@ static SDValue combineMaskedStore(SDNode *N, SelectionDAG &DAG,
   if (Mst->isCompressingStore())
     return SDValue();
 
-
-
   EVT VT = Mst->getValue().getValueType();
   SDLoc dl(Mst);
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();

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https://github.com/llvm/llvm-project/pull/105451