[llvm] 3145cff - [RISCV] Add coverage for int reductions of <3 x i8> vectors
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 20 16:44:01 PDT 2024
Author: Philip Reames
Date: 2024-08-20T16:42:42-07:00
New Revision: 3145cff24bda61ae0d3ba3981c19599f12af95ab
URL: https://github.com/llvm/llvm-project/commit/3145cff24bda61ae0d3ba3981c19599f12af95ab
DIFF: https://github.com/llvm/llvm-project/commit/3145cff24bda61ae0d3ba3981c19599f12af95ab.diff
LOG: [RISCV] Add coverage for int reductions of <3 x i8> vectors
Specifically, to illustrate our general lowering strategy for
non-power of two vectors.
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
index f67282f9e6a322..29d80979808a9c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
@@ -32,6 +32,24 @@ define i8 @vreduce_add_v2i8(ptr %x) {
ret i8 %red
}
+declare i8 @llvm.vector.reduce.add.v3i8(<3 x i8>)
+
+define i8 @vreduce_add_v3i8(ptr %x) {
+; CHECK-LABEL: vreduce_add_v3i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmv.s.x v9, zero
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %v = load <3 x i8>, ptr %x
+ %red = call i8 @llvm.vector.reduce.add.v3i8(<3 x i8> %v)
+ ret i8 %red
+}
+
declare i8 @llvm.vector.reduce.add.v4i8(<4 x i8>)
define i8 @vreduce_add_v4i8(ptr %x) {
@@ -1743,6 +1761,25 @@ define i8 @vreduce_and_v2i8(ptr %x) {
ret i8 %red
}
+declare i8 @llvm.vector.reduce.and.v3i8(<3 x i8>)
+
+define i8 @vreduce_and_v3i8(ptr %x) {
+; CHECK-LABEL: vreduce_and_v3i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vmv.v.i v9, -1
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: vredand.vs v8, v8, v8
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %v = load <3 x i8>, ptr %x
+ %red = call i8 @llvm.vector.reduce.and.v3i8(<3 x i8> %v)
+ ret i8 %red
+}
+
+
declare i8 @llvm.vector.reduce.and.v4i8(<4 x i8>)
define i8 @vreduce_and_v4i8(ptr %x) {
@@ -2328,6 +2365,24 @@ define i8 @vreduce_or_v2i8(ptr %x) {
ret i8 %red
}
+declare i8 @llvm.vector.reduce.or.v3i8(<3 x i8>)
+
+define i8 @vreduce_or_v3i8(ptr %x) {
+; CHECK-LABEL: vreduce_or_v3i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmv.s.x v9, zero
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: vredor.vs v8, v8, v8
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %v = load <3 x i8>, ptr %x
+ %red = call i8 @llvm.vector.reduce.or.v3i8(<3 x i8> %v)
+ ret i8 %red
+}
+
declare i8 @llvm.vector.reduce.or.v4i8(<4 x i8>)
define i8 @vreduce_or_v4i8(ptr %x) {
@@ -2914,6 +2969,24 @@ define i8 @vreduce_xor_v2i8(ptr %x) {
ret i8 %red
}
+declare i8 @llvm.vector.reduce.xor.v3i8(<3 x i8>)
+
+define i8 @vreduce_xor_v3i8(ptr %x) {
+; CHECK-LABEL: vreduce_xor_v3i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmv.s.x v9, zero
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %v = load <3 x i8>, ptr %x
+ %red = call i8 @llvm.vector.reduce.xor.v3i8(<3 x i8> %v)
+ ret i8 %red
+}
+
declare i8 @llvm.vector.reduce.xor.v4i8(<4 x i8>)
define i8 @vreduce_xor_v4i8(ptr %x) {
@@ -3531,6 +3604,25 @@ define i8 @vreduce_smin_v2i8(ptr %x) {
ret i8 %red
}
+declare i8 @llvm.vector.reduce.smin.v3i8(<3 x i8>)
+
+define i8 @vreduce_smin_v3i8(ptr %x) {
+; CHECK-LABEL: vreduce_smin_v3i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: li a0, 127
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: vredmin.vs v8, v8, v8
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %v = load <3 x i8>, ptr %x
+ %red = call i8 @llvm.vector.reduce.smin.v3i8(<3 x i8> %v)
+ ret i8 %red
+}
+
declare i8 @llvm.vector.reduce.smin.v4i8(<4 x i8>)
define i8 @vreduce_smin_v4i8(ptr %x) {
@@ -4116,6 +4208,25 @@ define i8 @vreduce_smax_v2i8(ptr %x) {
ret i8 %red
}
+declare i8 @llvm.vector.reduce.smax.v3i8(<3 x i8>)
+
+define i8 @vreduce_smax_v3i8(ptr %x) {
+; CHECK-LABEL: vreduce_smax_v3i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: li a0, -128
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: vredmax.vs v8, v8, v8
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %v = load <3 x i8>, ptr %x
+ %red = call i8 @llvm.vector.reduce.smax.v3i8(<3 x i8> %v)
+ ret i8 %red
+}
+
declare i8 @llvm.vector.reduce.smax.v4i8(<4 x i8>)
define i8 @vreduce_smax_v4i8(ptr %x) {
@@ -4701,6 +4812,24 @@ define i8 @vreduce_umin_v2i8(ptr %x) {
ret i8 %red
}
+declare i8 @llvm.vector.reduce.umin.v3i8(<3 x i8>)
+
+define i8 @vreduce_umin_v3i8(ptr %x) {
+; CHECK-LABEL: vreduce_umin_v3i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vmv.v.i v9, -1
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: vredminu.vs v8, v8, v8
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %v = load <3 x i8>, ptr %x
+ %red = call i8 @llvm.vector.reduce.umin.v3i8(<3 x i8> %v)
+ ret i8 %red
+}
+
declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
define i8 @vreduce_umin_v4i8(ptr %x) {
@@ -5286,6 +5415,24 @@ define i8 @vreduce_umax_v2i8(ptr %x) {
ret i8 %red
}
+declare i8 @llvm.vector.reduce.umax.v3i8(<3 x i8>)
+
+define i8 @vreduce_umax_v3i8(ptr %x) {
+; CHECK-LABEL: vreduce_umax_v3i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmv.s.x v9, zero
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: vredmaxu.vs v8, v8, v8
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %v = load <3 x i8>, ptr %x
+ %red = call i8 @llvm.vector.reduce.umax.v3i8(<3 x i8> %v)
+ ret i8 %red
+}
+
declare i8 @llvm.vector.reduce.umax.v4i8(<4 x i8>)
define i8 @vreduce_umax_v4i8(ptr %x) {
@@ -5872,6 +6019,30 @@ define i8 @vreduce_mul_v2i8(ptr %x) {
ret i8 %red
}
+declare i8 @llvm.vector.reduce.mul.v3i8(<3 x i8>)
+
+define i8 @vreduce_mul_v3i8(ptr %x) {
+; CHECK-LABEL: vreduce_mul_v3i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vmv.v.i v9, 1
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vi v9, v8, 2
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vmul.vv v8, v8, v9
+; CHECK-NEXT: vslidedown.vi v9, v8, 1
+; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; CHECK-NEXT: vmul.vv v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %v = load <3 x i8>, ptr %x
+ %red = call i8 @llvm.vector.reduce.mul.v3i8(<3 x i8> %v)
+ ret i8 %red
+}
+
declare i8 @llvm.vector.reduce.mul.v4i8(<4 x i8>)
define i8 @vreduce_mul_v4i8(ptr %x) {
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