[llvm] [SPIR-V] Rework usage of virtual registers' types and classes (PR #104104)
Vyacheslav Levytskyy via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 20 13:30:00 PDT 2024
https://github.com/VyacheslavLevytskyy updated https://github.com/llvm/llvm-project/pull/104104
>From 741349d1ccc78b809835c1a8c3e3f7a2b02d5b87 Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Wed, 14 Aug 2024 10:58:03 -0700
Subject: [PATCH 01/14] Rework usage of virtual registers' types and classes
---
.../SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp | 3 +-
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 60 ++++++------
llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp | 4 +-
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp | 97 ++++++++-----------
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h | 4 +-
llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp | 10 +-
llvm/lib/Target/SPIRV/SPIRVISelLowering.h | 2 +-
llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp | 9 +-
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 64 ++++++------
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 50 +++++-----
llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp | 14 +--
llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 27 +++---
llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td | 46 +++------
llvm/lib/Target/SPIRV/SPIRVRegularizer.cpp | 2 +-
14 files changed, 171 insertions(+), 221 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
index 6dd0df2a104c0f..42567f695395ef 100644
--- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
@@ -67,7 +67,8 @@ static bool hasType(const MCInst &MI, const MCInstrInfo &MII) {
// Check if we define an ID, and take a type as operand 1.
auto &DefOpInfo = MCDesc.operands()[0];
auto &FirstArgOpInfo = MCDesc.operands()[1];
- return DefOpInfo.RegClass != SPIRV::TYPERegClassID &&
+ return DefOpInfo.RegClass >= 0 && FirstArgOpInfo.RegClass >= 0 &&
+ DefOpInfo.RegClass != SPIRV::TYPERegClassID &&
FirstArgOpInfo.RegClass == SPIRV::TYPERegClassID;
}
return false;
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 09f06728d2d10d..dadfee03c5bc41 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -443,7 +443,7 @@ static Register buildLoadInst(SPIRVType *BaseType, Register PtrRegister,
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
if (!DestinationReg.isValid()) {
DestinationReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
- MRI->setType(DestinationReg, LLT::scalar(32));
+ MRI->setType(DestinationReg, LLT::scalar(64));
GR->assignSPIRVTypeToVReg(BaseType, DestinationReg, MIRBuilder.getMF());
}
// TODO: consider using correct address space and alignment (p0 is canonical
@@ -526,11 +526,11 @@ static SPIRV::Scope::Scope getSPIRVScope(SPIRV::CLMemoryScope ClScope) {
report_fatal_error("Unknown CL memory scope");
}
-static Register buildConstantIntReg(uint64_t Val, MachineIRBuilder &MIRBuilder,
- SPIRVGlobalRegistry *GR,
- unsigned BitWidth = 32) {
- SPIRVType *IntType = GR->getOrCreateSPIRVIntegerType(BitWidth, MIRBuilder);
- return GR->buildConstantInt(Val, MIRBuilder, IntType);
+static Register buildConstantIntReg32(uint64_t Val,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ return GR->buildConstantInt(Val, MIRBuilder,
+ GR->getOrCreateSPIRVIntegerType(32, MIRBuilder));
}
static Register buildScopeReg(Register CLScopeRegister,
@@ -548,7 +548,7 @@ static Register buildScopeReg(Register CLScopeRegister,
return CLScopeRegister;
}
}
- return buildConstantIntReg(Scope, MIRBuilder, GR);
+ return buildConstantIntReg32(Scope, MIRBuilder, GR);
}
static Register buildMemSemanticsReg(Register SemanticsRegister,
@@ -568,7 +568,7 @@ static Register buildMemSemanticsReg(Register SemanticsRegister,
return SemanticsRegister;
}
}
- return buildConstantIntReg(Semantics, MIRBuilder, GR);
+ return buildConstantIntReg32(Semantics, MIRBuilder, GR);
}
static bool buildOpFromWrapper(MachineIRBuilder &MIRBuilder, unsigned Opcode,
@@ -625,7 +625,7 @@ static bool buildAtomicLoadInst(const SPIRV::IncomingCall *Call,
ScopeRegister = Call->Arguments[1];
MIRBuilder.getMRI()->setRegClass(ScopeRegister, &SPIRV::iIDRegClass);
} else
- ScopeRegister = buildConstantIntReg(SPIRV::Scope::Device, MIRBuilder, GR);
+ ScopeRegister = buildConstantIntReg32(SPIRV::Scope::Device, MIRBuilder, GR);
Register MemSemanticsReg;
if (Call->Arguments.size() > 2) {
@@ -636,7 +636,7 @@ static bool buildAtomicLoadInst(const SPIRV::IncomingCall *Call,
int Semantics =
SPIRV::MemorySemantics::SequentiallyConsistent |
getMemSemanticsForStorageClass(GR->getPointerStorageClass(PtrRegister));
- MemSemanticsReg = buildConstantIntReg(Semantics, MIRBuilder, GR);
+ MemSemanticsReg = buildConstantIntReg32(Semantics, MIRBuilder, GR);
}
MIRBuilder.buildInstr(SPIRV::OpAtomicLoad)
@@ -656,13 +656,13 @@ static bool buildAtomicStoreInst(const SPIRV::IncomingCall *Call,
return buildOpFromWrapper(MIRBuilder, SPIRV::OpAtomicStore, Call, Register(0));
Register ScopeRegister =
- buildConstantIntReg(SPIRV::Scope::Device, MIRBuilder, GR);
+ buildConstantIntReg32(SPIRV::Scope::Device, MIRBuilder, GR);
Register PtrRegister = Call->Arguments[0];
MIRBuilder.getMRI()->setRegClass(PtrRegister, &SPIRV::iIDRegClass);
int Semantics =
SPIRV::MemorySemantics::SequentiallyConsistent |
getMemSemanticsForStorageClass(GR->getPointerStorageClass(PtrRegister));
- Register MemSemanticsReg = buildConstantIntReg(Semantics, MIRBuilder, GR);
+ Register MemSemanticsReg = buildConstantIntReg32(Semantics, MIRBuilder, GR);
MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
MIRBuilder.buildInstr(SPIRV::OpAtomicStore)
.addUse(PtrRegister)
@@ -733,9 +733,9 @@ static bool buildAtomicCompareExchangeInst(
MRI->setRegClass(Call->Arguments[4], &SPIRV::iIDRegClass);
}
if (!MemSemEqualReg.isValid())
- MemSemEqualReg = buildConstantIntReg(MemSemEqual, MIRBuilder, GR);
+ MemSemEqualReg = buildConstantIntReg32(MemSemEqual, MIRBuilder, GR);
if (!MemSemUnequalReg.isValid())
- MemSemUnequalReg = buildConstantIntReg(MemSemUnequal, MIRBuilder, GR);
+ MemSemUnequalReg = buildConstantIntReg32(MemSemUnequal, MIRBuilder, GR);
Register ScopeReg;
auto Scope = IsCmpxchg ? SPIRV::Scope::Workgroup : SPIRV::Scope::Device;
@@ -750,12 +750,12 @@ static bool buildAtomicCompareExchangeInst(
MRI->setRegClass(Call->Arguments[5], &SPIRV::iIDRegClass);
}
if (!ScopeReg.isValid())
- ScopeReg = buildConstantIntReg(Scope, MIRBuilder, GR);
+ ScopeReg = buildConstantIntReg32(Scope, MIRBuilder, GR);
Register Expected = IsCmpxchg
? ExpectedArg
: buildLoadInst(SpvDesiredTy, ExpectedArg, MIRBuilder,
- GR, LLT::scalar(32));
+ GR, LLT::scalar(64));
MRI->setType(Expected, DesiredLLT);
Register Tmp = !IsCmpxchg ? MRI->createGenericVirtualRegister(DesiredLLT)
: Call->ReturnRegister;
@@ -941,7 +941,7 @@ static bool buildBarrierInst(const SPIRV::IncomingCall *Call, unsigned Opcode,
MemSemanticsReg = Call->Arguments[0];
MRI->setRegClass(MemSemanticsReg, &SPIRV::iIDRegClass);
} else
- MemSemanticsReg = buildConstantIntReg(MemSemantics, MIRBuilder, GR);
+ MemSemanticsReg = buildConstantIntReg32(MemSemantics, MIRBuilder, GR);
Register ScopeReg;
SPIRV::Scope::Scope Scope = SPIRV::Scope::Workgroup;
@@ -967,11 +967,11 @@ static bool buildBarrierInst(const SPIRV::IncomingCall *Call, unsigned Opcode,
}
if (!ScopeReg.isValid())
- ScopeReg = buildConstantIntReg(Scope, MIRBuilder, GR);
+ ScopeReg = buildConstantIntReg32(Scope, MIRBuilder, GR);
auto MIB = MIRBuilder.buildInstr(Opcode).addUse(ScopeReg);
if (Opcode != SPIRV::OpMemoryBarrier)
- MIB.addUse(buildConstantIntReg(MemScope, MIRBuilder, GR));
+ MIB.addUse(buildConstantIntReg32(MemScope, MIRBuilder, GR));
MIB.addUse(MemSemanticsReg);
return true;
}
@@ -1133,7 +1133,7 @@ static bool generateGroupInst(const SPIRV::IncomingCall *Call,
auto Scope = Builtin->Name.starts_with("sub_group") ? SPIRV::Scope::Subgroup
: SPIRV::Scope::Workgroup;
- Register ScopeRegister = buildConstantIntReg(Scope, MIRBuilder, GR);
+ Register ScopeRegister = buildConstantIntReg32(Scope, MIRBuilder, GR);
Register VecReg;
if (GroupBuiltin->Opcode == SPIRV::OpGroupBroadcast &&
@@ -1334,7 +1334,7 @@ static bool generateKernelClockInst(const SPIRV::IncomingCall *Call,
.EndsWith("device", SPIRV::Scope::Scope::Device)
.EndsWith("work_group", SPIRV::Scope::Scope::Workgroup)
.EndsWith("sub_group", SPIRV::Scope::Scope::Subgroup);
- Register ScopeReg = buildConstantIntReg(ScopeArg, MIRBuilder, GR);
+ Register ScopeReg = buildConstantIntReg32(ScopeArg, MIRBuilder, GR);
MIRBuilder.buildInstr(SPIRV::OpReadClockKHR)
.addDef(ResultReg)
@@ -1649,7 +1649,7 @@ static bool generateImageSizeQueryInst(const SPIRV::IncomingCall *Call,
.addUse(GR->getSPIRVTypeID(QueryResultType))
.addUse(Call->Arguments[0]);
if (!IsDimBuf)
- MIB.addUse(buildConstantIntReg(0, MIRBuilder, GR)); // Lod id.
+ MIB.addUse(buildConstantIntReg32(0, MIRBuilder, GR)); // Lod id.
if (NumExpectedRetComponents == NumActualRetComponents)
return true;
if (NumExpectedRetComponents == 1) {
@@ -2142,8 +2142,8 @@ static bool buildEnqueueKernel(const SPIRV::IncomingCall *Call,
GEPInst
.addImm(GepMI->getOperand(2).getImm()) // In bound.
.addUse(ArrayMI->getOperand(0).getReg()) // Alloca.
- .addUse(buildConstantIntReg(0, MIRBuilder, GR)) // Indices.
- .addUse(buildConstantIntReg(I, MIRBuilder, GR));
+ .addUse(buildConstantIntReg32(0, MIRBuilder, GR)) // Indices.
+ .addUse(buildConstantIntReg32(I, MIRBuilder, GR));
LocalSizes.push_back(Reg);
}
}
@@ -2160,7 +2160,7 @@ static bool buildEnqueueKernel(const SPIRV::IncomingCall *Call,
// If there are no event arguments in the original call, add dummy ones.
if (!HasEvents) {
- MIB.addUse(buildConstantIntReg(0, MIRBuilder, GR)); // Dummy num events.
+ MIB.addUse(buildConstantIntReg32(0, MIRBuilder, GR)); // Dummy num events.
Register NullPtr = GR->getOrCreateConstNullPtr(
MIRBuilder, getOrCreateSPIRVDeviceEventPointer(MIRBuilder, GR));
MIB.addUse(NullPtr); // Dummy wait events.
@@ -2179,10 +2179,10 @@ static bool buildEnqueueKernel(const SPIRV::IncomingCall *Call,
Type *PType = const_cast<Type *>(getBlockStructType(BlockLiteralReg, MRI));
// TODO: these numbers should be obtained from block literal structure.
// Param Size: Size of block literal structure.
- MIB.addUse(buildConstantIntReg(DL.getTypeStoreSize(PType), MIRBuilder, GR));
+ MIB.addUse(buildConstantIntReg32(DL.getTypeStoreSize(PType), MIRBuilder, GR));
// Param Aligment: Aligment of block literal structure.
MIB.addUse(
- buildConstantIntReg(DL.getPrefTypeAlign(PType).value(), MIRBuilder, GR));
+ buildConstantIntReg32(DL.getPrefTypeAlign(PType).value(), MIRBuilder, GR));
for (unsigned i = 0; i < LocalSizes.size(); i++)
MIB.addUse(LocalSizes[i]);
@@ -2250,7 +2250,7 @@ static bool generateAsyncCopy(const SPIRV::IncomingCall *Call,
return buildOpFromWrapper(MIRBuilder, Opcode, Call,
IsSet ? TypeReg : Register(0));
- auto Scope = buildConstantIntReg(SPIRV::Scope::Workgroup, MIRBuilder, GR);
+ auto Scope = buildConstantIntReg32(SPIRV::Scope::Workgroup, MIRBuilder, GR);
switch (Opcode) {
case SPIRV::OpGroupAsyncCopy: {
@@ -2270,7 +2270,7 @@ static bool generateAsyncCopy(const SPIRV::IncomingCall *Call,
.addUse(Call->Arguments[2])
.addUse(Call->Arguments.size() > 4
? Call->Arguments[3]
- : buildConstantIntReg(1, MIRBuilder, GR))
+ : buildConstantIntReg32(1, MIRBuilder, GR))
.addUse(EventReg);
if (NewType != nullptr)
insertAssignInstr(Call->ReturnRegister, nullptr, NewType, GR, MIRBuilder,
@@ -2545,7 +2545,7 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
MIRBuilder.getMRI()->setRegClass(ReturnRegister, &SPIRV::iIDRegClass);
} else if (OrigRetTy && OrigRetTy->isVoidTy()) {
ReturnRegister = MIRBuilder.getMRI()->createVirtualRegister(&IDRegClass);
- MIRBuilder.getMRI()->setType(ReturnRegister, LLT::scalar(32));
+ MIRBuilder.getMRI()->setType(ReturnRegister, LLT::scalar(64));
ReturnType = GR->assignTypeToVReg(OrigRetTy, ReturnRegister, MIRBuilder);
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
index 316abe866a163c..26d84c8efb10ba 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
@@ -371,7 +371,7 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
}
auto MRI = MIRBuilder.getMRI();
- Register FuncVReg = MRI->createGenericVirtualRegister(LLT::scalar(32));
+ Register FuncVReg = MRI->createGenericVirtualRegister(LLT::scalar(64));
MRI->setRegClass(FuncVReg, &SPIRV::iIDRegClass);
if (F.isDeclaration())
GR->add(&F, &MIRBuilder.getMF(), FuncVReg);
@@ -557,7 +557,7 @@ bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
for (const Argument &Arg : CF->args()) {
if (MIRBuilder.getDataLayout().getTypeStoreSize(Arg.getType()).isZero())
continue; // Don't handle zero sized types.
- Register Reg = MRI->createGenericVirtualRegister(LLT::scalar(32));
+ Register Reg = MRI->createGenericVirtualRegister(LLT::scalar(64));
MRI->setRegClass(Reg, &SPIRV::iIDRegClass);
ToInsert.push_back({Reg});
VRegArgs.push_back(ToInsert.back());
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
index 6702a0efc638ae..621b6bdf71cd06 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
@@ -72,17 +72,14 @@ void SPIRVGlobalRegistry::assignSPIRVTypeToVReg(SPIRVType *SpirvType,
VRegToTypeMap[&MF][VReg] = SpirvType;
}
-static Register createTypeVReg(MachineIRBuilder &MIRBuilder) {
- auto &MRI = MIRBuilder.getMF().getRegInfo();
- auto Res = MRI.createGenericVirtualRegister(LLT::scalar(32));
+static Register createTypeVReg(MachineRegisterInfo &MRI) {
+ auto Res = MRI.createGenericVirtualRegister(LLT::scalar(64));
MRI.setRegClass(Res, &SPIRV::TYPERegClass);
return Res;
}
-static Register createTypeVReg(MachineRegisterInfo &MRI) {
- auto Res = MRI.createGenericVirtualRegister(LLT::scalar(32));
- MRI.setRegClass(Res, &SPIRV::TYPERegClass);
- return Res;
+inline Register createTypeVReg(MachineIRBuilder &MIRBuilder) {
+ return createTypeVReg(MIRBuilder.getMF().getRegInfo());
}
SPIRVType *SPIRVGlobalRegistry::getOpTypeBool(MachineIRBuilder &MIRBuilder) {
@@ -157,26 +154,24 @@ SPIRVType *SPIRVGlobalRegistry::getOpTypeVector(uint32_t NumElems,
return MIB;
}
-std::tuple<Register, ConstantInt *, bool>
+std::tuple<Register, ConstantInt *, bool, unsigned>
SPIRVGlobalRegistry::getOrCreateConstIntReg(uint64_t Val, SPIRVType *SpvType,
MachineIRBuilder *MIRBuilder,
MachineInstr *I,
const SPIRVInstrInfo *TII) {
- const IntegerType *LLVMIntTy;
- if (SpvType)
- LLVMIntTy = cast<IntegerType>(getTypeForSPIRVType(SpvType));
- else
- LLVMIntTy = IntegerType::getInt32Ty(CurMF->getFunction().getContext());
+ assert(SpvType);
+ const IntegerType *LLVMIntTy =
+ cast<IntegerType>(getTypeForSPIRVType(SpvType));
+ unsigned BitWidth = getScalarOrVectorBitWidth(SpvType);
bool NewInstr = false;
// Find a constant in DT or build a new one.
ConstantInt *CI = ConstantInt::get(const_cast<IntegerType *>(LLVMIntTy), Val);
Register Res = DT.find(CI, CurMF);
if (!Res.isValid()) {
- unsigned BitWidth = SpvType ? getScalarOrVectorBitWidth(SpvType) : 32;
// TODO: handle cases where the type is not 32bit wide
// TODO: https://github.com/llvm/llvm-project/issues/88129
- LLT LLTy = LLT::scalar(32);
- Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
+ Res =
+ CurMF->getRegInfo().createGenericVirtualRegister(LLT::scalar(BitWidth));
CurMF->getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);
if (MIRBuilder)
assignTypeToVReg(LLVMIntTy, Res, *MIRBuilder);
@@ -185,7 +180,7 @@ SPIRVGlobalRegistry::getOrCreateConstIntReg(uint64_t Val, SPIRVType *SpvType,
DT.add(CI, CurMF, Res);
NewInstr = true;
}
- return std::make_tuple(Res, CI, NewInstr);
+ return std::make_tuple(Res, CI, NewInstr, BitWidth);
}
std::tuple<Register, ConstantFP *, bool, unsigned>
@@ -193,27 +188,19 @@ SPIRVGlobalRegistry::getOrCreateConstFloatReg(APFloat Val, SPIRVType *SpvType,
MachineIRBuilder *MIRBuilder,
MachineInstr *I,
const SPIRVInstrInfo *TII) {
- const Type *LLVMFloatTy;
+ assert(SpvType);
LLVMContext &Ctx = CurMF->getFunction().getContext();
- unsigned BitWidth = 32;
- if (SpvType)
- LLVMFloatTy = getTypeForSPIRVType(SpvType);
- else {
- LLVMFloatTy = Type::getFloatTy(Ctx);
- if (MIRBuilder)
- SpvType = getOrCreateSPIRVType(LLVMFloatTy, *MIRBuilder);
- }
+ const Type *LLVMFloatTy = getTypeForSPIRVType(SpvType);
+ unsigned BitWidth = getScalarOrVectorBitWidth(SpvType);
bool NewInstr = false;
// Find a constant in DT or build a new one.
auto *const CI = ConstantFP::get(Ctx, Val);
Register Res = DT.find(CI, CurMF);
if (!Res.isValid()) {
- if (SpvType)
- BitWidth = getScalarOrVectorBitWidth(SpvType);
// TODO: handle cases where the type is not 32bit wide
// TODO: https://github.com/llvm/llvm-project/issues/88129
- LLT LLTy = LLT::scalar(32);
- Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
+ Res =
+ CurMF->getRegInfo().createGenericVirtualRegister(LLT::scalar(BitWidth));
CurMF->getRegInfo().setRegClass(Res, &SPIRV::fIDRegClass);
if (MIRBuilder)
assignTypeToVReg(LLVMFloatTy, Res, *MIRBuilder);
@@ -269,7 +256,8 @@ Register SPIRVGlobalRegistry::getOrCreateConstInt(uint64_t Val, MachineInstr &I,
ConstantInt *CI;
Register Res;
bool New;
- std::tie(Res, CI, New) =
+ unsigned BitWidth;
+ std::tie(Res, CI, New, BitWidth) =
getOrCreateConstIntReg(Val, SpvType, nullptr, &I, &TII);
// If we have found Res register which is defined by the passed G_CONSTANT
// machine instruction, a new constant instruction should be created.
@@ -281,7 +269,7 @@ Register SPIRVGlobalRegistry::getOrCreateConstInt(uint64_t Val, MachineInstr &I,
MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantI))
.addDef(Res)
.addUse(getSPIRVTypeID(SpvType));
- addNumImm(APInt(getScalarOrVectorBitWidth(SpvType), Val), MIB);
+ addNumImm(APInt(BitWidth, Val), MIB);
} else {
MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull))
.addDef(Res)
@@ -297,19 +285,16 @@ Register SPIRVGlobalRegistry::buildConstantInt(uint64_t Val,
MachineIRBuilder &MIRBuilder,
SPIRVType *SpvType,
bool EmitIR) {
+ assert(SpvType);
auto &MF = MIRBuilder.getMF();
- const IntegerType *LLVMIntTy;
- if (SpvType)
- LLVMIntTy = cast<IntegerType>(getTypeForSPIRVType(SpvType));
- else
- LLVMIntTy = IntegerType::getInt32Ty(MF.getFunction().getContext());
+ const IntegerType *LLVMIntTy = cast<IntegerType>(getTypeForSPIRVType(SpvType));
// Find a constant in DT or build a new one.
const auto ConstInt =
ConstantInt::get(const_cast<IntegerType *>(LLVMIntTy), Val);
Register Res = DT.find(ConstInt, &MF);
if (!Res.isValid()) {
- unsigned BitWidth = SpvType ? getScalarOrVectorBitWidth(SpvType) : 32;
- LLT LLTy = LLT::scalar(EmitIR ? BitWidth : 32);
+ unsigned BitWidth = getScalarOrVectorBitWidth(SpvType);
+ LLT LLTy = LLT::scalar(EmitIR ? BitWidth : 32); // lev
Res = MF.getRegInfo().createGenericVirtualRegister(LLTy);
MF.getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);
assignTypeToVReg(LLVMIntTy, Res, MIRBuilder,
@@ -318,18 +303,17 @@ Register SPIRVGlobalRegistry::buildConstantInt(uint64_t Val,
if (EmitIR) {
MIRBuilder.buildConstant(Res, *ConstInt);
} else {
- if (!SpvType)
- SpvType = getOrCreateSPIRVIntegerType(BitWidth, MIRBuilder);
+ Register SpvTypeReg = getSPIRVTypeID(SpvType);
MachineInstrBuilder MIB;
if (Val) {
MIB = MIRBuilder.buildInstr(SPIRV::OpConstantI)
.addDef(Res)
- .addUse(getSPIRVTypeID(SpvType));
+ .addUse(SpvTypeReg);
addNumImm(APInt(BitWidth, Val), MIB);
} else {
MIB = MIRBuilder.buildInstr(SPIRV::OpConstantNull)
.addDef(Res)
- .addUse(getSPIRVTypeID(SpvType));
+ .addUse(SpvTypeReg);
}
const auto &Subtarget = CurMF->getSubtarget();
constrainSelectedInstRegOperands(*MIB, *Subtarget.getInstrInfo(),
@@ -353,7 +337,8 @@ Register SPIRVGlobalRegistry::buildConstantFP(APFloat Val,
const auto ConstFP = ConstantFP::get(Ctx, Val);
Register Res = DT.find(ConstFP, &MF);
if (!Res.isValid()) {
- Res = MF.getRegInfo().createGenericVirtualRegister(LLT::scalar(32));
+ Res = MF.getRegInfo().createGenericVirtualRegister(
+ LLT::scalar(getScalarOrVectorBitWidth(SpvType)));
MF.getRegInfo().setRegClass(Res, &SPIRV::fIDRegClass);
assignSPIRVTypeToVReg(SpvType, Res, MF);
DT.add(ConstFP, &MF, Res);
@@ -407,7 +392,7 @@ Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull(
// TODO: handle cases where the type is not 32bit wide
// TODO: https://github.com/llvm/llvm-project/issues/88129
- LLT LLTy = LLT::scalar(32);
+ LLT LLTy = LLT::scalar(64);
Register SpvVecConst =
CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::iIDRegClass);
@@ -509,7 +494,7 @@ Register SPIRVGlobalRegistry::getOrCreateIntCompositeOrNull(
getOrCreateSPIRVIntegerType(BitWidth, MIRBuilder);
SpvScalConst = buildConstantInt(Val, MIRBuilder, SpvBaseType, EmitIR);
}
- LLT LLTy = EmitIR ? LLT::fixed_vector(ElemCnt, BitWidth) : LLT::scalar(32);
+ LLT LLTy = EmitIR ? LLT::fixed_vector(ElemCnt, BitWidth) : LLT::scalar(64);
Register SpvVecConst =
CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::iIDRegClass);
@@ -650,7 +635,7 @@ Register SPIRVGlobalRegistry::buildGlobalVariable(
// Set to Reg the same type as ResVReg has.
auto MRI = MIRBuilder.getMRI();
- assert(MRI->getType(ResVReg).isPointer() && "Pointer type is expected");
+// assert(MRI->getType(ResVReg).isPointer() && "Pointer type is expected");
if (Reg != ResVReg) {
LLT RegLLTy =
LLT::pointer(MRI->getType(ResVReg).getAddressSpace(), getPointerSize());
@@ -706,8 +691,9 @@ SPIRVType *SPIRVGlobalRegistry::getOpTypeArray(uint32_t NumElems,
bool EmitIR) {
assert((ElemType->getOpcode() != SPIRV::OpTypeVoid) &&
"Invalid array element type");
+ SPIRVType *SpvTypeInt32 = getOrCreateSPIRVIntegerType(32, MIRBuilder);
Register NumElementsVReg =
- buildConstantInt(NumElems, MIRBuilder, nullptr, EmitIR);
+ buildConstantInt(NumElems, MIRBuilder, SpvTypeInt32, EmitIR);
auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeArray)
.addDef(createTypeVReg(MIRBuilder))
.addUse(getSPIRVTypeID(ElemType))
@@ -1188,14 +1174,15 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeCoopMatr(
if (ResVReg.isValid())
return MIRBuilder.getMF().getRegInfo().getUniqueVRegDef(ResVReg);
ResVReg = createTypeVReg(MIRBuilder);
+ SPIRVType *SpvTypeInt32 = getOrCreateSPIRVIntegerType(32, MIRBuilder);
SPIRVType *SpirvTy =
MIRBuilder.buildInstr(SPIRV::OpTypeCooperativeMatrixKHR)
.addDef(ResVReg)
.addUse(getSPIRVTypeID(ElemType))
- .addUse(buildConstantInt(Scope, MIRBuilder, nullptr, true))
- .addUse(buildConstantInt(Rows, MIRBuilder, nullptr, true))
- .addUse(buildConstantInt(Columns, MIRBuilder, nullptr, true))
- .addUse(buildConstantInt(Use, MIRBuilder, nullptr, true));
+ .addUse(buildConstantInt(Scope, MIRBuilder, SpvTypeInt32, true))
+ .addUse(buildConstantInt(Rows, MIRBuilder, SpvTypeInt32, true))
+ .addUse(buildConstantInt(Columns, MIRBuilder, SpvTypeInt32, true))
+ .addUse(buildConstantInt(Use, MIRBuilder, SpvTypeInt32, true));
DT.add(ExtensionType, &MIRBuilder.getMF(), ResVReg);
return SpirvTy;
}
@@ -1386,8 +1373,8 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVArrayType(
if (Reg.isValid())
return getSPIRVTypeForVReg(Reg);
MachineBasicBlock &BB = *I.getParent();
- SPIRVType *SpirvType = getOrCreateSPIRVIntegerType(32, I, TII);
- Register Len = getOrCreateConstInt(NumElements, I, SpirvType, TII);
+ SPIRVType *SpvTypeInt32 = getOrCreateSPIRVIntegerType(32, I, TII);
+ Register Len = getOrCreateConstInt(NumElements, I, SpvTypeInt32, TII);
auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpTypeArray))
.addDef(createTypeVReg(CurMF->getRegInfo()))
.addUse(getSPIRVTypeID(BaseType))
@@ -1436,7 +1423,7 @@ Register SPIRVGlobalRegistry::getOrCreateUndef(MachineInstr &I,
Register Res = DT.find(UV, CurMF);
if (Res.isValid())
return Res;
- LLT LLTy = LLT::scalar(32);
+ LLT LLTy = LLT::scalar(64);
Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
CurMF->getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);
assignSPIRVTypeToVReg(SpvType, Res, *CurMF);
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
index 821c1218fcb7f0..290c7c25831ddb 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
@@ -430,7 +430,7 @@ class SPIRVGlobalRegistry {
getOrCreateSpecialType(const Type *Ty, MachineIRBuilder &MIRBuilder,
SPIRV::AccessQualifier::AccessQualifier AccQual);
- std::tuple<Register, ConstantInt *, bool> getOrCreateConstIntReg(
+ std::tuple<Register, ConstantInt *, bool, unsigned> getOrCreateConstIntReg(
uint64_t Val, SPIRVType *SpvType, MachineIRBuilder *MIRBuilder,
MachineInstr *I = nullptr, const SPIRVInstrInfo *TII = nullptr);
std::tuple<Register, ConstantFP *, bool, unsigned> getOrCreateConstFloatReg(
@@ -455,7 +455,7 @@ class SPIRVGlobalRegistry {
public:
Register buildConstantInt(uint64_t Val, MachineIRBuilder &MIRBuilder,
- SPIRVType *SpvType = nullptr, bool EmitIR = true);
+ SPIRVType *SpvType, bool EmitIR = true);
Register getOrCreateConstInt(uint64_t Val, MachineInstr &I,
SPIRVType *SpvType, const SPIRVInstrInfo &TII,
bool ZeroAsNull = true);
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
index 76419faa38e090..8db9808bb87e1d 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
@@ -91,13 +91,9 @@ SPIRVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
return std::make_pair(0u, RC);
if (VT.isFloatingPoint())
- RC = VT.isVector() ? &SPIRV::vfIDRegClass
- : (VT.getScalarSizeInBits() > 32 ? &SPIRV::fID64RegClass
- : &SPIRV::fIDRegClass);
+ RC = VT.isVector() ? &SPIRV::vfIDRegClass : &SPIRV::fIDRegClass;
else if (VT.isInteger())
- RC = VT.isVector() ? &SPIRV::vIDRegClass
- : (VT.getScalarSizeInBits() > 32 ? &SPIRV::iID64RegClass
- : &SPIRV::iIDRegClass);
+ RC = VT.isVector() ? &SPIRV::vIDRegClass : &SPIRV::iIDRegClass;
else
RC = &SPIRV::iIDRegClass;
@@ -115,7 +111,7 @@ static void doInsertBitcast(const SPIRVSubtarget &STI, MachineRegisterInfo *MRI,
SPIRVGlobalRegistry &GR, MachineInstr &I,
Register OpReg, unsigned OpIdx,
SPIRVType *NewPtrType) {
- Register NewReg = MRI->createGenericVirtualRegister(LLT::scalar(32));
+ Register NewReg = MRI->createGenericVirtualRegister(LLT::scalar(64));
MachineIRBuilder MIB(I);
bool Res = MIB.buildInstr(SPIRV::OpBitcast)
.addDef(NewReg)
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.h b/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
index 77356b7512a739..37a2f4aa99c034 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
@@ -44,7 +44,7 @@ class SPIRVTargetLowering : public TargetLowering {
// This is to prevent sexts of non-i64 vector indices which are generated
// within general IRTranslator hence type generation for it is omitted.
MVT getVectorIdxTy(const DataLayout &DL) const override {
- return MVT::getIntegerVT(32);
+ return MVT::getIntegerVT(32); // lev
}
unsigned getNumRegistersForCallingConv(LLVMContext &Context,
CallingConv::ID CC,
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
index 12cf7613a45cf3..dac7640cdddd69 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
@@ -256,12 +256,9 @@ void SPIRVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
}
bool SPIRVInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
- if (MI.getOpcode() == SPIRV::GET_ID || MI.getOpcode() == SPIRV::GET_ID64 ||
- MI.getOpcode() == SPIRV::GET_fID || MI.getOpcode() == SPIRV::GET_fID64 ||
- MI.getOpcode() == SPIRV::GET_pID32 ||
- MI.getOpcode() == SPIRV::GET_pID64 || MI.getOpcode() == SPIRV::GET_vfID ||
- MI.getOpcode() == SPIRV::GET_vID || MI.getOpcode() == SPIRV::GET_vpID32 ||
- MI.getOpcode() == SPIRV::GET_vpID64) {
+ if (MI.getOpcode() == SPIRV::GET_ID || MI.getOpcode() == SPIRV::GET_fID ||
+ MI.getOpcode() == SPIRV::GET_pID || MI.getOpcode() == SPIRV::GET_vfID ||
+ MI.getOpcode() == SPIRV::GET_vID || MI.getOpcode() == SPIRV::GET_vpID) {
auto &MRI = MI.getMF()->getRegInfo();
MRI.replaceRegWith(MI.getOperand(0).getReg(), MI.getOperand(1).getReg());
MI.eraseFromParent();
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index c4b09dd6bfe430..2298011d0d656a 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -15,18 +15,14 @@ include "SPIRVSymbolicOperands.td"
// Codegen only metadata instructions
let isCodeGenOnly=1 in {
- def ASSIGN_TYPE: Pseudo<(outs ANYID:$dst_id), (ins ANYID:$src_id, TYPE:$src_ty)>;
- def DECL_TYPE: Pseudo<(outs ANYID:$dst_id), (ins ANYID:$src_id, TYPE:$src_ty)>;
- def GET_ID: Pseudo<(outs iID:$dst_id), (ins ANYID:$src)>;
- def GET_ID64: Pseudo<(outs iID64:$dst_id), (ins ANYID:$src)>;
- def GET_fID: Pseudo<(outs fID:$dst_id), (ins ANYID:$src)>;
- def GET_fID64: Pseudo<(outs fID64:$dst_id), (ins ANYID:$src)>;
- def GET_pID32: Pseudo<(outs pID32:$dst_id), (ins ANYID:$src)>;
- def GET_pID64: Pseudo<(outs pID64:$dst_id), (ins ANYID:$src)>;
- def GET_vID: Pseudo<(outs vID:$dst_id), (ins ANYID:$src)>;
- def GET_vfID: Pseudo<(outs vfID:$dst_id), (ins ANYID:$src)>;
- def GET_vpID32: Pseudo<(outs vpID32:$dst_id), (ins ANYID:$src)>;
- def GET_vpID64: Pseudo<(outs vpID64:$dst_id), (ins ANYID:$src)>;
+ def ASSIGN_TYPE: Pseudo<(outs ID:$dst_id), (ins ID:$src_id, TYPE:$src_ty)>;
+ def DECL_TYPE: Pseudo<(outs ID:$dst_id), (ins ID:$src_id, TYPE:$src_ty)>;
+ def GET_ID: Pseudo<(outs iID:$dst_id), (ins ID:$src)>;
+ def GET_fID: Pseudo<(outs fID:$dst_id), (ins ID:$src)>;
+ def GET_pID: Pseudo<(outs pID:$dst_id), (ins ID:$src)>;
+ def GET_vID: Pseudo<(outs vID:$dst_id), (ins ID:$src)>;
+ def GET_vfID: Pseudo<(outs vfID:$dst_id), (ins ID:$src)>;
+ def GET_vpID: Pseudo<(outs vpID:$dst_id), (ins ID:$src)>;
}
def SPVTypeBin : SDTypeProfile<1, 2, []>;
@@ -36,16 +32,18 @@ def assigntype : SDNode<"SPIRVISD::AssignType", SPVTypeBin>;
def : GINodeEquiv<ASSIGN_TYPE, assigntype>;
class BinOp<string name, bits<16> opCode, list<dag> pattern=[]>
- : Op<opCode, (outs ANYID:$dst), (ins TYPE:$src_ty, ANYID:$src, ANYID:$src2),
+ : Op<opCode, (outs ID:$dst), (ins TYPE:$src_ty, ID:$src, ID:$src2),
"$dst = "#name#" $src_ty $src $src2", pattern>;
class BinOpTyped<string name, bits<16> opCode, RegisterClass CID, SDNode node>
: Op<opCode, (outs iID:$dst), (ins TYPE:$src_ty, CID:$src, CID:$src2),
- "$dst = "#name#" $src_ty $src $src2", [(set iID:$dst, (assigntype (node CID:$src, CID:$src2), TYPE:$src_ty))]>;
+ "$dst = "#name#" $src_ty $src $src2",
+ [(set iID:$dst, (assigntype (node CID:$src, CID:$src2), TYPE:$src_ty))]>;
class TernOpTyped<string name, bits<16> opCode, RegisterClass CCond, RegisterClass CID, SDNode node>
: Op<opCode, (outs iID:$dst), (ins TYPE:$src_ty, CCond:$cond, CID:$src1, CID:$src2),
- "$dst = "#name#" $src_ty $cond $src1 $src2", [(set iID:$dst, (assigntype (node CCond:$cond, CID:$src1, CID:$src2), TYPE:$src_ty))]>;
+ "$dst = "#name#" $src_ty $cond $src1 $src2",
+ [(set iID:$dst, (assigntype (node CCond:$cond, CID:$src1, CID:$src2), TYPE:$src_ty))]>;
multiclass BinOpTypedGen<string name, bits<16> opCode, SDNode node, bit genF = 0, bit genV = 0> {
if genF then
@@ -70,10 +68,8 @@ multiclass TernOpTypedGen<string name, bits<16> opCode, SDNode node, bit genP =
def SIVCond: TernOpTyped<name, opCode, vID, iID, node>;
}
if genP then {
- def SPSCond32: TernOpTyped<name, opCode, iID, pID32, node>;
- def SPVCond32: TernOpTyped<name, opCode, vID, pID32, node>;
- def SPSCond64: TernOpTyped<name, opCode, iID, pID64, node>;
- def SPVCond64: TernOpTyped<name, opCode, vID, pID64, node>;
+ def SPSCond: TernOpTyped<name, opCode, iID, pID, node>;
+ def SPVCond: TernOpTyped<name, opCode, vID, pID, node>;
}
if genV then {
if genF then {
@@ -85,16 +81,14 @@ multiclass TernOpTypedGen<string name, bits<16> opCode, SDNode node, bit genP =
def VIVCond: TernOpTyped<name, opCode, vID, vID, node>;
}
if genP then {
- def VPSCond32: TernOpTyped<name, opCode, iID, vpID32, node>;
- def VPVCond32: TernOpTyped<name, opCode, vID, vpID32, node>;
- def VPSCond64: TernOpTyped<name, opCode, iID, vpID64, node>;
- def VPVCond64: TernOpTyped<name, opCode, vID, vpID64, node>;
+ def VPSCond: TernOpTyped<name, opCode, iID, vpID, node>;
+ def VPVCond: TernOpTyped<name, opCode, vID, vpID, node>;
}
}
}
class UnOp<string name, bits<16> opCode, list<dag> pattern=[]>
- : Op<opCode, (outs ANYID:$dst), (ins TYPE:$type, ANYID:$src),
+ : Op<opCode, (outs ID:$dst), (ins TYPE:$type, ID:$src),
"$dst = "#name#" $type $src", pattern>;
class UnOpTyped<string name, bits<16> opCode, RegisterClass CID, SDNode node>
: Op<opCode, (outs iID:$dst), (ins TYPE:$src_ty, CID:$src),
@@ -222,21 +216,21 @@ return CurDAG->getTargetConstant(
N->getValueAP().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
}]>;
-def fimm_to_i32 : SDNodeXForm<imm, [{
+def fimm_to_i64 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(
- N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
+ N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
}]>;
-def gi_bitcast_fimm_to_i32 : GICustomOperandRenderer<"renderFImm32">,
- GISDNodeXFormEquiv<fimm_to_i32>;
+def gi_bitcast_fimm_to_i64 : GICustomOperandRenderer<"renderFImm64">,
+ GISDNodeXFormEquiv<fimm_to_i64>;
def gi_bitcast_imm_to_i32 : GICustomOperandRenderer<"renderImm32">,
GISDNodeXFormEquiv<imm_to_i32>;
-def PseudoConstI: IntImmLeaf<i32, [{ return Imm.getBitWidth() <= 32; }], imm_to_i32>;
-def PseudoConstF: FPImmLeaf<f32, [{ return true; }], fimm_to_i32>;
-def ConstPseudoTrue: IntImmLeaf<i32, [{ return Imm.getBitWidth() == 1 && Imm.getZExtValue() == 1; }]>;
-def ConstPseudoFalse: IntImmLeaf<i32, [{ return Imm.getBitWidth() == 1 && Imm.getZExtValue() == 0; }]>;
+def PseudoConstI: IntImmLeaf<i64, [{ return Imm.getBitWidth() <= 32; }], imm_to_i32>;
+def PseudoConstF: FPImmLeaf<f64, [{ return true; }], fimm_to_i64>;
+def ConstPseudoTrue: IntImmLeaf<i64, [{ return Imm.getBitWidth() == 1 && Imm.getZExtValue() == 1; }]>;
+def ConstPseudoFalse: IntImmLeaf<i64, [{ return Imm.getBitWidth() == 1 && Imm.getZExtValue() == 0; }]>;
def ConstPseudoNull: IntImmLeaf<i64, [{ return Imm.isZero(); }]>;
multiclass IntFPImm<bits<16> opCode, string name> {
@@ -634,7 +628,7 @@ let isTerminator=1 in {
let isReturn = 1, hasDelaySlot=0, isBarrier = 0, isTerminator=1, isNotDuplicable = 1 in {
def OpKill: SimpleOp<"OpKill", 252>;
def OpReturn: SimpleOp<"OpReturn", 253>;
- def OpReturnValue: Op<254, (outs), (ins ANYID:$ret), "OpReturnValue $ret">;
+ def OpReturnValue: Op<254, (outs), (ins ID:$ret), "OpReturnValue $ret">;
def OpUnreachable: SimpleOp<"OpUnreachable", 255>;
}
def OpLifetimeStart: Op<256, (outs), (ins ID:$ptr, i32imm:$sz), "OpLifetimeStart $ptr, $sz">;
@@ -862,9 +856,9 @@ def OpGroupLogicalXorKHR: Op<6408, (outs ID:$res), (ins TYPE:$type, ID:$scope, i
"$res = OpGroupLogicalXorKHR $type $scope $groupOp $value">;
// Inline Assembly Instructions
-def OpAsmTargetINTEL: Op<5609, (outs ID:$res), (ins StringImm:$str), "$res = OpAsmTargetINTEL $str">;
+def OpAsmTargetINTEL: Op<5609, (outs ID:$res), (ins StringImm:$str, variable_ops), "$res = OpAsmTargetINTEL $str">;
def OpAsmINTEL: Op<5610, (outs ID:$res), (ins TYPE:$type, TYPE:$asm_type, ID:$target,
- StringImm:$asm, StringImm:$constraints),
+ StringImm:$asm, StringImm:$constraints, variable_ops),
"$res = OpAsmINTEL $type $asm_type $target $asm">;
def OpAsmCallINTEL: Op<5611, (outs ID:$res), (ins TYPE:$type, ID:$asm, variable_ops),
"$res = OpAsmCallINTEL $type $asm">;
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index ecb3cee4e781af..712700aa346be9 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -186,7 +186,7 @@ class SPIRVInstructionSelector : public InstructionSelector {
void renderImm32(MachineInstrBuilder &MIB, const MachineInstr &I,
int OpIdx) const;
- void renderFImm32(MachineInstrBuilder &MIB, const MachineInstr &I,
+ void renderFImm64(MachineInstrBuilder &MIB, const MachineInstr &I,
int OpIdx) const;
bool selectConst(Register ResVReg, const SPIRVType *ResType, const APInt &Imm,
@@ -305,14 +305,8 @@ void SPIRVInstructionSelector::resetVRegsType(MachineFunction &MF) {
HasVRegsReset = &MF;
MachineRegisterInfo &MRI = MF.getRegInfo();
- for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
- Register Reg = Register::index2VirtReg(I);
- LLT Ty = MRI.getType(Reg);
- if (Ty.isScalar())
- MRI.setType(Reg, LLT::scalar(32));
- else if (Ty.isVector() && !Ty.isPointer())
- MRI.setType(Reg, LLT::scalar(32));
- }
+ for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I)
+ MRI.setType(Register::index2VirtReg(I), LLT::scalar(64));
for (const auto &MBB : MF) {
for (const auto &MI : MBB) {
if (MI.getOpcode() != SPIRV::ASSIGN_TYPE)
@@ -351,9 +345,13 @@ bool SPIRVInstructionSelector::select(MachineInstr &I) {
Register SrcReg = I.getOperand(1).getReg();
auto *Def = MRI->getVRegDef(SrcReg);
if (isTypeFoldingSupported(Def->getOpcode())) {
- if (MRI->getType(DstReg).isPointer())
- MRI->setType(DstReg, LLT::scalar(32));
bool Res = selectImpl(I, *CoverageInfo);
+ LLVM_DEBUG({
+ if (!Res && Def->getOpcode() != TargetOpcode::G_CONSTANT) {
+ dbgs() << "Unexpected pattern in ASSIGN_TYPE.\nInstruction: ";
+ I.print(dbgs());
+ }
+ });
assert(Res || Def->getOpcode() == TargetOpcode::G_CONSTANT);
if (Res)
return Res;
@@ -363,8 +361,8 @@ bool SPIRVInstructionSelector::select(MachineInstr &I) {
I.removeFromParent();
return true;
} else if (I.getNumDefs() == 1) {
- // Make all vregs 32 bits (for SPIR-V IDs).
- MRI->setType(I.getOperand(0).getReg(), LLT::scalar(32));
+ // Make all vregs 64 bits (for SPIR-V IDs).
+ MRI->setType(I.getOperand(0).getReg(), LLT::scalar(64));
}
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
}
@@ -381,9 +379,9 @@ bool SPIRVInstructionSelector::select(MachineInstr &I) {
SPIRVType *ResType = HasDefs ? GR.getSPIRVTypeForVReg(ResVReg) : nullptr;
assert(!HasDefs || ResType || I.getOpcode() == TargetOpcode::G_GLOBAL_VALUE);
if (spvSelect(ResVReg, ResType, I)) {
- if (HasDefs) // Make all vregs 32 bits (for SPIR-V IDs).
+ if (HasDefs) // Make all vregs 64 bits (for SPIR-V IDs).
for (unsigned i = 0; i < I.getNumDefs(); ++i)
- MRI->setType(I.getOperand(i).getReg(), LLT::scalar(32));
+ MRI->setType(I.getOperand(i).getReg(), LLT::scalar(64));
I.removeFromParent();
return true;
}
@@ -909,7 +907,7 @@ bool SPIRVInstructionSelector::selectMemOperation(Register ResVReg,
GlobalVariable *GV = new GlobalVariable(*CurFunction.getParent(), LLVMArrTy,
true, GlobalValue::InternalLinkage,
Constant::getNullValue(LLVMArrTy));
- Register VarReg = MRI->createGenericVirtualRegister(LLT::scalar(32));
+ Register VarReg = MRI->createGenericVirtualRegister(LLT::scalar(64));
GR.add(GV, GR.CurMF, VarReg);
buildOpDecorate(VarReg, I, TII, SPIRV::Decoration::Constant, {});
@@ -921,7 +919,7 @@ bool SPIRVInstructionSelector::selectMemOperation(Register ResVReg,
.constrainAllUses(TII, TRI, RBI);
SPIRVType *SourceTy = GR.getOrCreateSPIRVPointerType(
ValTy, I, TII, SPIRV::StorageClass::UniformConstant);
- SrcReg = MRI->createGenericVirtualRegister(LLT::scalar(32));
+ SrcReg = MRI->createGenericVirtualRegister(LLT::scalar(64));
selectUnOpWithSrc(SrcReg, SourceTy, I, VarReg, SPIRV::OpBitcast);
}
auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCopyMemorySized))
@@ -1716,7 +1714,7 @@ bool SPIRVInstructionSelector::selectICmp(Register ResVReg,
return selectCmp(ResVReg, ResType, CmpOpc, I);
}
-void SPIRVInstructionSelector::renderFImm32(MachineInstrBuilder &MIB,
+void SPIRVInstructionSelector::renderFImm64(MachineInstrBuilder &MIB,
const MachineInstr &I,
int OpIdx) const {
assert(I.getOpcode() == TargetOpcode::G_FCONSTANT && OpIdx == -1 &&
@@ -1736,14 +1734,14 @@ void SPIRVInstructionSelector::renderImm32(MachineInstrBuilder &MIB,
Register
SPIRVInstructionSelector::buildI32Constant(uint32_t Val, MachineInstr &I,
const SPIRVType *ResType) const {
- Type *LLVMTy = IntegerType::get(GR.CurMF->getFunction().getContext(), 32);
+ Type *LLVMTy = IntegerType::get(GR.CurMF->getFunction().getContext(), 32); // lev
const SPIRVType *SpvI32Ty =
ResType ? ResType : GR.getOrCreateSPIRVIntegerType(32, I, TII);
// Find a constant in DT or build a new one.
auto ConstInt = ConstantInt::get(LLVMTy, Val);
Register NewReg = GR.find(ConstInt, GR.CurMF);
if (!NewReg.isValid()) {
- NewReg = MRI->createGenericVirtualRegister(LLT::scalar(32));
+ NewReg = MRI->createGenericVirtualRegister(LLT::scalar(64));
GR.add(ConstInt, GR.CurMF, NewReg);
MachineInstr *MI;
MachineBasicBlock &BB = *I.getParent();
@@ -1939,7 +1937,7 @@ bool SPIRVInstructionSelector::selectConst(Register ResVReg,
.addDef(ResVReg)
.addUse(GR.getSPIRVTypeID(ResType));
// <=32-bit integers should be caught by the sdag pattern.
- assert(Imm.getBitWidth() > 32);
+ assert(Imm.getBitWidth() > 32); // lev
addNumImm(Imm, MIB);
return MIB.constrainAllUses(TII, TRI, RBI);
}
@@ -2089,7 +2087,7 @@ bool SPIRVInstructionSelector::wrapIntoSpecConstantOp(
GR.add(OpDefine, MF, WrapReg);
CompositeArgs.push_back(WrapReg);
// Decorate the wrapper register and generate a new instruction
- MRI->setType(WrapReg, LLT::pointer(0, 32));
+ MRI->setType(WrapReg, LLT::pointer(0, 64));
GR.assignSPIRVTypeToVReg(OpType, WrapReg, *MF);
MachineBasicBlock &BB = *I.getParent();
Result = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSpecConstantOp))
@@ -2402,7 +2400,7 @@ bool SPIRVInstructionSelector::selectGlobalValue(
// registers without a definition. We will resolve it later, during
// module analysis stage.
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
- Register FuncVReg = MRI->createGenericVirtualRegister(LLT::scalar(32));
+ Register FuncVReg = MRI->createGenericVirtualRegister(LLT::scalar(64));
MRI->setRegClass(FuncVReg, &SPIRV::iIDRegClass);
MachineInstrBuilder MB =
BuildMI(BB, I, I.getDebugLoc(),
@@ -2513,7 +2511,7 @@ bool SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
// 93 ThreadId reads the thread ID
MachineIRBuilder MIRBuilder(I);
- const SPIRVType *U32Type = GR.getOrCreateSPIRVIntegerType(32, MIRBuilder);
+ const SPIRVType *U32Type = GR.getOrCreateSPIRVIntegerType(32, MIRBuilder); // lev
const SPIRVType *Vec3Ty =
GR.getOrCreateSPIRVVectorType(U32Type, 3, MIRBuilder);
const SPIRVType *PtrType = GR.getOrCreateSPIRVPointerType(
@@ -2522,7 +2520,7 @@ bool SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
// Create new register for GlobalInvocationID builtin variable.
Register NewRegister =
MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::iIDRegClass);
- MIRBuilder.getMRI()->setType(NewRegister, LLT::pointer(0, 32));
+ MIRBuilder.getMRI()->setType(NewRegister, LLT::pointer(0, 64));
GR.assignSPIRVTypeToVReg(PtrType, NewRegister, MIRBuilder.getMF());
// Build GlobalInvocationID global variable with the necessary decorations.
@@ -2535,7 +2533,7 @@ bool SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
// Create new register for loading value.
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
Register LoadedRegister = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
- MIRBuilder.getMRI()->setType(LoadedRegister, LLT::pointer(0, 32));
+ MIRBuilder.getMRI()->setType(LoadedRegister, LLT::pointer(0, 64));
GR.assignSPIRVTypeToVReg(Vec3Ty, LoadedRegister, MIRBuilder.getMF());
// Load v3uint value from the global variable.
diff --git a/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
index 44685be3d68ad4..7516d61a67724d 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
@@ -54,11 +54,9 @@ extern void processInstr(MachineInstr &MI, MachineIRBuilder &MIB,
} // namespace llvm
static bool isMetaInstrGET(unsigned Opcode) {
- return Opcode == SPIRV::GET_ID || Opcode == SPIRV::GET_ID64 ||
- Opcode == SPIRV::GET_fID || Opcode == SPIRV::GET_fID64 ||
- Opcode == SPIRV::GET_pID32 || Opcode == SPIRV::GET_pID64 ||
- Opcode == SPIRV::GET_vID || Opcode == SPIRV::GET_vfID ||
- Opcode == SPIRV::GET_vpID32 || Opcode == SPIRV::GET_vpID64;
+ return Opcode == SPIRV::GET_ID || Opcode == SPIRV::GET_fID ||
+ Opcode == SPIRV::GET_pID || Opcode == SPIRV::GET_vID ||
+ Opcode == SPIRV::GET_vfID || Opcode == SPIRV::GET_vpID;
}
static bool mayBeInserted(unsigned Opcode) {
@@ -138,10 +136,8 @@ static void processNewInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
continue;
// Restore usual instructions pattern for the newly inserted
// instruction
- MRI.setRegClass(ResVReg, MRI.getType(ResVReg).isVector()
- ? &SPIRV::iIDRegClass
- : &SPIRV::ANYIDRegClass);
- MRI.setType(ResVReg, LLT::scalar(32));
+ MRI.setRegClass(ResVReg, &SPIRV::iIDRegClass);
+ MRI.setType(ResVReg, LLT::scalar(64));
insertAssignInstr(ResVReg, nullptr, ResVType, GR, MIB, MRI);
processInstr(I, MIB, MRI, GR);
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 7c158abba3c28c..3438782c0016be 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -323,8 +323,7 @@ static const TargetRegisterClass *getRegClass(SPIRVType *SpvType,
case SPIRV::OpTypeFloat:
return &SPIRV::fIDRegClass;
case SPIRV::OpTypePointer:
- return GR.getPointerSize() == 64 ? &SPIRV::pID64RegClass
- : &SPIRV::pID32RegClass;
+ return &SPIRV::pIDRegClass;
case SPIRV::OpTypeVector: {
SPIRVType *ElemType =
GR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg());
@@ -332,8 +331,7 @@ static const TargetRegisterClass *getRegClass(SPIRVType *SpvType,
if (ElemOpcode == SPIRV::OpTypeFloat)
return &SPIRV::vfIDRegClass;
if (ElemOpcode == SPIRV::OpTypePointer)
- return GR.getPointerSize() == 64 ? &SPIRV::vpID64RegClass
- : &SPIRV::vpID32RegClass;
+ return &SPIRV::vpIDRegClass;
return &SPIRV::vIDRegClass;
}
}
@@ -356,10 +354,7 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
bool IsVec = SrcLLT.isVector();
if (IsVec)
NewT = LLT::fixed_vector(2, NewT);
- if (PtrSz == 64)
- GetIdOp = IsVec ? SPIRV::GET_vpID64 : SPIRV::GET_pID64;
- else
- GetIdOp = IsVec ? SPIRV::GET_vpID32 : SPIRV::GET_pID32;
+ GetIdOp = IsVec ? SPIRV::GET_vpID : SPIRV::GET_pID;
} else if (SrcLLT.isVector()) {
NewT = LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
NewT = LLT::fixed_vector(2, NewT);
@@ -501,6 +496,8 @@ generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
if (isSpvIntrinsic(UseMI, Intrinsic::spv_assign_type) ||
isSpvIntrinsic(UseMI, Intrinsic::spv_assign_name))
continue;
+ if (UseMI.getOpcode() == SPIRV::ASSIGN_TYPE)
+ NeedAssignType = false;
}
Type *Ty = nullptr;
if (MIOp == TargetOpcode::G_CONSTANT) {
@@ -619,8 +616,8 @@ static void processInstrsWithTypeFolding(MachineFunction &MF,
if (UseMI.getOpcode() == TargetOpcode::G_ADDRSPACE_CAST)
continue;
}
- if (MRI.getType(DstReg).isPointer())
- MRI.setType(DstReg, LLT::pointer(0, GR->getPointerSize()));
+// if (MRI.getType(DstReg).isPointer())
+// MRI.setType(DstReg, LLT::pointer(0, GR->getPointerSize()));
}
}
}
@@ -634,7 +631,7 @@ insertInlineAsmProcess(MachineFunction &MF, SPIRVGlobalRegistry *GR,
for (unsigned i = 0, Sz = ToProcess.size(); i + 1 < Sz; i += 2) {
MachineInstr *I1 = ToProcess[i], *I2 = ToProcess[i + 1];
assert(isSpvIntrinsic(*I1, Intrinsic::spv_inline_asm) && I2->isInlineAsm());
- MIRBuilder.setInsertPt(*I1->getParent(), *I1);
+ MIRBuilder.setInsertPt(*I2->getParent(), *I2);
if (!AsmTargetReg.isValid()) {
// define vendor specific assembly target or dialect
@@ -714,10 +711,10 @@ insertInlineAsmProcess(MachineFunction &MF, SPIRVGlobalRegistry *GR,
unsigned IntrIdx = 2;
for (unsigned Idx : Ops) {
++IntrIdx;
- const MachineOperand &MO = I2->getOperand(Idx);
- if (MO.isReg())
- AsmCall.addUse(MO.getReg());
- else
+ //const MachineOperand &MO = I2->getOperand(Idx);
+ //if (MO.isReg())
+ // AsmCall.addUse(MO.getReg());
+ //else
AsmCall.addUse(I1->getOperand(IntrIdx).getReg());
}
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td b/llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
index 936ad8e684b3e2..1ef42b79f1a8ea 100644
--- a/llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
@@ -12,7 +12,6 @@
let Namespace = "SPIRV" in {
// Pointer types for patterns with the GlobalISelEmitter
- def p32 : PtrValueType <i32, 0>;
def p64 : PtrValueType <i64, 0>;
class VTPtrVec<int nelem, PtrValueType ptr>
@@ -20,50 +19,35 @@ let Namespace = "SPIRV" in {
int isPointer = true;
}
- def v2p32 : VTPtrVec<2, p32>;
def v2p64 : VTPtrVec<2, p64>;
// Class for type registers
def TYPE0 : Register<"TYPE0">;
- def TYPE : RegisterClass<"SPIRV", [i32], 32, (add TYPE0)>;
+ def TYPE : RegisterClass<"SPIRV", [i64], 64, (add TYPE0)>;
// Class for non-type registers
def ID0 : Register<"ID0">;
- def ID640 : Register<"ID640">;
def fID0 : Register<"fID0">;
- def fID640 : Register<"fID640">;
- def pID320 : Register<"pID320">;
- def pID640 : Register<"pID640">;
+ def pID0 : Register<"pID0">;
def vID0 : Register<"vID0">;
def vfID0 : Register<"vfID0">;
- def vpID320 : Register<"vpID320">;
- def vpID640 : Register<"vpID640">;
-
- def iID : RegisterClass<"SPIRV", [i32], 32, (add ID0)>;
- def iID64 : RegisterClass<"SPIRV", [i64], 32, (add ID640)>;
- def fID : RegisterClass<"SPIRV", [f32], 32, (add fID0)>;
- def fID64 : RegisterClass<"SPIRV", [f64], 32, (add fID640)>;
- def pID32 : RegisterClass<"SPIRV", [p32], 32, (add pID320)>;
- def pID64 : RegisterClass<"SPIRV", [p64], 32, (add pID640)>;
- def vID : RegisterClass<"SPIRV", [v2i32], 32, (add vID0)>;
- def vfID : RegisterClass<"SPIRV", [v2f32], 32, (add vfID0)>;
- def vpID32 : RegisterClass<"SPIRV", [v2p32], 32, (add vpID320)>;
- def vpID64 : RegisterClass<"SPIRV", [v2p64], 32, (add vpID640)>;
-
+ def vpID0 : Register<"vpID0">;
+
+ def iID : RegisterClass<"SPIRV", [i64], 64, (add ID0)>;
+ def fID : RegisterClass<"SPIRV", [f64], 64, (add fID0)>;
+ def pID : RegisterClass<"SPIRV", [p64], 64, (add pID0)>;
+ def vID : RegisterClass<"SPIRV", [v2i64], 64, (add vID0)>;
+ def vfID : RegisterClass<"SPIRV", [v2f64], 64, (add vfID0)>;
+ def vpID : RegisterClass<"SPIRV", [v2p64], 64, (add vpID0)>;
+
def ID : RegisterClass<
"SPIRV",
- [i32, i64, f32, f64, p32, p64, v2i32, v2f32, v2p32, v2p64],
- 32,
- (add iID, iID64, fID, fID64, pID32, pID64, vID, vfID, vpID32, vpID64)>;
-
- def ANYID : RegisterClass<
- "SPIRV",
- [i32, i64, f32, f64, p32, p64, v2i32, v2f32, v2p32, v2p64],
- 32,
- (add ID0, ID640, fID0, fID640, pID320, pID640, vID0, vfID0, vpID320, vpID640)>;
+ [i64, f64, p64, v2i64, v2f64, v2p64],
+ 64,
+ (add iID, fID, pID, vID, vfID, vpID)>;
// A few instructions like OpName can take ids from both type and non-type
// instructions, so we need a super-class to allow for both to count as valid
// arguments for these instructions.
- def ANY : RegisterClass<"SPIRV", [i32], 32, (add TYPE, ID)>;
+ def ANY : RegisterClass<"SPIRV", [i64], 64, (add TYPE, ID)>;
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVRegularizer.cpp b/llvm/lib/Target/SPIRV/SPIRVRegularizer.cpp
index 322e051a87db1a..003e0ee2f240a0 100644
--- a/llvm/lib/Target/SPIRV/SPIRVRegularizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVRegularizer.cpp
@@ -232,7 +232,7 @@ void SPIRVRegularizer::visitCallScalToVec(CallInst *CI, StringRef MangledName,
// %10 = OpCompositeInsert %v2uint %uint_5 %8 0
// %11 = OpVectorShuffle %v2uint %10 %8 0 0
// %call = OpExtInst %v2uint %1 s_min %14 %11
- auto ConstInt = ConstantInt::get(IntegerType::get(CI->getContext(), 32), 0);
+ auto ConstInt = ConstantInt::get(IntegerType::get(CI->getContext(), 32), 0); // lev
PoisonValue *PVal = PoisonValue::get(Arg0Ty);
Instruction *Inst =
InsertElementInst::Create(PVal, CI->getOperand(1), ConstInt, "", CI);
>From fc161ee0c427a6284e67d62d30116ca90d507f21 Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Mon, 19 Aug 2024 01:43:20 -0700
Subject: [PATCH 02/14] apply clang-format; simplify inline asm operands usage
---
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 8 +--
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp | 4 +-
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 6 +-
llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 65 ++++++++++---------
llvm/lib/Target/SPIRV/SPIRVRegularizer.cpp | 2 +-
5 files changed, 45 insertions(+), 40 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index dadfee03c5bc41..03f0390c2a1aca 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -2140,8 +2140,8 @@ static bool buildEnqueueKernel(const SPIRV::IncomingCall *Call,
auto GEPInst = MIRBuilder.buildIntrinsic(
Intrinsic::spv_gep, ArrayRef<Register>{Reg}, true, false);
GEPInst
- .addImm(GepMI->getOperand(2).getImm()) // In bound.
- .addUse(ArrayMI->getOperand(0).getReg()) // Alloca.
+ .addImm(GepMI->getOperand(2).getImm()) // In bound.
+ .addUse(ArrayMI->getOperand(0).getReg()) // Alloca.
.addUse(buildConstantIntReg32(0, MIRBuilder, GR)) // Indices.
.addUse(buildConstantIntReg32(I, MIRBuilder, GR));
LocalSizes.push_back(Reg);
@@ -2181,8 +2181,8 @@ static bool buildEnqueueKernel(const SPIRV::IncomingCall *Call,
// Param Size: Size of block literal structure.
MIB.addUse(buildConstantIntReg32(DL.getTypeStoreSize(PType), MIRBuilder, GR));
// Param Aligment: Aligment of block literal structure.
- MIB.addUse(
- buildConstantIntReg32(DL.getPrefTypeAlign(PType).value(), MIRBuilder, GR));
+ MIB.addUse(buildConstantIntReg32(DL.getPrefTypeAlign(PType).value(),
+ MIRBuilder, GR));
for (unsigned i = 0; i < LocalSizes.size(); i++)
MIB.addUse(LocalSizes[i]);
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
index 621b6bdf71cd06..19fe0ad2ede3f1 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
@@ -287,7 +287,8 @@ Register SPIRVGlobalRegistry::buildConstantInt(uint64_t Val,
bool EmitIR) {
assert(SpvType);
auto &MF = MIRBuilder.getMF();
- const IntegerType *LLVMIntTy = cast<IntegerType>(getTypeForSPIRVType(SpvType));
+ const IntegerType *LLVMIntTy =
+ cast<IntegerType>(getTypeForSPIRVType(SpvType));
// Find a constant in DT or build a new one.
const auto ConstInt =
ConstantInt::get(const_cast<IntegerType *>(LLVMIntTy), Val);
@@ -635,7 +636,6 @@ Register SPIRVGlobalRegistry::buildGlobalVariable(
// Set to Reg the same type as ResVReg has.
auto MRI = MIRBuilder.getMRI();
-// assert(MRI->getType(ResVReg).isPointer() && "Pointer type is expected");
if (Reg != ResVReg) {
LLT RegLLTy =
LLT::pointer(MRI->getType(ResVReg).getAddressSpace(), getPointerSize());
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 712700aa346be9..35e9aca8b9fd9e 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -1734,7 +1734,8 @@ void SPIRVInstructionSelector::renderImm32(MachineInstrBuilder &MIB,
Register
SPIRVInstructionSelector::buildI32Constant(uint32_t Val, MachineInstr &I,
const SPIRVType *ResType) const {
- Type *LLVMTy = IntegerType::get(GR.CurMF->getFunction().getContext(), 32); // lev
+ Type *LLVMTy =
+ IntegerType::get(GR.CurMF->getFunction().getContext(), 32); // lev
const SPIRVType *SpvI32Ty =
ResType ? ResType : GR.getOrCreateSPIRVIntegerType(32, I, TII);
// Find a constant in DT or build a new one.
@@ -2511,7 +2512,8 @@ bool SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
// 93 ThreadId reads the thread ID
MachineIRBuilder MIRBuilder(I);
- const SPIRVType *U32Type = GR.getOrCreateSPIRVIntegerType(32, MIRBuilder); // lev
+ const SPIRVType *U32Type =
+ GR.getOrCreateSPIRVIntegerType(32, MIRBuilder); // lev
const SPIRVType *Vec3Ty =
GR.getOrCreateSPIRVVectorType(U32Type, 3, MIRBuilder);
const SPIRVType *PtrType = GR.getOrCreateSPIRVPointerType(
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 3438782c0016be..2decfd2748dfae 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -616,12 +616,39 @@ static void processInstrsWithTypeFolding(MachineFunction &MF,
if (UseMI.getOpcode() == TargetOpcode::G_ADDRSPACE_CAST)
continue;
}
-// if (MRI.getType(DstReg).isPointer())
-// MRI.setType(DstReg, LLT::pointer(0, GR->getPointerSize()));
}
}
}
+static Register
+collectInlineAsmInstrOperands(MachineInstr *MI,
+ SmallVector<unsigned, 4> *Ops = nullptr) {
+ Register DefReg;
+ unsigned StartOp = InlineAsm::MIOp_FirstOperand,
+ AsmDescOp = InlineAsm::MIOp_FirstOperand;
+ for (unsigned Idx = StartOp, MISz = MI->getNumOperands(); Idx != MISz;
+ ++Idx) {
+ const MachineOperand &MO = MI->getOperand(Idx);
+ if (MO.isMetadata())
+ continue;
+ if (Idx == AsmDescOp && MO.isImm()) {
+ // compute the index of the next operand descriptor
+ const InlineAsm::Flag F(MO.getImm());
+ AsmDescOp += 1 + F.getNumOperandRegisters();
+ continue;
+ }
+ if (MO.isReg() && MO.isDef()) {
+ if (!Ops)
+ return MO.getReg();
+ else
+ DefReg = MO.getReg();
+ } else if (Ops) {
+ Ops->push_back(Idx);
+ }
+ }
+ return DefReg;
+}
+
static void
insertInlineAsmProcess(MachineFunction &MF, SPIRVGlobalRegistry *GR,
const SPIRVSubtarget &ST, MachineIRBuilder MIRBuilder,
@@ -677,26 +704,8 @@ insertInlineAsmProcess(MachineFunction &MF, SPIRVGlobalRegistry *GR,
MIRBuilder.buildInstr(SPIRV::OpDecorate)
.addUse(AsmReg)
.addImm(static_cast<uint32_t>(SPIRV::Decoration::SideEffectsINTEL));
- Register DefReg;
- SmallVector<unsigned, 4> Ops;
- unsigned StartOp = InlineAsm::MIOp_FirstOperand,
- AsmDescOp = InlineAsm::MIOp_FirstOperand;
- unsigned I2Sz = I2->getNumOperands();
- for (unsigned Idx = StartOp; Idx != I2Sz; ++Idx) {
- const MachineOperand &MO = I2->getOperand(Idx);
- if (MO.isMetadata())
- continue;
- if (Idx == AsmDescOp && MO.isImm()) {
- // compute the index of the next operand descriptor
- const InlineAsm::Flag F(MO.getImm());
- AsmDescOp += 1 + F.getNumOperandRegisters();
- } else {
- if (MO.isReg() && MO.isDef())
- DefReg = MO.getReg();
- else
- Ops.push_back(Idx);
- }
- }
+
+ Register DefReg = collectInlineAsmInstrOperands(I2);
if (!DefReg.isValid()) {
DefReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
MRI.setRegClass(DefReg, &SPIRV::iIDRegClass);
@@ -704,19 +713,13 @@ insertInlineAsmProcess(MachineFunction &MF, SPIRVGlobalRegistry *GR,
Type::getVoidTy(MF.getFunction().getContext()), MIRBuilder);
GR->assignSPIRVTypeToVReg(VoidType, DefReg, MF);
}
+
auto AsmCall = MIRBuilder.buildInstr(SPIRV::OpAsmCallINTEL)
.addDef(DefReg)
.addUse(GR->getSPIRVTypeID(RetType))
.addUse(AsmReg);
- unsigned IntrIdx = 2;
- for (unsigned Idx : Ops) {
- ++IntrIdx;
- //const MachineOperand &MO = I2->getOperand(Idx);
- //if (MO.isReg())
- // AsmCall.addUse(MO.getReg());
- //else
- AsmCall.addUse(I1->getOperand(IntrIdx).getReg());
- }
+ for (unsigned IntrIdx = 3; IntrIdx < I1->getNumOperands(); ++IntrIdx)
+ AsmCall.addUse(I1->getOperand(IntrIdx).getReg());
}
for (MachineInstr *MI : ToProcess)
MI->eraseFromParent();
diff --git a/llvm/lib/Target/SPIRV/SPIRVRegularizer.cpp b/llvm/lib/Target/SPIRV/SPIRVRegularizer.cpp
index 003e0ee2f240a0..322e051a87db1a 100644
--- a/llvm/lib/Target/SPIRV/SPIRVRegularizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVRegularizer.cpp
@@ -232,7 +232,7 @@ void SPIRVRegularizer::visitCallScalToVec(CallInst *CI, StringRef MangledName,
// %10 = OpCompositeInsert %v2uint %uint_5 %8 0
// %11 = OpVectorShuffle %v2uint %10 %8 0 0
// %call = OpExtInst %v2uint %1 s_min %14 %11
- auto ConstInt = ConstantInt::get(IntegerType::get(CI->getContext(), 32), 0); // lev
+ auto ConstInt = ConstantInt::get(IntegerType::get(CI->getContext(), 32), 0);
PoisonValue *PVal = PoisonValue::get(Arg0Ty);
Instruction *Inst =
InsertElementInst::Create(PVal, CI->getOperand(1), ConstInt, "", CI);
>From 51f2ead70d5ea738e0f5e16e9e15709c5b2ad53a Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Mon, 19 Aug 2024 05:08:54 -0700
Subject: [PATCH 03/14] address ptr bitcasts and OpExtInst
---
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp | 2 +-
llvm/lib/Target/SPIRV/SPIRVISelLowering.h | 2 +-
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 7 +++++--
llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp | 8 +++-----
llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp | 11 +++++------
llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 14 ++++++++++++--
llvm/lib/Target/SPIRV/SPIRVSubtarget.h | 2 ++
.../SPV_INTEL_inline_assembly/inline_asm.ll | 2 +-
llvm/test/CodeGen/SPIRV/llvm-intrinsics/abs.ll | 2 +-
.../SPIRV/pointers/bitcast-fix-accesschain.ll | 5 ++++-
10 files changed, 35 insertions(+), 20 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
index 19fe0ad2ede3f1..f4daa1af6e4b25 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
@@ -295,7 +295,7 @@ Register SPIRVGlobalRegistry::buildConstantInt(uint64_t Val,
Register Res = DT.find(ConstInt, &MF);
if (!Res.isValid()) {
unsigned BitWidth = getScalarOrVectorBitWidth(SpvType);
- LLT LLTy = LLT::scalar(EmitIR ? BitWidth : 32); // lev
+ LLT LLTy = LLT::scalar(BitWidth);
Res = MF.getRegInfo().createGenericVirtualRegister(LLTy);
MF.getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);
assignTypeToVReg(LLVMIntTy, Res, MIRBuilder,
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.h b/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
index 37a2f4aa99c034..77356b7512a739 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
@@ -44,7 +44,7 @@ class SPIRVTargetLowering : public TargetLowering {
// This is to prevent sexts of non-i64 vector indices which are generated
// within general IRTranslator hence type generation for it is omitted.
MVT getVectorIdxTy(const DataLayout &DL) const override {
- return MVT::getIntegerVT(32); // lev
+ return MVT::getIntegerVT(32);
}
unsigned getNumRegistersForCallingConv(LLVMContext &Context,
CallingConv::ID CC,
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 2298011d0d656a..c3391e3e503353 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -146,9 +146,12 @@ def OpMemberDecorateString: Op<5633, (outs),
def OpExtension: Op<10, (outs), (ins StringImm:$name, variable_ops), "OpExtension $name">;
def OpExtInstImport: Op<11, (outs ID:$res), (ins StringImm:$extInstsName, variable_ops),
"$res = OpExtInstImport $extInstsName">;
-def OpExtInst: Op<12, (outs ID:$res), (ins TYPE:$ty, ID:$set, Extension:$inst, variable_ops),
+// $set should have been a register by the SPIR-V specification,
+// however, OpExtInst and OpExtInstImport get its own special case treatment
+// after instruction selection, so `i32imm` is the correct definition from the
+// perspective of the instruction selection pass
+def OpExtInst: Op<12, (outs ID:$res), (ins TYPE:$ty, i32imm:$set, Extension:$inst, variable_ops),
"$res = OpExtInst $ty $set $inst">;
-
// 3.42.5 Mode-Setting Instructions
def OpMemoryModel: Op<14, (outs), (ins AddressingModel:$addr, MemoryModel:$mem),
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 35e9aca8b9fd9e..4e6674a4b19279 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -1734,8 +1734,7 @@ void SPIRVInstructionSelector::renderImm32(MachineInstrBuilder &MIB,
Register
SPIRVInstructionSelector::buildI32Constant(uint32_t Val, MachineInstr &I,
const SPIRVType *ResType) const {
- Type *LLVMTy =
- IntegerType::get(GR.CurMF->getFunction().getContext(), 32); // lev
+ Type *LLVMTy = IntegerType::get(GR.CurMF->getFunction().getContext(), 32);
const SPIRVType *SpvI32Ty =
ResType ? ResType : GR.getOrCreateSPIRVIntegerType(32, I, TII);
// Find a constant in DT or build a new one.
@@ -1938,7 +1937,7 @@ bool SPIRVInstructionSelector::selectConst(Register ResVReg,
.addDef(ResVReg)
.addUse(GR.getSPIRVTypeID(ResType));
// <=32-bit integers should be caught by the sdag pattern.
- assert(Imm.getBitWidth() > 32); // lev
+ assert(Imm.getBitWidth() > 32);
addNumImm(Imm, MIB);
return MIB.constrainAllUses(TII, TRI, RBI);
}
@@ -2512,8 +2511,7 @@ bool SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
// 93 ThreadId reads the thread ID
MachineIRBuilder MIRBuilder(I);
- const SPIRVType *U32Type =
- GR.getOrCreateSPIRVIntegerType(32, MIRBuilder); // lev
+ const SPIRVType *U32Type = GR.getOrCreateSPIRVIntegerType(32, MIRBuilder);
const SPIRVType *Vec3Ty =
GR.getOrCreateSPIRVVectorType(U32Type, 3, MIRBuilder);
const SPIRVType *PtrType = GR.getOrCreateSPIRVPointerType(
diff --git a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
index e775f8c57b048e..e11b4e3db2060e 100644
--- a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
@@ -142,7 +142,6 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
p2, p3, p4, p5, p6};
auto allPtrs = {p0, p1, p2, p3, p4, p5, p6};
- auto allWritablePtrs = {p0, p1, p3, p4, p5, p6};
for (auto Opc : TypeFoldingSupportingOpcs)
getActionDefinitionsBuilder(Opc).custom();
@@ -173,10 +172,10 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
getActionDefinitionsBuilder(G_UNMERGE_VALUES).alwaysLegal();
getActionDefinitionsBuilder({G_MEMCPY, G_MEMMOVE})
- .legalIf(all(typeInSet(0, allWritablePtrs), typeInSet(1, allPtrs)));
+ .legalIf(all(typeInSet(0, allPtrs), typeInSet(1, allPtrs)));
getActionDefinitionsBuilder(G_MEMSET).legalIf(
- all(typeInSet(0, allWritablePtrs), typeInSet(1, allIntScalars)));
+ all(typeInSet(0, allPtrs), typeInSet(1, allIntScalars)));
getActionDefinitionsBuilder(G_ADDRSPACE_CAST)
.legalForCartesianProduct(allPtrs, allPtrs);
@@ -232,14 +231,14 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
G_ATOMICRMW_MAX, G_ATOMICRMW_MIN,
G_ATOMICRMW_SUB, G_ATOMICRMW_XOR,
G_ATOMICRMW_UMAX, G_ATOMICRMW_UMIN})
- .legalForCartesianProduct(allIntScalars, allWritablePtrs);
+ .legalForCartesianProduct(allIntScalars, allPtrs);
getActionDefinitionsBuilder(
{G_ATOMICRMW_FADD, G_ATOMICRMW_FSUB, G_ATOMICRMW_FMIN, G_ATOMICRMW_FMAX})
- .legalForCartesianProduct(allFloatScalars, allWritablePtrs);
+ .legalForCartesianProduct(allFloatScalars, allPtrs);
getActionDefinitionsBuilder(G_ATOMICRMW_XCHG)
- .legalForCartesianProduct(allFloatAndIntScalarsAndPtrs, allWritablePtrs);
+ .legalForCartesianProduct(allFloatAndIntScalarsAndPtrs, allPtrs);
getActionDefinitionsBuilder(G_ATOMIC_CMPXCHG_WITH_SUCCESS).lower();
// TODO: add proper legalization rules.
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 2decfd2748dfae..761d1823abae40 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -193,14 +193,24 @@ static void insertBitcasts(MachineFunction &MF, SPIRVGlobalRegistry *GR,
// If the ptrcast would be redundant, replace all uses with the source
// register.
+ MachineRegisterInfo *MRI = MIB.getMRI();
if (GR->getSPIRVTypeForVReg(Source) == AssignedPtrType) {
// Erase Def's assign type instruction if we are going to replace Def.
- if (MachineInstr *AssignMI = findAssignTypeInstr(Def, MIB.getMRI()))
+ if (MachineInstr *AssignMI = findAssignTypeInstr(Def, MRI))
ToErase.push_back(AssignMI);
- MIB.getMRI()->replaceRegWith(Def, Source);
+ MRI->replaceRegWith(Def, Source);
} else {
GR->assignSPIRVTypeToVReg(AssignedPtrType, Def, MF);
MIB.buildBitcast(Def, Source);
+ // MachineVerifier requires that bitcast must change the type.
+ // Change AddressSpace if needed to hint that Def and Source points to
+ // different types: this doesn't change actual code generation.
+ LLT DefType = MRI->getType(Def);
+ if (DefType == MRI->getType(Source))
+ MRI->setType(Def,
+ LLT::pointer((DefType.getAddressSpace() + 1) %
+ SPIRVSubtarget::MaxLegalAddressSpace,
+ GR->getPointerSize()));
}
}
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVSubtarget.h b/llvm/lib/Target/SPIRV/SPIRVSubtarget.h
index 211216488db799..82ec3cc95cdd3f 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSubtarget.h
+++ b/llvm/lib/Target/SPIRV/SPIRVSubtarget.h
@@ -128,6 +128,8 @@ class SPIRVSubtarget : public SPIRVGenSubtargetInfo {
static bool classof(const TargetSubtargetInfo *ST) {
return ST->getTargetTriple().isSPIRV();
}
+
+ static constexpr unsigned MaxLegalAddressSpace = 6;
};
} // namespace llvm
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
index 449dd71954500b..e006651d49e4bd 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s --spirv-ext=+SPV_INTEL_inline_assembly -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s --spirv-ext=+SPV_INTEL_inline_assembly -o - | FileCheck %s
; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s --spirv-ext=+SPV_INTEL_inline_assembly -o - -filetype=obj | spirv-val %}
; RUN: not llc -O0 -mtriple=spirv64-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/abs.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/abs.ll
index d627a2fc7838a9..f0f5f78b55550e 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/abs.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/abs.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-linux %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-linux %s -o - | FileCheck %s
; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] s_abs
; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] s_abs
diff --git a/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-accesschain.ll b/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-accesschain.ll
index 7fae6ca2c48cf1..7db1eed84bf7d9 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-accesschain.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-accesschain.ll
@@ -1,6 +1,9 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
; CHECK-DAG: %[[#TYCHAR:]] = OpTypeInt 8 0
; CHECK-DAG: %[[#TYCHARPTR:]] = OpTypePointer Function %[[#TYCHAR]]
; CHECK-DAG: %[[#TYINT32:]] = OpTypeInt 32 0
>From d86857014d7fb05cebad42d665e2cca83a910e4e Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Mon, 19 Aug 2024 09:10:27 -0700
Subject: [PATCH 04/14] improve virtual registers types and classes
---
llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp | 2 +-
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp | 51 +++++++++++++++++++
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h | 3 ++
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 24 ++++-----
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 30 ++++++++---
llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp | 7 +--
llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 26 +---------
.../test/CodeGen/SPIRV/llvm-intrinsics/abs.ll | 4 ++
.../llvm-intrinsics/llvm-vector-reduce/add.ll | 7 +--
.../llvm-intrinsics/llvm-vector-reduce/and.ll | 7 +--
.../llvm-vector-reduce/fadd.ll | 7 +--
11 files changed, 111 insertions(+), 57 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
index 26d84c8efb10ba..3bc5565236131f 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
@@ -403,7 +403,7 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
int i = 0;
for (const auto &Arg : F.args()) {
assert(VRegs[i].size() == 1 && "Formal arg has multiple vregs");
- MRI->setRegClass(VRegs[i][0], &SPIRV::iIDRegClass);
+ MRI->setRegClass(VRegs[i][0], GR->getRegClass(ArgTypeVRegs[i]));
MIRBuilder.buildInstr(SPIRV::OpFunctionParameter)
.addDef(VRegs[i][0])
.addUse(GR->getSPIRVTypeID(ArgTypeVRegs[i]));
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
index f4daa1af6e4b25..be35ced338a843 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
@@ -1438,3 +1438,54 @@ Register SPIRVGlobalRegistry::getOrCreateUndef(MachineInstr &I,
*ST.getRegisterInfo(), *ST.getRegBankInfo());
return Res;
}
+
+const TargetRegisterClass *
+SPIRVGlobalRegistry::getRegClass(SPIRVType *SpvType) const {
+ unsigned Opcode = SpvType->getOpcode();
+ switch (Opcode) {
+ case SPIRV::OpTypeFloat:
+ return &SPIRV::fIDRegClass;
+ case SPIRV::OpTypePointer:
+ return &SPIRV::pIDRegClass;
+ case SPIRV::OpTypeVector: {
+ SPIRVType *ElemType = getSPIRVTypeForVReg(SpvType->getOperand(1).getReg());
+ unsigned ElemOpcode = ElemType ? ElemType->getOpcode() : 0;
+ if (ElemOpcode == SPIRV::OpTypeFloat)
+ return &SPIRV::vfIDRegClass;
+ if (ElemOpcode == SPIRV::OpTypePointer)
+ return &SPIRV::vpIDRegClass;
+ return &SPIRV::vIDRegClass;
+ }
+ }
+ return &SPIRV::iIDRegClass;
+}
+
+LLT SPIRVGlobalRegistry::getRegType(SPIRVType *SpvType) const {
+ unsigned Opcode = SpvType ? SpvType->getOpcode() : 0;
+ switch (Opcode) {
+ case SPIRV::OpTypeInt:
+ case SPIRV::OpTypeFloat:
+ case SPIRV::OpTypeBool:
+ return LLT::scalar(getScalarOrVectorBitWidth(SpvType));
+ case SPIRV::OpTypePointer:
+ return LLT::pointer(0, getPointerSize());
+ case SPIRV::OpTypeVector: {
+ SPIRVType *ElemType = getSPIRVTypeForVReg(SpvType->getOperand(1).getReg());
+ LLT ET;
+ switch (ElemType ? ElemType->getOpcode() : 0) {
+ case SPIRV::OpTypePointer:
+ ET = LLT::pointer(0, getPointerSize());
+ break;
+ case SPIRV::OpTypeInt:
+ case SPIRV::OpTypeFloat:
+ case SPIRV::OpTypeBool:
+ ET = LLT::scalar(getScalarOrVectorBitWidth(ElemType));
+ break;
+ default:
+ ET = LLT::scalar(64);
+ }
+ return LLT::fixed_vector(2, ET);
+ }
+ }
+ return LLT::scalar(64);
+}
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
index 290c7c25831ddb..a5cb86f4f1c638 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
@@ -550,6 +550,9 @@ class SPIRVGlobalRegistry {
SPIRVType *getOrCreateOpTypeByOpcode(const Type *Ty,
MachineIRBuilder &MIRBuilder,
unsigned Opcode);
+
+ const TargetRegisterClass *getRegClass(SPIRVType *SpvType) const;
+ LLT getRegType(SPIRVType *SpvType) const;
};
} // end namespace llvm
#endif // LLLVM_LIB_TARGET_SPIRV_SPIRVTYPEMANAGER_H
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index c3391e3e503353..75e8dc439c589d 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -17,12 +17,12 @@ include "SPIRVSymbolicOperands.td"
let isCodeGenOnly=1 in {
def ASSIGN_TYPE: Pseudo<(outs ID:$dst_id), (ins ID:$src_id, TYPE:$src_ty)>;
def DECL_TYPE: Pseudo<(outs ID:$dst_id), (ins ID:$src_id, TYPE:$src_ty)>;
- def GET_ID: Pseudo<(outs iID:$dst_id), (ins ID:$src)>;
- def GET_fID: Pseudo<(outs fID:$dst_id), (ins ID:$src)>;
- def GET_pID: Pseudo<(outs pID:$dst_id), (ins ID:$src)>;
- def GET_vID: Pseudo<(outs vID:$dst_id), (ins ID:$src)>;
- def GET_vfID: Pseudo<(outs vfID:$dst_id), (ins ID:$src)>;
- def GET_vpID: Pseudo<(outs vpID:$dst_id), (ins ID:$src)>;
+ def GET_ID: Pseudo<(outs iID:$dst_id), (ins iID:$src)>;
+ def GET_fID: Pseudo<(outs fID:$dst_id), (ins fID:$src)>;
+ def GET_pID: Pseudo<(outs pID:$dst_id), (ins pID:$src)>;
+ def GET_vID: Pseudo<(outs vID:$dst_id), (ins vID:$src)>;
+ def GET_vfID: Pseudo<(outs vfID:$dst_id), (ins vfID:$src)>;
+ def GET_vpID: Pseudo<(outs vpID:$dst_id), (ins vpID:$src)>;
}
def SPVTypeBin : SDTypeProfile<1, 2, []>;
@@ -36,14 +36,14 @@ class BinOp<string name, bits<16> opCode, list<dag> pattern=[]>
"$dst = "#name#" $src_ty $src $src2", pattern>;
class BinOpTyped<string name, bits<16> opCode, RegisterClass CID, SDNode node>
- : Op<opCode, (outs iID:$dst), (ins TYPE:$src_ty, CID:$src, CID:$src2),
+ : Op<opCode, (outs CID:$dst), (ins TYPE:$src_ty, CID:$src, CID:$src2),
"$dst = "#name#" $src_ty $src $src2",
- [(set iID:$dst, (assigntype (node CID:$src, CID:$src2), TYPE:$src_ty))]>;
+ [(set CID:$dst, (assigntype (node CID:$src, CID:$src2), TYPE:$src_ty))]>;
class TernOpTyped<string name, bits<16> opCode, RegisterClass CCond, RegisterClass CID, SDNode node>
- : Op<opCode, (outs iID:$dst), (ins TYPE:$src_ty, CCond:$cond, CID:$src1, CID:$src2),
+ : Op<opCode, (outs CID:$dst), (ins TYPE:$src_ty, CCond:$cond, CID:$src1, CID:$src2),
"$dst = "#name#" $src_ty $cond $src1 $src2",
- [(set iID:$dst, (assigntype (node CCond:$cond, CID:$src1, CID:$src2), TYPE:$src_ty))]>;
+ [(set CID:$dst, (assigntype (node CCond:$cond, CID:$src1, CID:$src2), TYPE:$src_ty))]>;
multiclass BinOpTypedGen<string name, bits<16> opCode, SDNode node, bit genF = 0, bit genV = 0> {
if genF then
@@ -91,8 +91,8 @@ class UnOp<string name, bits<16> opCode, list<dag> pattern=[]>
: Op<opCode, (outs ID:$dst), (ins TYPE:$type, ID:$src),
"$dst = "#name#" $type $src", pattern>;
class UnOpTyped<string name, bits<16> opCode, RegisterClass CID, SDNode node>
- : Op<opCode, (outs iID:$dst), (ins TYPE:$src_ty, CID:$src),
- "$dst = "#name#" $src_ty $src", [(set iID:$dst, (assigntype (node CID:$src), TYPE:$src_ty))]>;
+ : Op<opCode, (outs CID:$dst), (ins TYPE:$src_ty, CID:$src),
+ "$dst = "#name#" $src_ty $src", [(set CID:$dst, (assigntype (node CID:$src), TYPE:$src_ty))]>;
class SimpleOp<string name, bits<16> opCode>: Op<opCode, (outs), (ins), name>;
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 4e6674a4b19279..47a1ae828ac53c 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -305,8 +305,16 @@ void SPIRVInstructionSelector::resetVRegsType(MachineFunction &MF) {
HasVRegsReset = &MF;
MachineRegisterInfo &MRI = MF.getRegInfo();
- for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I)
- MRI.setType(Register::index2VirtReg(I), LLT::scalar(64));
+ for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
+ Register Reg = Register::index2VirtReg(I);
+ LLT RegType = MRI.getType(Reg);
+ if (RegType.isScalar())
+ MRI.setType(Reg, LLT::scalar(64));
+ else if (RegType.isPointer())
+ MRI.setType(Reg, LLT::pointer(RegType.getAddressSpace(), 64));
+ else if (RegType.isVector())
+ MRI.setType(Reg, LLT::fixed_vector(2, LLT::scalar(64)));
+ }
for (const auto &MBB : MF) {
for (const auto &MI : MBB) {
if (MI.getOpcode() != SPIRV::ASSIGN_TYPE)
@@ -356,7 +364,7 @@ bool SPIRVInstructionSelector::select(MachineInstr &I) {
if (Res)
return Res;
}
- MRI->setRegClass(DstReg, &SPIRV::iIDRegClass);
+ MRI->setRegClass(SrcReg, MRI->getRegClass(DstReg));
MRI->replaceRegWith(SrcReg, DstReg);
I.removeFromParent();
return true;
@@ -994,7 +1002,7 @@ bool SPIRVInstructionSelector::selectUnmergeValues(MachineInstr &I) const {
if (!ResType) {
// There was no "assign type" actions, let's fix this now
ResType = ScalarType;
- MRI->setRegClass(ResVReg, &SPIRV::iIDRegClass);
+ MRI->setRegClass(ResVReg, GR.getRegClass(ResType));
MRI->setType(ResVReg, LLT::scalar(GR.getScalarOrVectorBitWidth(ResType)));
GR.assignSPIRVTypeToVReg(ResType, ResVReg, *GR.CurMF);
}
@@ -1855,12 +1863,17 @@ bool SPIRVInstructionSelector::selectExt(Register ResVReg,
return selectSelect(ResVReg, ResType, I, IsSigned);
SPIRVType *SrcType = GR.getSPIRVTypeForVReg(SrcReg);
- if (SrcType == ResType)
+ if (SrcType == ResType) {
+ const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(ResVReg);
+ const TargetRegisterClass *SrcRC = MRI->getRegClassOrNull(SrcReg);
+ if (DstRC != SrcRC && SrcRC)
+ MRI->setRegClass(ResVReg, SrcRC);
return BuildMI(*I.getParent(), I, I.getDebugLoc(),
TII.get(TargetOpcode::COPY))
.addDef(ResVReg)
.addUse(SrcReg)
.constrainAllUses(TII, TRI, RBI);
+ }
unsigned Opcode = IsSigned ? SPIRV::OpSConvert : SPIRV::OpUConvert;
return selectUnOp(ResVReg, ResType, I, Opcode);
@@ -1899,12 +1912,17 @@ bool SPIRVInstructionSelector::selectTrunc(Register ResVReg,
const SPIRVType *ArgType = GR.getSPIRVTypeForVReg(IntReg);
if (GR.isScalarOrVectorOfType(ResVReg, SPIRV::OpTypeBool))
return selectIntToBool(IntReg, ResVReg, I, ArgType, ResType);
- if (ArgType == ResType)
+ if (ArgType == ResType) {
+ const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(ResVReg);
+ const TargetRegisterClass *SrcRC = MRI->getRegClassOrNull(IntReg);
+ if (DstRC != SrcRC && SrcRC)
+ MRI->setRegClass(ResVReg, SrcRC);
return BuildMI(*I.getParent(), I, I.getDebugLoc(),
TII.get(TargetOpcode::COPY))
.addDef(ResVReg)
.addUse(IntReg)
.constrainAllUses(TII, TRI, RBI);
+ }
bool IsSigned = GR.isScalarOrVectorSigned(ResType);
unsigned Opcode = IsSigned ? SPIRV::OpSConvert : SPIRV::OpUConvert;
return selectUnOp(ResVReg, ResType, I, Opcode);
diff --git a/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
index 7516d61a67724d..b8668da8c89024 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
@@ -122,9 +122,8 @@ static void processNewInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
if (!ResVType)
continue;
// Set type & class
- MRI.setRegClass(ResVReg, &SPIRV::iIDRegClass);
- MRI.setType(ResVReg,
- LLT::scalar(GR->getScalarOrVectorBitWidth(ResVType)));
+ MRI.setRegClass(ResVReg, GR->getRegClass(ResVType));
+ MRI.setType(ResVReg, GR->getRegType(ResVType));
GR->assignSPIRVTypeToVReg(ResVType, ResVReg, *GR->CurMF);
}
// If this is a simple operation that is to be reduced by TableGen
@@ -136,8 +135,6 @@ static void processNewInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
continue;
// Restore usual instructions pattern for the newly inserted
// instruction
- MRI.setRegClass(ResVReg, &SPIRV::iIDRegClass);
- MRI.setType(ResVReg, LLT::scalar(64));
insertAssignInstr(ResVReg, nullptr, ResVType, GR, MIB, MRI);
processInstr(I, MIB, MRI, GR);
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 761d1823abae40..7ce459ccddcb2c 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -326,28 +326,6 @@ inline bool getIsFloat(SPIRVType *SpvType, const SPIRVGlobalRegistry &GR) {
->getOpcode() == SPIRV::OpTypeFloat;
}
-static const TargetRegisterClass *getRegClass(SPIRVType *SpvType,
- const SPIRVGlobalRegistry &GR) {
- unsigned Opcode = SpvType->getOpcode();
- switch (Opcode) {
- case SPIRV::OpTypeFloat:
- return &SPIRV::fIDRegClass;
- case SPIRV::OpTypePointer:
- return &SPIRV::pIDRegClass;
- case SPIRV::OpTypeVector: {
- SPIRVType *ElemType =
- GR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg());
- unsigned ElemOpcode = ElemType ? ElemType->getOpcode() : 0;
- if (ElemOpcode == SPIRV::OpTypeFloat)
- return &SPIRV::vfIDRegClass;
- if (ElemOpcode == SPIRV::OpTypePointer)
- return &SPIRV::vpIDRegClass;
- return &SPIRV::vIDRegClass;
- }
- }
- return &SPIRV::iIDRegClass;
-}
-
static std::pair<Register, unsigned>
createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
const SPIRVGlobalRegistry &GR) {
@@ -373,7 +351,7 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
NewT = LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
}
Register IdReg = MRI.createGenericVirtualRegister(NewT);
- MRI.setRegClass(IdReg, getRegClass(SpvType, GR));
+ MRI.setRegClass(IdReg, GR.getRegClass(SpvType));
return {IdReg, GetIdOp};
}
@@ -396,7 +374,7 @@ Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpvType,
if (auto *RC = MRI.getRegClassOrNull(Reg)) {
MRI.setRegClass(NewReg, RC);
} else {
- auto RegClass = getRegClass(SpvType, *GR);
+ auto RegClass = GR->getRegClass(SpvType);
MRI.setRegClass(NewReg, RegClass);
MRI.setRegClass(Reg, RegClass);
}
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/abs.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/abs.ll
index f0f5f78b55550e..f74c6ef99b4559 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/abs.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/abs.ll
@@ -1,4 +1,8 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-linux %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-linux %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] s_abs
; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] s_abs
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/add.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/add.ll
index e0c84ee3a3f1c1..ef9719e64586d9 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/add.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/add.ll
@@ -1,7 +1,8 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
-; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-target triple = "spir64-unknown-unknown"
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[Char:.*]] = OpTypeInt 8 0
; CHECK-DAG: %[[CharVec2:.*]] = OpTypeVector %[[Char]] 2
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/and.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/and.ll
index 12a4a86fa4a8be..e9d9adba8f3651 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/and.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/and.ll
@@ -1,7 +1,8 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
-; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-target triple = "spir64-unknown-unknown"
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[Char:.*]] = OpTypeInt 8 0
; CHECK-DAG: %[[CharVec2:.*]] = OpTypeVector %[[Char]] 2
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fadd.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fadd.ll
index 459bc6bdcdaff8..38ec4db34c9bcf 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fadd.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fadd.ll
@@ -1,7 +1,8 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
-; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-target triple = "spir64-unknown-unknown"
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[Half:.*]] = OpTypeFloat 16
; CHECK-DAG: %[[HalfVec2:.*]] = OpTypeVector %[[Half]] 2
>From a2597ca426840bb5a7de24504e86af5155b2903a Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Mon, 19 Aug 2024 09:55:19 -0700
Subject: [PATCH 05/14] fix builtin vreg type & class
---
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 6 +++---
llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 03f0390c2a1aca..5d1b4657ad8137 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -799,14 +799,14 @@ static bool buildAtomicRMWInst(const SPIRV::IncomingCall *Call, unsigned Opcode,
Register PtrRegister = Call->Arguments[0];
unsigned Semantics = SPIRV::MemorySemantics::None;
- MRI->setRegClass(PtrRegister, &SPIRV::iIDRegClass);
+ MRI->setRegClass(PtrRegister, &SPIRV::pIDRegClass);
Register MemSemanticsReg =
Call->Arguments.size() >= 3 ? Call->Arguments[2] : Register();
MemSemanticsReg = buildMemSemanticsReg(MemSemanticsReg, PtrRegister,
Semantics, MIRBuilder, GR);
- MRI->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
Register ValueReg = Call->Arguments[1];
Register ValueTypeReg = GR->getSPIRVTypeID(Call->ReturnType);
+ MRI->setRegClass(ValueReg, GR->getRegClass(Call->ReturnType));
// support cl_ext_float_atomics
if (Call->ReturnType->getOpcode() == SPIRV::OpTypeFloat) {
if (Opcode == SPIRV::OpAtomicIAdd) {
@@ -817,7 +817,7 @@ static bool buildAtomicRMWInst(const SPIRV::IncomingCall *Call, unsigned Opcode,
Opcode = SPIRV::OpAtomicFAddEXT;
Register NegValueReg =
MRI->createGenericVirtualRegister(MRI->getType(ValueReg));
- MRI->setRegClass(NegValueReg, &SPIRV::iIDRegClass);
+ MRI->setRegClass(NegValueReg, GR->getRegClass(Call->ReturnType));
GR->assignSPIRVTypeToVReg(Call->ReturnType, NegValueReg,
MIRBuilder.getMF());
MIRBuilder.buildInstr(TargetOpcode::G_FNEG)
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 7ce459ccddcb2c..2bd3eb258f3ee1 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -297,7 +297,7 @@ static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR,
if (SpvType)
GR->assignSPIRVTypeToVReg(SpvType, Reg, MIB.getMF());
if (!MRI.getRegClassOrNull(Reg))
- MRI.setRegClass(Reg, &SPIRV::iIDRegClass);
+ MRI.setRegClass(Reg, SpvType ? GR->getRegClass(SpvType) : &SPIRV::iIDRegClass);
}
}
return SpvType;
>From a962e08fd982d834263c77fd7871ce297505c8ce Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Mon, 19 Aug 2024 15:34:45 -0700
Subject: [PATCH 06/14] improve tablegen, builtins, virtual registers types and
classes
---
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 39 ++++++++++++-------
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 24 ++++++------
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 12 +++++-
llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 3 +-
.../CodeGen/SPIRV/hlsl-intrinsics/log10.ll | 2 +-
.../SPIRV/transcoding/sub_group_ballot.ll | 2 +-
6 files changed, 52 insertions(+), 30 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 5d1b4657ad8137..3de2f6659578f0 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -408,7 +408,7 @@ buildBoolRegister(MachineIRBuilder &MIRBuilder, const SPIRVType *ResultType,
Register ResultRegister =
MIRBuilder.getMRI()->createGenericVirtualRegister(Type);
- MIRBuilder.getMRI()->setRegClass(ResultRegister, &SPIRV::iIDRegClass);
+ MIRBuilder.getMRI()->setRegClass(ResultRegister, GR->getRegClass(ResultType));
GR->assignSPIRVTypeToVReg(BoolType, ResultRegister, MIRBuilder.getMF());
return std::make_tuple(ResultRegister, BoolType);
}
@@ -430,6 +430,8 @@ static bool buildSelectInst(MachineIRBuilder &MIRBuilder,
TrueConst = GR->buildConstantInt(1, MIRBuilder, ReturnType);
FalseConst = GR->buildConstantInt(0, MIRBuilder, ReturnType);
}
+
+ MIRBuilder.getMRI()->setRegClass(ReturnRegister, GR->getRegClass(ReturnType));
return MIRBuilder.buildSelect(ReturnRegister, SourceRegister, TrueConst,
FalseConst);
}
@@ -939,9 +941,11 @@ static bool buildBarrierInst(const SPIRV::IncomingCall *Call, unsigned Opcode,
Register MemSemanticsReg;
if (MemFlags == MemSemantics) {
MemSemanticsReg = Call->Arguments[0];
- MRI->setRegClass(MemSemanticsReg, &SPIRV::iIDRegClass);
- } else
+ if (!MRI->getRegClassOrNull(MemSemanticsReg))
+ MRI->setRegClass(MemSemanticsReg, &SPIRV::iIDRegClass);
+ } else {
MemSemanticsReg = buildConstantIntReg32(MemSemantics, MIRBuilder, GR);
+ }
Register ScopeReg;
SPIRV::Scope::Scope Scope = SPIRV::Scope::Workgroup;
@@ -962,7 +966,8 @@ static bool buildBarrierInst(const SPIRV::IncomingCall *Call, unsigned Opcode,
if (CLScope == static_cast<unsigned>(Scope)) {
ScopeReg = Call->Arguments[1];
- MRI->setRegClass(ScopeReg, &SPIRV::iIDRegClass);
+ if (!MRI->getRegClassOrNull(ScopeReg))
+ MRI->setRegClass(ScopeReg, &SPIRV::iIDRegClass);
}
}
@@ -1104,7 +1109,7 @@ static bool generateGroupInst(const SPIRV::IncomingCall *Call,
} else {
if (BoolRegType->getOpcode() == SPIRV::OpTypeInt) {
Arg0 = MRI->createGenericVirtualRegister(LLT::scalar(1));
- MRI->setRegClass(Arg0, &SPIRV::IDRegClass);
+ MRI->setRegClass(Arg0, &SPIRV::iIDRegClass);
GR->assignSPIRVTypeToVReg(BoolType, Arg0, MIRBuilder.getMF());
MIRBuilder.buildICmp(CmpInst::ICMP_NE, Arg0, BoolReg,
GR->buildConstantInt(0, MIRBuilder, BoolRegType));
@@ -1253,8 +1258,10 @@ static bool generateIntelSubgroupsInst(const SPIRV::IncomingCall *Call,
.addDef(Call->ReturnRegister)
.addUse(GR->getSPIRVTypeID(Call->ReturnType));
for (size_t i = 0; i < Call->Arguments.size(); ++i) {
- MIB.addUse(Call->Arguments[i]);
- MRI->setRegClass(Call->Arguments[i], &SPIRV::iIDRegClass);
+ Register ArgReg = Call->Arguments[i];
+ MIB.addUse(ArgReg);
+ if (!MRI->getRegClassOrNull(ArgReg))
+ MRI->setRegClass(ArgReg, &SPIRV::iIDRegClass);
}
return true;
@@ -1278,11 +1285,13 @@ static bool generateGroupUniformInst(const SPIRV::IncomingCall *Call,
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
Register GroupResultReg = Call->ReturnRegister;
- MRI->setRegClass(GroupResultReg, &SPIRV::iIDRegClass);
+ if (!MRI->getRegClassOrNull(GroupResultReg))
+ MRI->setRegClass(GroupResultReg, GR->getRegClass(Call->ReturnType));
// Scope
Register ScopeReg = Call->Arguments[0];
- MRI->setRegClass(ScopeReg, &SPIRV::iIDRegClass);
+ if (!MRI->getRegClassOrNull(ScopeReg))
+ MRI->setRegClass(ScopeReg, &SPIRV::iIDRegClass);
// Group Operation
Register ConstGroupOpReg = Call->Arguments[1];
@@ -1299,7 +1308,8 @@ static bool generateGroupUniformInst(const SPIRV::IncomingCall *Call,
// Value
Register ValueReg = Call->Arguments[2];
- MRI->setRegClass(ValueReg, &SPIRV::iIDRegClass);
+ if (!MRI->getRegClassOrNull(ValueReg))
+ MRI->setRegClass(ValueReg, GR->getRegClass(Call->ReturnType));
auto MIB = MIRBuilder.buildInstr(GroupUniform->Opcode)
.addDef(GroupResultReg)
@@ -1326,7 +1336,8 @@ static bool generateKernelClockInst(const SPIRV::IncomingCall *Call,
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
Register ResultReg = Call->ReturnRegister;
- MRI->setRegClass(ResultReg, &SPIRV::iIDRegClass);
+ if (!MRI->getRegClassOrNull(ResultReg))
+ MRI->setRegClass(ResultReg, &SPIRV::iIDRegClass);
// Deduce the `Scope` operand from the builtin function name.
SPIRV::Scope::Scope ScopeArg =
@@ -1634,7 +1645,7 @@ static bool generateImageSizeQueryInst(const SPIRV::IncomingCall *Call,
if (NumExpectedRetComponents != NumActualRetComponents) {
QueryResult = MIRBuilder.getMRI()->createGenericVirtualRegister(
LLT::fixed_vector(NumActualRetComponents, 32));
- MIRBuilder.getMRI()->setRegClass(QueryResult, &SPIRV::iIDRegClass);
+ MIRBuilder.getMRI()->setRegClass(QueryResult, &SPIRV::vIDRegClass);
SPIRVType *IntTy = GR->getOrCreateSPIRVIntegerType(32, MIRBuilder);
QueryResultType = GR->getOrCreateSPIRVVectorType(
IntTy, NumActualRetComponents, MIRBuilder);
@@ -2540,9 +2551,9 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
Register ReturnRegister = OrigRet;
SPIRVType *ReturnType = nullptr;
if (OrigRetTy && !OrigRetTy->isVoidTy()) {
- ReturnType = GR->assignTypeToVReg(OrigRetTy, OrigRet, MIRBuilder);
+ ReturnType = GR->assignTypeToVReg(OrigRetTy, ReturnRegister, MIRBuilder);
if (!MIRBuilder.getMRI()->getRegClassOrNull(ReturnRegister))
- MIRBuilder.getMRI()->setRegClass(ReturnRegister, &SPIRV::iIDRegClass);
+ MIRBuilder.getMRI()->setRegClass(ReturnRegister, GR->getRegClass(ReturnType));
} else if (OrigRetTy && OrigRetTy->isVoidTy()) {
ReturnRegister = MIRBuilder.getMRI()->createVirtualRegister(&IDRegClass);
MIRBuilder.getMRI()->setType(ReturnRegister, LLT::scalar(64));
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 75e8dc439c589d..79b9bb87739fec 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -59,30 +59,30 @@ multiclass BinOpTypedGen<string name, bits<16> opCode, SDNode node, bit genF = 0
}
multiclass TernOpTypedGen<string name, bits<16> opCode, SDNode node, bit genP = 1, bit genI = 1, bit genF = 0, bit genV = 0> {
- if genF then {
- def SFSCond: TernOpTyped<name, opCode, iID, fID, node>;
- def SFVCond: TernOpTyped<name, opCode, vID, fID, node>;
+ if genP then {
+ def SPSCond: TernOpTyped<name, opCode, iID, pID, node>;
+ def SPVCond: TernOpTyped<name, opCode, vID, pID, node>;
}
if genI then {
def SISCond: TernOpTyped<name, opCode, iID, iID, node>;
def SIVCond: TernOpTyped<name, opCode, vID, iID, node>;
}
- if genP then {
- def SPSCond: TernOpTyped<name, opCode, iID, pID, node>;
- def SPVCond: TernOpTyped<name, opCode, vID, pID, node>;
+ if genF then {
+ def SFSCond: TernOpTyped<name, opCode, iID, fID, node>;
+ def SFVCond: TernOpTyped<name, opCode, vID, fID, node>;
}
if genV then {
- if genF then {
- def VFSCond: TernOpTyped<name, opCode, iID, vfID, node>;
- def VFVCond: TernOpTyped<name, opCode, vID, vfID, node>;
+ if genP then {
+ def VPSCond: TernOpTyped<name, opCode, iID, vpID, node>;
+ def VPVCond: TernOpTyped<name, opCode, vID, vpID, node>;
}
if genI then {
def VISCond: TernOpTyped<name, opCode, iID, vID, node>;
def VIVCond: TernOpTyped<name, opCode, vID, vID, node>;
}
- if genP then {
- def VPSCond: TernOpTyped<name, opCode, iID, vpID, node>;
- def VPVCond: TernOpTyped<name, opCode, vID, vpID, node>;
+ if genF then {
+ def VFSCond: TernOpTyped<name, opCode, iID, vfID, node>;
+ def VFVCond: TernOpTyped<name, opCode, vID, vfID, node>;
}
}
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 47a1ae828ac53c..b35ac7ba74373c 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -371,6 +371,16 @@ bool SPIRVInstructionSelector::select(MachineInstr &I) {
} else if (I.getNumDefs() == 1) {
// Make all vregs 64 bits (for SPIR-V IDs).
MRI->setType(I.getOperand(0).getReg(), LLT::scalar(64));
+/*
+ Register Reg = I.getOperand(0).getReg();
+ LLT RegType = MRI->getType(Reg);
+ if (RegType.isScalar())
+ MRI->setType(Reg, LLT::scalar(64));
+ else if (RegType.isPointer())
+ MRI->setType(Reg, LLT::pointer(RegType.getAddressSpace(), 64));
+ else if (RegType.isVector())
+ MRI->setType(Reg, LLT::fixed_vector(2, LLT::scalar(64)));
+*/
}
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
}
@@ -2486,7 +2496,7 @@ bool SPIRVInstructionSelector::selectLog10(Register ResVReg,
MachineBasicBlock &BB = *I.getParent();
// Build log2(x).
- Register VarReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
+ Register VarReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
bool Result =
BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
.addDef(VarReg)
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 2bd3eb258f3ee1..53b50d2b46a092 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -297,7 +297,8 @@ static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR,
if (SpvType)
GR->assignSPIRVTypeToVReg(SpvType, Reg, MIB.getMF());
if (!MRI.getRegClassOrNull(Reg))
- MRI.setRegClass(Reg, SpvType ? GR->getRegClass(SpvType) : &SPIRV::iIDRegClass);
+ MRI.setRegClass(Reg, SpvType ? GR->getRegClass(SpvType)
+ : &SPIRV::iIDRegClass);
}
}
return SpvType;
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log10.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log10.ll
index 52ca6812d5d63a..32d63a0c0f1d21 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log10.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log10.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: %[[#extinst:]] = OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_ballot.ll b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_ballot.ll
index c579859a3f5314..a815f5d44969c9 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_ballot.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_ballot.ll
@@ -155,7 +155,7 @@
;; dst[4] = get_sub_group_lt_mask();
;; }
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; CHECK-SPIRV-DAG: OpCapability GroupNonUniformBallot
>From 9e85ffd1429aba577fe46daaba7afe886524408c Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Tue, 20 Aug 2024 03:24:58 -0700
Subject: [PATCH 07/14] uniform creation of vregs; address call lowering &
builtins
---
llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp | 16 ++++++---
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp | 13 +++++--
llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 35 ++++++++++++++++---
3 files changed, 52 insertions(+), 12 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
index 3bc5565236131f..601089d5dc48c8 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
@@ -404,6 +404,7 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
for (const auto &Arg : F.args()) {
assert(VRegs[i].size() == 1 && "Formal arg has multiple vregs");
MRI->setRegClass(VRegs[i][0], GR->getRegClass(ArgTypeVRegs[i]));
+ MRI->setType(VRegs[i][0], GR->getRegType(ArgTypeVRegs[i]));
MIRBuilder.buildInstr(SPIRV::OpFunctionParameter)
.addDef(VRegs[i][0])
.addUse(GR->getSPIRVTypeID(ArgTypeVRegs[i]));
@@ -532,10 +533,17 @@ bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
SmallVector<Register, 8> ArgVRegs;
for (auto Arg : Info.OrigArgs) {
assert(Arg.Regs.size() == 1 && "Call arg has multiple VRegs");
- ArgVRegs.push_back(Arg.Regs[0]);
- SPIRVType *SPIRVTy = GR->getOrCreateSPIRVType(Arg.Ty, MIRBuilder);
- if (!GR->getSPIRVTypeForVReg(Arg.Regs[0]))
- GR->assignSPIRVTypeToVReg(SPIRVTy, Arg.Regs[0], MF);
+ Register ArgReg = Arg.Regs[0];
+ ArgVRegs.push_back(ArgReg);
+ SPIRVType *SpvType = GR->getSPIRVTypeForVReg(ArgReg);
+ if (!SpvType) {
+ SpvType = GR->getOrCreateSPIRVType(Arg.Ty, MIRBuilder);
+ GR->assignSPIRVTypeToVReg(SpvType, ArgReg, MF);
+ }
+ if (!MRI->getRegClassOrNull(ArgReg)) {
+ MRI->setRegClass(ArgReg, GR->getRegClass(SpvType));
+ MRI->setType(ArgReg, GR->getRegType(SpvType));
+ }
}
auto instructionSet = canUseOpenCL ? SPIRV::InstructionSet::OpenCL_std
: SPIRV::InstructionSet::GLSL_std_450;
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
index be35ced338a843..54bcb96772e7ab 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
@@ -1460,6 +1460,12 @@ SPIRVGlobalRegistry::getRegClass(SPIRVType *SpvType) const {
return &SPIRV::iIDRegClass;
}
+inline unsigned getAS(SPIRVType *SpvType) {
+ return storageClassToAddressSpace(
+ static_cast<SPIRV::StorageClass::StorageClass>(
+ SpvType->getOperand(1).getImm()));
+}
+
LLT SPIRVGlobalRegistry::getRegType(SPIRVType *SpvType) const {
unsigned Opcode = SpvType ? SpvType->getOpcode() : 0;
switch (Opcode) {
@@ -1468,13 +1474,13 @@ LLT SPIRVGlobalRegistry::getRegType(SPIRVType *SpvType) const {
case SPIRV::OpTypeBool:
return LLT::scalar(getScalarOrVectorBitWidth(SpvType));
case SPIRV::OpTypePointer:
- return LLT::pointer(0, getPointerSize());
+ return LLT::pointer(getAS(SpvType), getPointerSize());
case SPIRV::OpTypeVector: {
SPIRVType *ElemType = getSPIRVTypeForVReg(SpvType->getOperand(1).getReg());
LLT ET;
switch (ElemType ? ElemType->getOpcode() : 0) {
case SPIRV::OpTypePointer:
- ET = LLT::pointer(0, getPointerSize());
+ ET = LLT::pointer(getAS(ElemType), getPointerSize());
break;
case SPIRV::OpTypeInt:
case SPIRV::OpTypeFloat:
@@ -1484,7 +1490,8 @@ LLT SPIRVGlobalRegistry::getRegType(SPIRVType *SpvType) const {
default:
ET = LLT::scalar(64);
}
- return LLT::fixed_vector(2, ET);
+ return LLT::fixed_vector(
+ static_cast<unsigned>(SpvType->getOperand(2).getImm()), ET);
}
}
return LLT::scalar(64);
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 53b50d2b46a092..131dc0b81a1cd7 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -327,6 +327,7 @@ inline bool getIsFloat(SPIRVType *SpvType, const SPIRVGlobalRegistry &GR) {
->getOpcode() == SPIRV::OpTypeFloat;
}
+/*
static std::pair<Register, unsigned>
createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
const SPIRVGlobalRegistry &GR) {
@@ -337,16 +338,18 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
LLT SrcLLT = MRI.getType(SrcReg);
bool IsFloat = getIsFloat(SpvType, GR);
auto GetIdOp = IsFloat ? SPIRV::GET_fID : SPIRV::GET_ID;
+ bool IsVec = SrcLLT.isVector();
+ unsigned NumElements =
+ IsVec ? std::max(2U, GR.getScalarOrVectorComponentCount(SpvType)) : 1;
if (SrcLLT.isPointer()) {
unsigned PtrSz = GR.getPointerSize();
NewT = LLT::pointer(0, PtrSz);
- bool IsVec = SrcLLT.isVector();
if (IsVec)
- NewT = LLT::fixed_vector(2, NewT);
+ NewT = LLT::fixed_vector(NumElements, NewT);
GetIdOp = IsVec ? SPIRV::GET_vpID : SPIRV::GET_pID;
- } else if (SrcLLT.isVector()) {
- NewT = LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
- NewT = LLT::fixed_vector(2, NewT);
+ } else if (IsVec) {
+ NewT = LLT::fixed_vector(
+ NumElements, LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType)));
GetIdOp = IsFloat ? SPIRV::GET_vfID : SPIRV::GET_vID;
} else {
NewT = LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
@@ -355,6 +358,28 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
MRI.setRegClass(IdReg, GR.getRegClass(SpvType));
return {IdReg, GetIdOp};
}
+*/
+static std::pair<Register, unsigned>
+createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
+ const SPIRVGlobalRegistry &GR) {
+ if (!SpvType)
+ SpvType = GR.getSPIRVTypeForVReg(SrcReg);
+ const TargetRegisterClass *RC = GR.getRegClass(SpvType);
+ Register Reg = MRI.createGenericVirtualRegister(GR.getRegType(SpvType));
+ MRI.setRegClass(Reg, RC);
+ unsigned GetIdOp = SPIRV::GET_ID;
+ if (RC == &SPIRV::fIDRegClass)
+ GetIdOp = SPIRV::GET_fID;
+ else if (RC == &SPIRV::pIDRegClass)
+ GetIdOp = SPIRV::GET_pID;
+ else if (RC == &SPIRV::vfIDRegClass)
+ GetIdOp = SPIRV::GET_vfID;
+ else if (RC == &SPIRV::vpIDRegClass)
+ GetIdOp = SPIRV::GET_vpID;
+ else if (RC == &SPIRV::vIDRegClass)
+ GetIdOp = SPIRV::GET_vID;
+ return {Reg, GetIdOp};
+}
// Insert ASSIGN_TYPE instuction between Reg and its definition, set NewReg as
// a dst of the definition, assign SPIRVType to both registers. If SpvType is
>From dd41fdf88e378bd43d1eb9a0607532e716555b9a Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Tue, 20 Aug 2024 03:36:43 -0700
Subject: [PATCH 08/14] builtins & call lowering
---
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 2 +-
llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp | 9 +++++----
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 3de2f6659578f0..340effb747b871 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -762,7 +762,7 @@ static bool buildAtomicCompareExchangeInst(
Register Tmp = !IsCmpxchg ? MRI->createGenericVirtualRegister(DesiredLLT)
: Call->ReturnRegister;
if (!MRI->getRegClassOrNull(Tmp))
- MRI->setRegClass(Tmp, &SPIRV::iIDRegClass);
+ MRI->setRegClass(Tmp, GR->getRegClass(SpvDesiredTy));
GR->assignSPIRVTypeToVReg(SpvDesiredTy, Tmp, MIRBuilder.getMF());
SPIRVType *IntTy = GR->getOrCreateSPIRVIntegerType(32, MIRBuilder);
diff --git a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
index 601089d5dc48c8..27a9cb0ba9b8c0 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
@@ -403,13 +403,14 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
int i = 0;
for (const auto &Arg : F.args()) {
assert(VRegs[i].size() == 1 && "Formal arg has multiple vregs");
- MRI->setRegClass(VRegs[i][0], GR->getRegClass(ArgTypeVRegs[i]));
- MRI->setType(VRegs[i][0], GR->getRegType(ArgTypeVRegs[i]));
+ Register ArgReg = VRegs[i][0];
+ MRI->setRegClass(ArgReg, GR->getRegClass(ArgTypeVRegs[i]));
+ MRI->setType(ArgReg, GR->getRegType(ArgTypeVRegs[i]));
MIRBuilder.buildInstr(SPIRV::OpFunctionParameter)
- .addDef(VRegs[i][0])
+ .addDef(ArgReg)
.addUse(GR->getSPIRVTypeID(ArgTypeVRegs[i]));
if (F.isDeclaration())
- GR->add(&Arg, &MIRBuilder.getMF(), VRegs[i][0]);
+ GR->add(&Arg, &MIRBuilder.getMF(), ArgReg);
i++;
}
// Name the function.
>From 56cd0a61855b3993fc9c7017b1bde1479f110a33 Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Tue, 20 Aug 2024 04:16:09 -0700
Subject: [PATCH 09/14] correct virtual registers creation for builtins
---
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 188 +++++---------------
llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp | 6 +
2 files changed, 49 insertions(+), 145 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 340effb747b871..88a005b0013730 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -431,7 +431,6 @@ static bool buildSelectInst(MachineIRBuilder &MIRBuilder,
FalseConst = GR->buildConstantInt(0, MIRBuilder, ReturnType);
}
- MIRBuilder.getMRI()->setRegClass(ReturnRegister, GR->getRegClass(ReturnType));
return MIRBuilder.buildSelect(ReturnRegister, SourceRegister, TrueConst,
FalseConst);
}
@@ -577,17 +576,12 @@ static bool buildOpFromWrapper(MachineIRBuilder &MIRBuilder, unsigned Opcode,
const SPIRV::IncomingCall *Call,
Register TypeReg,
ArrayRef<uint32_t> ImmArgs = {}) {
- MachineRegisterInfo *MRI = MIRBuilder.getMRI();
auto MIB = MIRBuilder.buildInstr(Opcode);
if (TypeReg.isValid())
MIB.addDef(Call->ReturnRegister).addUse(TypeReg);
unsigned Sz = Call->Arguments.size() - ImmArgs.size();
- for (unsigned i = 0; i < Sz; ++i) {
- Register ArgReg = Call->Arguments[i];
- if (!MRI->getRegClassOrNull(ArgReg))
- MRI->setRegClass(ArgReg, &SPIRV::iIDRegClass);
- MIB.addUse(ArgReg);
- }
+ for (unsigned i = 0; i < Sz; ++i)
+ MIB.addUse(Call->Arguments[i]);
for (uint32_t ImmArg : ImmArgs)
MIB.addImm(ImmArg);
return true;
@@ -601,8 +595,6 @@ static bool buildAtomicInitInst(const SPIRV::IncomingCall *Call,
assert(Call->Arguments.size() == 2 &&
"Need 2 arguments for atomic init translation");
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
MIRBuilder.buildInstr(SPIRV::OpStore)
.addUse(Call->Arguments[0])
.addUse(Call->Arguments[1]);
@@ -618,22 +610,17 @@ static bool buildAtomicLoadInst(const SPIRV::IncomingCall *Call,
return buildOpFromWrapper(MIRBuilder, SPIRV::OpAtomicLoad, Call, TypeReg);
Register PtrRegister = Call->Arguments[0];
- MIRBuilder.getMRI()->setRegClass(PtrRegister, &SPIRV::iIDRegClass);
// TODO: if true insert call to __translate_ocl_memory_sccope before
// OpAtomicLoad and the function implementation. We can use Translator's
// output for transcoding/atomic_explicit_arguments.cl as an example.
- Register ScopeRegister;
- if (Call->Arguments.size() > 1) {
- ScopeRegister = Call->Arguments[1];
- MIRBuilder.getMRI()->setRegClass(ScopeRegister, &SPIRV::iIDRegClass);
- } else
- ScopeRegister = buildConstantIntReg32(SPIRV::Scope::Device, MIRBuilder, GR);
-
+ Register ScopeRegister =
+ Call->Arguments.size() > 1
+ ? Call->Arguments[1]
+ : buildConstantIntReg32(SPIRV::Scope::Device, MIRBuilder, GR);
Register MemSemanticsReg;
if (Call->Arguments.size() > 2) {
// TODO: Insert call to __translate_ocl_memory_order before OpAtomicLoad.
MemSemanticsReg = Call->Arguments[2];
- MIRBuilder.getMRI()->setRegClass(MemSemanticsReg, &SPIRV::iIDRegClass);
} else {
int Semantics =
SPIRV::MemorySemantics::SequentiallyConsistent |
@@ -660,12 +647,10 @@ static bool buildAtomicStoreInst(const SPIRV::IncomingCall *Call,
Register ScopeRegister =
buildConstantIntReg32(SPIRV::Scope::Device, MIRBuilder, GR);
Register PtrRegister = Call->Arguments[0];
- MIRBuilder.getMRI()->setRegClass(PtrRegister, &SPIRV::iIDRegClass);
int Semantics =
SPIRV::MemorySemantics::SequentiallyConsistent |
getMemSemanticsForStorageClass(GR->getPointerStorageClass(PtrRegister));
Register MemSemanticsReg = buildConstantIntReg32(Semantics, MIRBuilder, GR);
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
MIRBuilder.buildInstr(SPIRV::OpAtomicStore)
.addUse(PtrRegister)
.addUse(ScopeRegister)
@@ -688,9 +673,6 @@ static bool buildAtomicCompareExchangeInst(
Register ObjectPtr = Call->Arguments[0]; // Pointer (volatile A *object.)
Register ExpectedArg = Call->Arguments[1]; // Comparator (C* expected).
Register Desired = Call->Arguments[2]; // Value (C Desired).
- MRI->setRegClass(ObjectPtr, &SPIRV::iIDRegClass);
- MRI->setRegClass(ExpectedArg, &SPIRV::iIDRegClass);
- MRI->setRegClass(Desired, &SPIRV::iIDRegClass);
SPIRVType *SpvDesiredTy = GR->getSPIRVTypeForVReg(Desired);
LLT DesiredLLT = MRI->getType(Desired);
@@ -731,8 +713,6 @@ static bool buildAtomicCompareExchangeInst(
MemSemEqualReg = Call->Arguments[3];
if (MemOrdNeq == MemSemEqual)
MemSemUnequalReg = Call->Arguments[4];
- MRI->setRegClass(Call->Arguments[3], &SPIRV::iIDRegClass);
- MRI->setRegClass(Call->Arguments[4], &SPIRV::iIDRegClass);
}
if (!MemSemEqualReg.isValid())
MemSemEqualReg = buildConstantIntReg32(MemSemEqual, MIRBuilder, GR);
@@ -749,7 +729,6 @@ static bool buildAtomicCompareExchangeInst(
Scope = getSPIRVScope(ClScope);
if (ClScope == static_cast<unsigned>(Scope))
ScopeReg = Call->Arguments[5];
- MRI->setRegClass(Call->Arguments[5], &SPIRV::iIDRegClass);
}
if (!ScopeReg.isValid())
ScopeReg = buildConstantIntReg32(Scope, MIRBuilder, GR);
@@ -801,14 +780,12 @@ static bool buildAtomicRMWInst(const SPIRV::IncomingCall *Call, unsigned Opcode,
Register PtrRegister = Call->Arguments[0];
unsigned Semantics = SPIRV::MemorySemantics::None;
- MRI->setRegClass(PtrRegister, &SPIRV::pIDRegClass);
Register MemSemanticsReg =
Call->Arguments.size() >= 3 ? Call->Arguments[2] : Register();
MemSemanticsReg = buildMemSemanticsReg(MemSemanticsReg, PtrRegister,
Semantics, MIRBuilder, GR);
Register ValueReg = Call->Arguments[1];
Register ValueTypeReg = GR->getSPIRVTypeID(Call->ReturnType);
- MRI->setRegClass(ValueReg, GR->getRegClass(Call->ReturnType));
// support cl_ext_float_atomics
if (Call->ReturnType->getOpcode() == SPIRV::OpTypeFloat) {
if (Opcode == SPIRV::OpAtomicIAdd) {
@@ -847,21 +824,10 @@ static bool buildAtomicFloatingRMWInst(const SPIRV::IncomingCall *Call,
SPIRVGlobalRegistry *GR) {
assert(Call->Arguments.size() == 4 &&
"Wrong number of atomic floating-type builtin");
-
- MachineRegisterInfo *MRI = MIRBuilder.getMRI();
-
Register PtrReg = Call->Arguments[0];
- MRI->setRegClass(PtrReg, &SPIRV::iIDRegClass);
-
Register ScopeReg = Call->Arguments[1];
- MRI->setRegClass(ScopeReg, &SPIRV::iIDRegClass);
-
Register MemSemanticsReg = Call->Arguments[2];
- MRI->setRegClass(MemSemanticsReg, &SPIRV::iIDRegClass);
-
Register ValueReg = Call->Arguments[3];
- MRI->setRegClass(ValueReg, &SPIRV::iIDRegClass);
-
MIRBuilder.buildInstr(Opcode)
.addDef(Call->ReturnRegister)
.addUse(GR->getSPIRVTypeID(Call->ReturnType))
@@ -938,15 +904,10 @@ static bool buildBarrierInst(const SPIRV::IncomingCall *Call, unsigned Opcode,
MemSemantics |= SPIRV::MemorySemantics::SequentiallyConsistent;
}
- Register MemSemanticsReg;
- if (MemFlags == MemSemantics) {
- MemSemanticsReg = Call->Arguments[0];
- if (!MRI->getRegClassOrNull(MemSemanticsReg))
- MRI->setRegClass(MemSemanticsReg, &SPIRV::iIDRegClass);
- } else {
- MemSemanticsReg = buildConstantIntReg32(MemSemantics, MIRBuilder, GR);
- }
-
+ Register MemSemanticsReg =
+ MemFlags == MemSemantics
+ ? Call->Arguments[0]
+ : buildConstantIntReg32(MemSemantics, MIRBuilder, GR);
Register ScopeReg;
SPIRV::Scope::Scope Scope = SPIRV::Scope::Workgroup;
SPIRV::Scope::Scope MemScope = Scope;
@@ -963,12 +924,8 @@ static bool buildBarrierInst(const SPIRV::IncomingCall *Call, unsigned Opcode,
if (!(MemFlags & SPIRV::CLK_LOCAL_MEM_FENCE) ||
(Opcode == SPIRV::OpMemoryBarrier))
Scope = MemScope;
-
- if (CLScope == static_cast<unsigned>(Scope)) {
+ if (CLScope == static_cast<unsigned>(Scope))
ScopeReg = Call->Arguments[1];
- if (!MRI->getRegClassOrNull(ScopeReg))
- MRI->setRegClass(ScopeReg, &SPIRV::iIDRegClass);
- }
}
if (!ScopeReg.isValid())
@@ -1078,19 +1035,13 @@ static bool generateGroupInst(const SPIRV::IncomingCall *Call,
"Group Operation parameter must be an integer constant");
uint64_t GrpOp = MI->getOperand(1).getCImm()->getValue().getZExtValue();
Register ScopeReg = Call->Arguments[0];
- if (!MRI->getRegClassOrNull(ScopeReg))
- MRI->setRegClass(ScopeReg, &SPIRV::iIDRegClass);
auto MIB = MIRBuilder.buildInstr(GroupBuiltin->Opcode)
.addDef(Call->ReturnRegister)
.addUse(GR->getSPIRVTypeID(Call->ReturnType))
.addUse(ScopeReg)
.addImm(GrpOp);
- for (unsigned i = 2; i < Call->Arguments.size(); ++i) {
- Register ArgReg = Call->Arguments[i];
- if (!MRI->getRegClassOrNull(ArgReg))
- MRI->setRegClass(ArgReg, &SPIRV::iIDRegClass);
- MIB.addUse(ArgReg);
- }
+ for (unsigned i = 2; i < Call->Arguments.size(); ++i)
+ MIB.addUse(Call->Arguments[i]);
return true;
}
@@ -1183,10 +1134,8 @@ static bool generateGroupInst(const SPIRV::IncomingCall *Call,
if (VecReg.isValid())
MIB.addUse(VecReg);
else
- for (unsigned i = 1; i < Call->Arguments.size(); i++) {
+ for (unsigned i = 1; i < Call->Arguments.size(); i++)
MIB.addUse(Call->Arguments[i]);
- MRI->setRegClass(Call->Arguments[i], &SPIRV::iIDRegClass);
- }
}
// Build select instruction.
@@ -1220,7 +1169,6 @@ static bool generateIntelSubgroupsInst(const SPIRV::IncomingCall *Call,
: Register(0));
}
- MachineRegisterInfo *MRI = MIRBuilder.getMRI();
if (IntelSubgroups->IsBlock) {
// Minimal number or arguments set in TableGen records is 1
if (SPIRVType *Arg0Type = GR->getSPIRVTypeForVReg(Call->Arguments[0])) {
@@ -1257,13 +1205,8 @@ static bool generateIntelSubgroupsInst(const SPIRV::IncomingCall *Call,
: MIRBuilder.buildInstr(OpCode)
.addDef(Call->ReturnRegister)
.addUse(GR->getSPIRVTypeID(Call->ReturnType));
- for (size_t i = 0; i < Call->Arguments.size(); ++i) {
- Register ArgReg = Call->Arguments[i];
- MIB.addUse(ArgReg);
- if (!MRI->getRegClassOrNull(ArgReg))
- MRI->setRegClass(ArgReg, &SPIRV::iIDRegClass);
- }
-
+ for (size_t i = 0; i < Call->Arguments.size(); ++i)
+ MIB.addUse(Call->Arguments[i]);
return true;
}
@@ -1285,13 +1228,8 @@ static bool generateGroupUniformInst(const SPIRV::IncomingCall *Call,
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
Register GroupResultReg = Call->ReturnRegister;
- if (!MRI->getRegClassOrNull(GroupResultReg))
- MRI->setRegClass(GroupResultReg, GR->getRegClass(Call->ReturnType));
-
- // Scope
Register ScopeReg = Call->Arguments[0];
- if (!MRI->getRegClassOrNull(ScopeReg))
- MRI->setRegClass(ScopeReg, &SPIRV::iIDRegClass);
+ Register ValueReg = Call->Arguments[2];
// Group Operation
Register ConstGroupOpReg = Call->Arguments[1];
@@ -1306,11 +1244,6 @@ static bool generateGroupUniformInst(const SPIRV::IncomingCall *Call,
"integer constant",
false);
- // Value
- Register ValueReg = Call->Arguments[2];
- if (!MRI->getRegClassOrNull(ValueReg))
- MRI->setRegClass(ValueReg, GR->getRegClass(Call->ReturnType));
-
auto MIB = MIRBuilder.buildInstr(GroupUniform->Opcode)
.addDef(GroupResultReg)
.addUse(GR->getSPIRVTypeID(Call->ReturnType))
@@ -1334,10 +1267,7 @@ static bool generateKernelClockInst(const SPIRV::IncomingCall *Call,
report_fatal_error(DiagMsg.c_str(), false);
}
- MachineRegisterInfo *MRI = MIRBuilder.getMRI();
Register ResultReg = Call->ReturnRegister;
- if (!MRI->getRegClassOrNull(ResultReg))
- MRI->setRegClass(ResultReg, &SPIRV::iIDRegClass);
// Deduce the `Scope` operand from the builtin function name.
SPIRV::Scope::Scope ScopeArg =
@@ -1654,7 +1584,6 @@ static bool generateImageSizeQueryInst(const SPIRV::IncomingCall *Call,
bool IsDimBuf = ImgType->getOperand(2).getImm() == SPIRV::Dim::DIM_Buffer;
unsigned Opcode =
IsDimBuf ? SPIRV::OpImageQuerySize : SPIRV::OpImageQuerySizeLod;
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
auto MIB = MIRBuilder.buildInstr(Opcode)
.addDef(QueryResult)
.addUse(GR->getSPIRVTypeID(QueryResultType))
@@ -1710,7 +1639,6 @@ static bool generateImageMiscQueryInst(const SPIRV::IncomingCall *Call,
SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode;
Register Image = Call->Arguments[0];
- MIRBuilder.getMRI()->setRegClass(Image, &SPIRV::iIDRegClass);
SPIRV::Dim::Dim ImageDimensionality = static_cast<SPIRV::Dim::Dim>(
GR->getSPIRVTypeForVReg(Image)->getOperand(2).getImm());
(void)ImageDimensionality;
@@ -1774,12 +1702,8 @@ static bool generateReadImageInst(const StringRef DemangledCall,
SPIRVGlobalRegistry *GR) {
Register Image = Call->Arguments[0];
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
- MRI->setRegClass(Image, &SPIRV::iIDRegClass);
- MRI->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
bool HasOclSampler = DemangledCall.contains_insensitive("ocl_sampler");
bool HasMsaa = DemangledCall.contains_insensitive("msaa");
- if (HasOclSampler || HasMsaa)
- MRI->setRegClass(Call->Arguments[2], &SPIRV::iIDRegClass);
if (HasOclSampler) {
Register Sampler = Call->Arguments[1];
@@ -1805,32 +1729,35 @@ static bool generateReadImageInst(const StringRef DemangledCall,
Register Lod = GR->buildConstantFP(APFloat::getZero(APFloat::IEEEsingle()),
MIRBuilder);
- SPIRVType *TempType = Call->ReturnType;
- bool NeedsExtraction = false;
- if (TempType->getOpcode() != SPIRV::OpTypeVector) {
- TempType =
- GR->getOrCreateSPIRVVectorType(Call->ReturnType, 4, MIRBuilder);
- NeedsExtraction = true;
- }
- LLT LLType = LLT::scalar(GR->getScalarOrVectorBitWidth(TempType));
- Register TempRegister = MRI->createGenericVirtualRegister(LLType);
- MRI->setRegClass(TempRegister, &SPIRV::iIDRegClass);
- GR->assignSPIRVTypeToVReg(TempType, TempRegister, MIRBuilder.getMF());
- MIRBuilder.buildInstr(SPIRV::OpImageSampleExplicitLod)
- .addDef(NeedsExtraction ? TempRegister : Call->ReturnRegister)
- .addUse(GR->getSPIRVTypeID(TempType))
- .addUse(SampledImage)
- .addUse(Call->Arguments[2]) // Coordinate.
- .addImm(SPIRV::ImageOperand::Lod)
- .addUse(Lod);
-
- if (NeedsExtraction)
+ if (Call->ReturnType->getOpcode() != SPIRV::OpTypeVector) {
+ SPIRVType *TempType =
+ GR->getOrCreateSPIRVVectorType(Call->ReturnType, 4, MIRBuilder);
+ Register TempRegister =
+ MRI->createGenericVirtualRegister(GR->getRegType(TempType));
+ MRI->setRegClass(TempRegister, GR->getRegClass(TempType));
+ GR->assignSPIRVTypeToVReg(TempType, TempRegister, MIRBuilder.getMF());
+ MIRBuilder.buildInstr(SPIRV::OpImageSampleExplicitLod)
+ .addDef(TempRegister)
+ .addUse(GR->getSPIRVTypeID(TempType))
+ .addUse(SampledImage)
+ .addUse(Call->Arguments[2]) // Coordinate.
+ .addImm(SPIRV::ImageOperand::Lod)
+ .addUse(Lod);
MIRBuilder.buildInstr(SPIRV::OpCompositeExtract)
.addDef(Call->ReturnRegister)
.addUse(GR->getSPIRVTypeID(Call->ReturnType))
.addUse(TempRegister)
.addImm(0);
+ } else {
+ MIRBuilder.buildInstr(SPIRV::OpImageSampleExplicitLod)
+ .addDef(Call->ReturnRegister)
+ .addUse(GR->getSPIRVTypeID(Call->ReturnType))
+ .addUse(SampledImage)
+ .addUse(Call->Arguments[2]) // Coordinate.
+ .addImm(SPIRV::ImageOperand::Lod)
+ .addUse(Lod);
+ }
} else if (HasMsaa) {
MIRBuilder.buildInstr(SPIRV::OpImageRead)
.addDef(Call->ReturnRegister)
@@ -1852,9 +1779,6 @@ static bool generateReadImageInst(const StringRef DemangledCall,
static bool generateWriteImageInst(const SPIRV::IncomingCall *Call,
MachineIRBuilder &MIRBuilder,
SPIRVGlobalRegistry *GR) {
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[2], &SPIRV::iIDRegClass);
MIRBuilder.buildInstr(SPIRV::OpImageWrite)
.addUse(Call->Arguments[0]) // Image.
.addUse(Call->Arguments[1]) // Coordinate.
@@ -1909,10 +1833,6 @@ static bool generateSampleImageInst(const StringRef DemangledCall,
"Unable to recognize SPIRV type name: " + ReturnType;
report_fatal_error(DiagMsg.c_str());
}
- MRI->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
- MRI->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
- MRI->setRegClass(Call->Arguments[3], &SPIRV::iIDRegClass);
-
MIRBuilder.buildInstr(SPIRV::OpImageSampleExplicitLod)
.addDef(Call->ReturnRegister)
.addUse(GR->getSPIRVTypeID(Type))
@@ -2031,7 +1951,6 @@ static bool buildNDRange(const SPIRV::IncomingCall *Call,
MachineIRBuilder &MIRBuilder,
SPIRVGlobalRegistry *GR) {
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
- MRI->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
SPIRVType *PtrType = GR->getSPIRVTypeForVReg(Call->Arguments[0]);
assert(PtrType->getOpcode() == SPIRV::OpTypePointer &&
PtrType->getOperand(2).isReg());
@@ -2045,14 +1964,9 @@ static bool buildNDRange(const SPIRV::IncomingCall *Call,
unsigned NumArgs = Call->Arguments.size();
assert(NumArgs >= 2);
Register GlobalWorkSize = Call->Arguments[NumArgs < 4 ? 1 : 2];
- MRI->setRegClass(GlobalWorkSize, &SPIRV::iIDRegClass);
Register LocalWorkSize =
NumArgs == 2 ? Register(0) : Call->Arguments[NumArgs < 4 ? 2 : 3];
- if (LocalWorkSize.isValid())
- MRI->setRegClass(LocalWorkSize, &SPIRV::iIDRegClass);
Register GlobalWorkOffset = NumArgs <= 3 ? Register(0) : Call->Arguments[1];
- if (GlobalWorkOffset.isValid())
- MRI->setRegClass(GlobalWorkOffset, &SPIRV::iIDRegClass);
if (NumArgs < 4) {
Register Const;
SPIRVType *SpvTy = GR->getSPIRVTypeForVReg(GlobalWorkSize);
@@ -2061,8 +1975,6 @@ static bool buildNDRange(const SPIRV::IncomingCall *Call,
assert(DefInstr && isSpvIntrinsic(*DefInstr, Intrinsic::spv_gep) &&
DefInstr->getOperand(3).isReg());
Register GWSPtr = DefInstr->getOperand(3).getReg();
- if (!MRI->getRegClassOrNull(GWSPtr))
- MRI->setRegClass(GWSPtr, &SPIRV::iIDRegClass);
// TODO: Maybe simplify generation of the type of the fields.
unsigned Size = Call->Builtin->Name == "ndrange_3D" ? 3 : 2;
unsigned BitWidth = GR->getPointerSize() == 64 ? 64 : 32;
@@ -2211,7 +2123,6 @@ static bool generateEnqueueInst(const SPIRV::IncomingCall *Call,
switch (Opcode) {
case SPIRV::OpRetainEvent:
case SPIRV::OpReleaseEvent:
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
return MIRBuilder.buildInstr(Opcode).addUse(Call->Arguments[0]);
case SPIRV::OpCreateUserEvent:
case SPIRV::OpGetDefaultQueue:
@@ -2219,21 +2130,15 @@ static bool generateEnqueueInst(const SPIRV::IncomingCall *Call,
.addDef(Call->ReturnRegister)
.addUse(GR->getSPIRVTypeID(Call->ReturnType));
case SPIRV::OpIsValidEvent:
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
return MIRBuilder.buildInstr(Opcode)
.addDef(Call->ReturnRegister)
.addUse(GR->getSPIRVTypeID(Call->ReturnType))
.addUse(Call->Arguments[0]);
case SPIRV::OpSetUserEventStatus:
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
return MIRBuilder.buildInstr(Opcode)
.addUse(Call->Arguments[0])
.addUse(Call->Arguments[1]);
case SPIRV::OpCaptureEventProfilingInfo:
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[2], &SPIRV::iIDRegClass);
return MIRBuilder.buildInstr(Opcode)
.addUse(Call->Arguments[0])
.addUse(Call->Arguments[1])
@@ -2446,22 +2351,15 @@ static bool generateLoadStoreInst(const SPIRV::IncomingCall *Call,
// Add a pointer to the value to load/store.
MIB.addUse(Call->Arguments[0]);
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
- MRI->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
// Add a value to store.
- if (!IsLoad) {
+ if (!IsLoad)
MIB.addUse(Call->Arguments[1]);
- MRI->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
- }
// Add optional memory attributes and an alignment.
unsigned NumArgs = Call->Arguments.size();
- if ((IsLoad && NumArgs >= 2) || NumArgs >= 3) {
+ if ((IsLoad && NumArgs >= 2) || NumArgs >= 3)
MIB.addImm(getConstFromIntrinsic(Call->Arguments[IsLoad ? 1 : 2], MRI));
- MRI->setRegClass(Call->Arguments[IsLoad ? 1 : 2], &SPIRV::iIDRegClass);
- }
- if ((IsLoad && NumArgs >= 3) || NumArgs >= 4) {
+ if ((IsLoad && NumArgs >= 3) || NumArgs >= 4)
MIB.addImm(getConstFromIntrinsic(Call->Arguments[IsLoad ? 2 : 3], MRI));
- MRI->setRegClass(Call->Arguments[IsLoad ? 2 : 3], &SPIRV::iIDRegClass);
- }
return true;
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
index 8db9808bb87e1d..4cc4dbbde8e6a0 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
@@ -413,6 +413,12 @@ void SPIRVTargetLowering::finalizeLowering(MachineFunction &MF) const {
validateForwardCalls(STI, MRI, GR, MI);
break;
+ case SPIRV::OpIAddS:
+ if (GR.isScalarOrVectorOfType(MI.getOperand(1).getReg(),
+ SPIRV::OpTypeBool))
+ MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpLogicalOr));
+ break;
+
// ensure that LLVM IR bitwise instructions result in logical SPIR-V
// instructions when applied to bool type
case SPIRV::OpBitwiseOrS:
>From 7b40fbe42fe7956159826b9ea035a65435fe5d39 Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Tue, 20 Aug 2024 09:35:47 -0700
Subject: [PATCH 10/14] account for arbitrary integer sizes, update legalizer
---
llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp | 71 ++++++++++++++-----
llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 55 +++-----------
.../test/CodeGen/SPIRV/hlsl-intrinsics/abs.ll | 2 +-
.../CodeGen/SPIRV/hlsl-intrinsics/acos.ll | 2 +-
.../CodeGen/SPIRV/hlsl-intrinsics/asin.ll | 2 +-
.../CodeGen/SPIRV/hlsl-intrinsics/atan.ll | 2 +-
.../CodeGen/SPIRV/hlsl-intrinsics/ceil.ll | 2 +-
.../test/CodeGen/SPIRV/hlsl-intrinsics/cos.ll | 2 +-
.../CodeGen/SPIRV/hlsl-intrinsics/cosh.ll | 2 +-
.../test/CodeGen/SPIRV/hlsl-intrinsics/exp.ll | 2 +-
.../CodeGen/SPIRV/hlsl-intrinsics/exp2.ll | 2 +-
11 files changed, 73 insertions(+), 71 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
index e11b4e3db2060e..9fe4d8a16bc32a 100644
--- a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
@@ -54,6 +54,13 @@ bool isTypeFoldingSupported(unsigned Opcode) {
return TypeFoldingSupportingOpcs.count(Opcode) > 0;
}
+LegalityPredicate typeOfExtendedScalars(unsigned TypeIdx, bool IsExtendedInts) {
+ return [IsExtendedInts, TypeIdx](const LegalityQuery &Query) {
+ const LLT Ty = Query.Types[TypeIdx];
+ return IsExtendedInts && Ty.isValid() && Ty.isScalar();
+ };
+}
+
SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
using namespace TargetOpcode;
@@ -143,6 +150,27 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
auto allPtrs = {p0, p1, p2, p3, p4, p5, p6};
+ bool IsExtendedInts =
+ ST.canUseExtension(
+ SPIRV::Extension::SPV_INTEL_arbitrary_precision_integers) ||
+ ST.canUseExtension(SPIRV::Extension::SPV_KHR_bit_instructions);
+ auto extendedScalarsAndVectors =
+ [IsExtendedInts](const LegalityQuery &Query) {
+ const LLT Ty = Query.Types[0];
+ return IsExtendedInts && Ty.isValid() && !Ty.isPointerOrPointerVector();
+ };
+ auto extendedScalarsAndVectorsProduct = [IsExtendedInts](
+ const LegalityQuery &Query) {
+ const LLT Ty1 = Query.Types[0], Ty2 = Query.Types[1];
+ return IsExtendedInts && Ty1.isValid() && Ty2.isValid() &&
+ !Ty1.isPointerOrPointerVector() && !Ty2.isPointerOrPointerVector();
+ };
+ auto extendedPtrsScalarsAndVectors =
+ [IsExtendedInts](const LegalityQuery &Query) {
+ const LLT Ty = Query.Types[0];
+ return IsExtendedInts && Ty.isValid();
+ };
+
for (auto Opc : TypeFoldingSupportingOpcs)
getActionDefinitionsBuilder(Opc).custom();
@@ -182,7 +210,11 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
getActionDefinitionsBuilder({G_LOAD, G_STORE}).legalIf(typeInSet(1, allPtrs));
- getActionDefinitionsBuilder(G_BITREVERSE).legalFor(allIntScalarsAndVectors);
+ getActionDefinitionsBuilder({G_SMIN, G_SMAX, G_UMIN, G_UMAX, G_ABS,
+ G_BITREVERSE, G_SADDSAT, G_UADDSAT, G_SSUBSAT,
+ G_USUBSAT})
+ .legalFor(allIntScalarsAndVectors)
+ .legalIf(extendedScalarsAndVectors);
getActionDefinitionsBuilder(G_FMA).legalFor(allFloatScalarsAndVectors);
@@ -194,13 +226,18 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
.legalForCartesianProduct(allFloatScalarsAndVectors,
allScalarsAndVectors);
- getActionDefinitionsBuilder({G_SMIN, G_SMAX, G_UMIN, G_UMAX, G_ABS})
- .legalFor(allIntScalarsAndVectors);
+ getActionDefinitionsBuilder(G_CTPOP)
+ .legalForCartesianProduct(allIntScalarsAndVectors)
+ .legalIf(extendedScalarsAndVectorsProduct);
- getActionDefinitionsBuilder(G_CTPOP).legalForCartesianProduct(
- allIntScalarsAndVectors, allIntScalarsAndVectors);
+ // Extensions.
+ getActionDefinitionsBuilder({G_TRUNC, G_ZEXT, G_SEXT, G_ANYEXT})
+ .legalForCartesianProduct(allScalarsAndVectors)
+ .legalIf(extendedScalarsAndVectorsProduct);
- getActionDefinitionsBuilder(G_PHI).legalFor(allPtrsScalarsAndVectors);
+ getActionDefinitionsBuilder(G_PHI)
+ .legalFor(allPtrsScalarsAndVectors)
+ .legalIf(extendedPtrsScalarsAndVectors);
getActionDefinitionsBuilder(G_BITCAST).legalIf(
all(typeInSet(0, allPtrsScalarsAndVectors),
@@ -211,11 +248,17 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
getActionDefinitionsBuilder({G_STACKSAVE, G_STACKRESTORE}).alwaysLegal();
getActionDefinitionsBuilder(G_INTTOPTR)
- .legalForCartesianProduct(allPtrs, allIntScalars);
+ .legalForCartesianProduct(allPtrs, allIntScalars)
+ .legalIf(
+ all(typeInSet(0, allPtrs), typeOfExtendedScalars(1, IsExtendedInts)));
getActionDefinitionsBuilder(G_PTRTOINT)
- .legalForCartesianProduct(allIntScalars, allPtrs);
- getActionDefinitionsBuilder(G_PTR_ADD).legalForCartesianProduct(
- allPtrs, allIntScalars);
+ .legalForCartesianProduct(allIntScalars, allPtrs)
+ .legalIf(
+ all(typeOfExtendedScalars(0, IsExtendedInts), typeInSet(1, allPtrs)));
+ getActionDefinitionsBuilder(G_PTR_ADD)
+ .legalForCartesianProduct(allPtrs, allIntScalars)
+ .legalIf(
+ all(typeInSet(0, allPtrs), typeOfExtendedScalars(1, IsExtendedInts)));
// ST.canDirectlyComparePointers() for pointer args is supported in
// legalizeCustom().
@@ -247,10 +290,6 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
getActionDefinitionsBuilder({G_UADDO, G_USUBO, G_SMULO, G_UMULO})
.alwaysLegal();
- // Extensions.
- getActionDefinitionsBuilder({G_TRUNC, G_ZEXT, G_SEXT, G_ANYEXT})
- .legalForCartesianProduct(allScalarsAndVectors);
-
// FP conversions.
getActionDefinitionsBuilder({G_FPTRUNC, G_FPEXT})
.legalForCartesianProduct(allFloatScalarsAndVectors);
@@ -310,10 +349,6 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
// Struct return types become a single scalar, so cannot easily legalize.
getActionDefinitionsBuilder({G_SMULH, G_UMULH}).alwaysLegal();
-
- // supported saturation arithmetic
- getActionDefinitionsBuilder({G_SADDSAT, G_UADDSAT, G_SSUBSAT, G_USUBSAT})
- .legalFor(allIntScalarsAndVectors);
}
getLegacyLegalizerInfo().computeTables();
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 131dc0b81a1cd7..4e45aa4b888a92 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -319,46 +319,6 @@ static void widenScalarLLTNextPow2(Register Reg, MachineRegisterInfo &MRI) {
MRI.setType(Reg, LLT::scalar(NewSz));
}
-inline bool getIsFloat(SPIRVType *SpvType, const SPIRVGlobalRegistry &GR) {
- bool IsFloat = SpvType->getOpcode() == SPIRV::OpTypeFloat;
- return IsFloat ? true
- : SpvType->getOpcode() == SPIRV::OpTypeVector &&
- GR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg())
- ->getOpcode() == SPIRV::OpTypeFloat;
-}
-
-/*
-static std::pair<Register, unsigned>
-createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
- const SPIRVGlobalRegistry &GR) {
- if (!SpvType)
- SpvType = GR.getSPIRVTypeForVReg(SrcReg);
- assert(SpvType && "VReg is expected to have SPIRV type");
- LLT NewT;
- LLT SrcLLT = MRI.getType(SrcReg);
- bool IsFloat = getIsFloat(SpvType, GR);
- auto GetIdOp = IsFloat ? SPIRV::GET_fID : SPIRV::GET_ID;
- bool IsVec = SrcLLT.isVector();
- unsigned NumElements =
- IsVec ? std::max(2U, GR.getScalarOrVectorComponentCount(SpvType)) : 1;
- if (SrcLLT.isPointer()) {
- unsigned PtrSz = GR.getPointerSize();
- NewT = LLT::pointer(0, PtrSz);
- if (IsVec)
- NewT = LLT::fixed_vector(NumElements, NewT);
- GetIdOp = IsVec ? SPIRV::GET_vpID : SPIRV::GET_pID;
- } else if (IsVec) {
- NewT = LLT::fixed_vector(
- NumElements, LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType)));
- GetIdOp = IsFloat ? SPIRV::GET_vfID : SPIRV::GET_vID;
- } else {
- NewT = LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
- }
- Register IdReg = MRI.createGenericVirtualRegister(NewT);
- MRI.setRegClass(IdReg, GR.getRegClass(SpvType));
- return {IdReg, GetIdOp};
-}
-*/
static std::pair<Register, unsigned>
createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
const SPIRVGlobalRegistry &GR) {
@@ -454,6 +414,11 @@ generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
SmallVector<MachineInstr *, 10> ToErase;
DenseMap<MachineInstr *, Register> RegsAlreadyAddedToDT;
+ bool IsExtendedInts =
+ ST->canUseExtension(
+ SPIRV::Extension::SPV_INTEL_arbitrary_precision_integers) ||
+ ST->canUseExtension(SPIRV::Extension::SPV_KHR_bit_instructions);
+
for (MachineBasicBlock *MBB : post_order(&MF)) {
if (MBB->empty())
continue;
@@ -464,10 +429,12 @@ generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
MachineInstr &MI = *MII;
unsigned MIOp = MI.getOpcode();
- // validate bit width of scalar registers
- for (const auto &MOP : MI.operands())
- if (MOP.isReg())
- widenScalarLLTNextPow2(MOP.getReg(), MRI);
+ if (!IsExtendedInts) {
+ // validate bit width of scalar registers
+ for (const auto &MOP : MI.operands())
+ if (MOP.isReg())
+ widenScalarLLTNextPow2(MOP.getReg(), MRI);
+ }
if (isSpvIntrinsic(MI, Intrinsic::spv_assign_ptr_type)) {
Register Reg = MI.getOperand(1).getReg();
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/abs.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/abs.ll
index 38c033bdd4dd78..8f1092c2206ed8 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/abs.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/abs.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/acos.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/acos.ll
index fb0ced342aba39..7c9450267cbe89 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/acos.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/acos.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/asin.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/asin.ll
index a8424170b26e3b..4d57c6fce77f70 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/asin.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/asin.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan.ll
index 65975fc413e532..65e198d0e71a35 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/ceil.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/ceil.ll
index 1b358ae54502ba..93677aadffa5e9 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/ceil.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/ceil.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cos.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cos.ll
index 28675cf9f15412..e9e9642354f5a5 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cos.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cos.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cosh.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cosh.ll
index 35ba1d69d7cbb1..1560f9b9bd7605 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cosh.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cosh.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp.ll
index ee230df41a6c7b..c1734a264ea042 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp2.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp2.ll
index eeaca1b6560af0..4753b7bd9fe5bd 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp2.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp2.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpExtInstImport "GLSL.std.450"
>From 1023742ca936b11af8d0cc3e4c499fd16d619a0c Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Tue, 20 Aug 2024 09:46:37 -0700
Subject: [PATCH 11/14] update tests with '-verify-machineinstrs'
---
.../test/CodeGen/SPIRV/hlsl-intrinsics/SV_DispatchThreadID.ll | 2 +-
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneIndex.ll | 2 +-
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/floor.ll | 2 +-
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmad.ll | 2 +-
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll | 2 +-
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll | 2 +-
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/frac.ll | 2 +-
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/lerp.ll | 2 +-
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log.ll | 2 +-
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log2.ll | 2 +-
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/pow.ll | 2 +-
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rcp.ll | 2 +-
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/reversebits.ll | 2 +-
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/round.ll | 2 +-
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rsqrt.ll | 2 +-
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sin.ll | 2 +-
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sinh.ll | 2 +-
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smax.ll | 2 +-
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smin.ll | 2 +-
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sqrt.ll | 2 +-
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tan.ll | 2 +-
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tanh.ll | 2 +-
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/trunc.ll | 2 +-
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umax.ll | 2 +-
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umin.ll | 2 +-
llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll | 2 +-
llvm/test/CodeGen/SPIRV/llvm-intrinsics/bswap.ll | 2 +-
llvm/test/CodeGen/SPIRV/llvm-intrinsics/ceil.ll | 2 +-
llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctlz.ll | 2 +-
llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctpop.ll | 2 +-
llvm/test/CodeGen/SPIRV/llvm-intrinsics/cttz.ll | 2 +-
llvm/test/CodeGen/SPIRV/llvm-intrinsics/fabs.ll | 2 +-
llvm/test/CodeGen/SPIRV/llvm-intrinsics/fp-intrinsics.ll | 2 +-
llvm/test/CodeGen/SPIRV/llvm-intrinsics/invariant.ll | 2 +-
llvm/test/CodeGen/SPIRV/llvm-intrinsics/lifetime.ll | 4 ++--
.../CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmax.ll | 2 +-
.../SPIRV/llvm-intrinsics/llvm-vector-reduce/fmaximum.ll | 2 +-
.../CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmin.ll | 2 +-
.../SPIRV/llvm-intrinsics/llvm-vector-reduce/fminimum.ll | 2 +-
.../CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmul.ll | 2 +-
.../CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/mul.ll | 2 +-
.../CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/or.ll | 2 +-
.../CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smax.ll | 2 +-
.../CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smin.ll | 2 +-
.../CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umax.ll | 2 +-
.../CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umin.ll | 2 +-
.../CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/xor.ll | 2 +-
llvm/test/CodeGen/SPIRV/llvm-intrinsics/maxnum.ll | 2 +-
llvm/test/CodeGen/SPIRV/llvm-intrinsics/nearbyint.ll | 2 +-
llvm/test/CodeGen/SPIRV/llvm-intrinsics/ptr-annotation.ll | 2 +-
llvm/test/CodeGen/SPIRV/llvm-intrinsics/satur-arith.ll | 4 ++--
llvm/test/CodeGen/SPIRV/llvm-intrinsics/sqrt.ll | 2 +-
llvm/test/CodeGen/SPIRV/llvm-intrinsics/umul.with.overflow.ll | 2 +-
llvm/test/CodeGen/SPIRV/pointers/argument-ptr-to-struct.ll | 2 +-
llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-load.ll | 2 +-
llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-store.ll | 2 +-
llvm/test/CodeGen/SPIRV/pointers/complex.ll | 4 ++--
llvm/test/CodeGen/SPIRV/pointers/custom-kernel-arg-type.ll | 2 +-
llvm/test/CodeGen/SPIRV/pointers/duplicate-type-ptr-def.ll | 2 +-
.../test/CodeGen/SPIRV/pointers/getelementptr-addressspace.ll | 2 +-
llvm/test/CodeGen/SPIRV/pointers/getelementptr-base-type.ll | 2 +-
.../test/CodeGen/SPIRV/pointers/getelementptr-bitcast-load.ll | 2 +-
.../CodeGen/SPIRV/pointers/getelementptr-kernel-arg-char.ll | 2 +-
llvm/test/CodeGen/SPIRV/pointers/global-ptrtoint.ll | 4 ++--
llvm/test/CodeGen/SPIRV/pointers/global-zeroinitializer.ll | 4 ++--
.../kernel-argument-builtin-vload-type-discrapency.ll | 2 +-
.../SPIRV/pointers/kernel-argument-pointer-addressspace.ll | 2 +-
...l-argument-pointer-type-deduction-no-bitcast-to-generic.ll | 2 +-
.../kernel-argument-pointer-type-deduction-no-metadata.ll | 2 +-
.../CodeGen/SPIRV/pointers/kernel-argument-pointer-type.ll | 2 +-
.../pointers/kernel-argument-ptr-i8-default-element-type.ll | 2 +-
.../CodeGen/SPIRV/pointers/kernel-argument-ptr-no-bitcast.ll | 2 +-
llvm/test/CodeGen/SPIRV/pointers/load-addressspace.ll | 2 +-
.../CodeGen/SPIRV/pointers/nested-struct-opaque-pointers.ll | 2 +-
llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byref.ll | 2 +-
llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byval.ll | 2 +-
.../pointers/store-kernel-arg-i8-ptr-as-value-operand.ll | 2 +-
.../SPIRV/pointers/store-kernel-arg-ptr-as-value-operand.ll | 2 +-
.../CodeGen/SPIRV/pointers/store-operand-ptr-to-struct.ll | 2 +-
llvm/test/CodeGen/SPIRV/pointers/struct-opaque-pointers.ll | 2 +-
.../test/CodeGen/SPIRV/pointers/two-bitcast-or-param-users.ll | 2 +-
llvm/test/CodeGen/SPIRV/pointers/two-subsequent-bitcasts.ll | 2 +-
llvm/test/CodeGen/SPIRV/pointers/type-deduce-args-rev.ll | 2 +-
llvm/test/CodeGen/SPIRV/pointers/type-deduce-args.ll | 2 +-
llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-chain.ll | 2 +-
.../CodeGen/SPIRV/pointers/type-deduce-by-call-complex.ll | 2 +-
llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-rev.ll | 2 +-
llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call.ll | 2 +-
.../CodeGen/SPIRV/pointers/type-deduce-call-no-bitcast.ll | 2 +-
llvm/test/CodeGen/SPIRV/pointers/typeof-ptr-int.ll | 2 +-
llvm/test/CodeGen/SPIRV/pointers/variables-storage-class.ll | 2 +-
91 files changed, 96 insertions(+), 96 deletions(-)
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_DispatchThreadID.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_DispatchThreadID.ll
index e93271b703f7b2..c84b1c4b06c199 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_DispatchThreadID.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_DispatchThreadID.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-vulkan-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-vulkan-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o - -filetype=obj | spirv-val %}
; This file generated from the following command:
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneIndex.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneIndex.ll
index ec35690ac1547c..89a8575fa15991 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneIndex.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneIndex.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-vulkan-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-vulkan-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o - -filetype=obj | spirv-val %}
; This file generated from the following command:
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/floor.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/floor.ll
index 5b972104d50389..ea19fa94ea3265 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/floor.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/floor.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmad.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmad.ll
index ce9b8f09daead1..b1ca34dc504c03 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmad.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmad.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll
index 159d4ac19c8cc8..ca0fcfe8d646b6 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll
index 15946b5038eec3..adc563bcea5c6c 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/frac.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/frac.ll
index 3c48782a185862..4c088b6b38103c 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/frac.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/frac.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/lerp.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/lerp.ll
index 63547820c18c77..aa7ad8c74d336c 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/lerp.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/lerp.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; Make sure SPIRV operation function calls for lerp are generated as FMix
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log.ll
index 5a09f32b83b2d4..f85b20324da515 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log2.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log2.ll
index 21f02a40fc089e..add7f77897f790 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log2.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log2.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/pow.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/pow.ll
index 7fae9637946fa2..3ac98853b92fbc 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/pow.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/pow.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rcp.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rcp.ll
index 34f3c610ca81da..6f91162a378c8a 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rcp.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rcp.ll
@@ -1,4 +1,4 @@
- ; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+ ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: %[[#float_64:]] = OpTypeFloat 64
; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/reversebits.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/reversebits.ll
index e58c9ab6dfb1c1..a23b15ab075d60 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/reversebits.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/reversebits.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpMemoryModel Logical GLSL450
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/round.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/round.ll
index baf20833840b65..1c7e78261ffefd 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/round.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/round.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rsqrt.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rsqrt.ll
index 650b32910d65e6..91023a1e401e16 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rsqrt.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rsqrt.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sin.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sin.ll
index 061af5b37345ad..a6ae70a48e5db4 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sin.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sin.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sinh.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sinh.ll
index 55e050c5001bf4..3b8bdbed0041bb 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sinh.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sinh.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smax.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smax.ll
index 6bbf10323faba2..901e4764e15f67 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smax.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smax.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smin.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smin.ll
index 04ab9600c85b7c..c39c39f0455fad 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smin.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smin.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sqrt.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sqrt.ll
index 6882b77a427339..bb1f0346047e22 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sqrt.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sqrt.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tan.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tan.ll
index 7bdce99dbfaa7e..b4a6e1574f732b 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tan.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tan.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tanh.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tanh.ll
index 8cddc0fc090a7d..94fc3f0ec7abf5 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tanh.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tanh.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/trunc.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/trunc.ll
index d75b7fa5a381d8..2a308028a9b482 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/trunc.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/trunc.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umax.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umax.ll
index 32677df3d51831..01606a38732772 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umax.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umax.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umin.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umin.ll
index a91fb8096c2f0c..34185ad7143e32 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umin.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umin.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpExtInstImport "GLSL.std.450"
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll
index 48c96fae8b03a0..3d2080e0050b7a 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; CHECK-SPIRV-NOT: OpCapability ExpectAssumeKHR
; CHECK-SPIRV-NOT: OpExtension "SPV_KHR_expect_assume"
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/bswap.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/bswap.ll
index 3f2ab9fa7190bc..0ec99a602e4b04 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/bswap.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/bswap.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; CHECK-SPIRV: OpName %[[#FuncNameInt16:]] "spirv.llvm_bswap_i16"
; CHECK-SPIRV: OpName %[[#FuncNameInt32:]] "spirv.llvm_bswap_i32"
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ceil.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ceil.ll
index 8411d90e23f0d1..a960c876cb5964 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ceil.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ceil.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; CHECK: %[[#extinst_id:]] = OpExtInstImport "OpenCL.std"
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctlz.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctlz.ll
index 147fd80462f9ad..480ea761a669cf 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctlz.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctlz.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; CHECK: %[[#extinst_id:]] = OpExtInstImport "OpenCL.std"
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctpop.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctpop.ll
index f2d881b083dd7e..21598d712f5c32 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctpop.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctpop.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-linux %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-linux %s -o - | FileCheck %s
; CHECK: %[[#]] = OpBitCount %[[#]] %[[#]]
; CHECK: %[[#]] = OpBitCount %[[#]] %[[#]]
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/cttz.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/cttz.ll
index b9bdcfdb162f76..96abdfc30e73b6 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/cttz.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/cttz.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; CHECK: %[[#extinst_id:]] = OpExtInstImport "OpenCL.std"
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fabs.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fabs.ll
index 5de22021762927..fe170bb287cc9c 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fabs.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fabs.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; CHECK: %[[#extinst_id:]] = OpExtInstImport "OpenCL.std"
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fp-intrinsics.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fp-intrinsics.ll
index 8f14e8cf272ba7..3d46b527bf14f7 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fp-intrinsics.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fp-intrinsics.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; CHECK: %[[#extinst_id:]] = OpExtInstImport "OpenCL.std"
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/invariant.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/invariant.ll
index 5b700b7fcfee3e..bb6225f8ad4a6f 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/invariant.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/invariant.ll
@@ -1,5 +1,5 @@
;; Make sure the backend doesn't crash if the input LLVM IR contains llvm.invariant.* intrinsics
-; RUN: llc -O0 -mtriple=spirv64-unknown-linux %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-linux %s -o - | FileCheck %s
; CHECK-NOT: OpFunctionParameter
; CHECK-NOT: OpFunctionCall
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/lifetime.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/lifetime.ll
index 7fae8759c1f7d9..45683585d65146 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/lifetime.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/lifetime.ll
@@ -1,7 +1,7 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#Char:]] = OpTypeInt 8 0
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmax.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmax.ll
index 4f9cd29cd05d2a..eb0edae9f0ab56 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmax.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmax.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
target triple = "spir64-unknown-unknown"
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmaximum.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmaximum.ll
index 837bea0fbe6247..418cafaf80a164 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmaximum.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmaximum.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
target triple = "spir64-unknown-unknown"
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmin.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmin.ll
index 475da2e1ec31ea..b17d577b57226d 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmin.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmin.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
target triple = "spir64-unknown-unknown"
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fminimum.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fminimum.ll
index b525c849c3b59a..26bb7796957eb0 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fminimum.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fminimum.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
target triple = "spir64-unknown-unknown"
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmul.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmul.ll
index 0985be992ca74e..25efce819ad47f 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmul.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmul.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
target triple = "spir64-unknown-unknown"
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/mul.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/mul.ll
index 1a700577e46b41..16455f2e21cb6f 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/mul.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/mul.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
target triple = "spir64-unknown-unknown"
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/or.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/or.ll
index 90c6cf5562a924..badfebc27072f6 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/or.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/or.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
target triple = "spir64-unknown-unknown"
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smax.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smax.ll
index 4551fa31681d2b..54afb3a25b4d67 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smax.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smax.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
target triple = "spir64-unknown-unknown"
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smin.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smin.ll
index a0d257bb131804..a95c2ea0bbbf67 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smin.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smin.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
target triple = "spir64-unknown-unknown"
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umax.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umax.ll
index ba5dba76aeecca..a742009cef0111 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umax.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umax.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
target triple = "spir64-unknown-unknown"
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umin.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umin.ll
index e16bde88ef5094..7844c205c7ab0e 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umin.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umin.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
target triple = "spir64-unknown-unknown"
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/xor.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/xor.ll
index cf887bb358aca6..22f45a2c0bd6cc 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/xor.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/xor.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
target triple = "spir64-unknown-unknown"
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/maxnum.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/maxnum.ll
index 7b8c05d9c98eda..e9254c27ab4042 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/maxnum.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/maxnum.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
define spir_func float @Test(float %x, float %y) {
entry:
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/nearbyint.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/nearbyint.ll
index 70194e21982dc9..7405ca4d64d196 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/nearbyint.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/nearbyint.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] rint
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ptr-annotation.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ptr-annotation.ll
index 06f1d0bf7fd37c..556062a6fef4b4 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ptr-annotation.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ptr-annotation.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: OpName %[[#Foo:]] "foo"
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/satur-arith.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/satur-arith.ll
index 5b59206ff7f2d3..08f15c077fed92 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/satur-arith.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/satur-arith.ll
@@ -1,7 +1,7 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpExtInstImport "OpenCL.std"
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/sqrt.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/sqrt.ll
index e47b7b84c2b20c..5eec92f978b587 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/sqrt.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/sqrt.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: %[[#ExtInstSetId:]] = OpExtInstImport "OpenCL.std"
; CHECK-DAG: %[[#Float:]] = OpTypeFloat 32
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/umul.with.overflow.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/umul.with.overflow.ll
index 406a23fa7d3df5..c34771bf381ea9 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/umul.with.overflow.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/umul.with.overflow.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; CHECK-SPIRV: OpName %[[#NAME_UMUL_FUNC_8:]] "spirv.llvm_umul_with_overflow_i8"
; CHECK-SPIRV: OpName %[[#NAME_UMUL_FUNC_32:]] "spirv.llvm_umul_with_overflow_i32"
diff --git a/llvm/test/CodeGen/SPIRV/pointers/argument-ptr-to-struct.ll b/llvm/test/CodeGen/SPIRV/pointers/argument-ptr-to-struct.ll
index ac72ec28c37d9d..df57e94a04c409 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/argument-ptr-to-struct.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/argument-ptr-to-struct.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#VOID:]] = OpTypeVoid
diff --git a/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-load.ll b/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-load.ll
index 18752fdf843d20..d6a0071167cef2 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-load.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-load.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#TYLONG:]] = OpTypeInt 32 0
diff --git a/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-store.ll b/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-store.ll
index 202bcfbf2599a9..02641a8e75a55e 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-store.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-store.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#TYLONG:]] = OpTypeInt 32 0
diff --git a/llvm/test/CodeGen/SPIRV/pointers/complex.ll b/llvm/test/CodeGen/SPIRV/pointers/complex.ll
index 6253ef24283b67..3b0974bc084974 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/complex.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/complex.ll
@@ -1,7 +1,7 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: OpName %[[#Foo:]] "foo"
diff --git a/llvm/test/CodeGen/SPIRV/pointers/custom-kernel-arg-type.ll b/llvm/test/CodeGen/SPIRV/pointers/custom-kernel-arg-type.ll
index 4593fad783c60e..db804de26ecf1e 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/custom-kernel-arg-type.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/custom-kernel-arg-type.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: %[[TyInt:.*]] = OpTypeInt 8 0
diff --git a/llvm/test/CodeGen/SPIRV/pointers/duplicate-type-ptr-def.ll b/llvm/test/CodeGen/SPIRV/pointers/duplicate-type-ptr-def.ll
index 8e70bef3a5399a..2f7579aa11abb2 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/duplicate-type-ptr-def.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/duplicate-type-ptr-def.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: %[[#Char:]] = OpTypeInt 8 0
diff --git a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-addressspace.ll b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-addressspace.ll
index 7e9c6214c2818a..7a09ac973b590c 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-addressspace.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-addressspace.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: %[[#INT8:]] = OpTypeInt 8 0
diff --git a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-base-type.ll b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-base-type.ll
index fc999ba1a3cdac..c822dbc5d6c0ed 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-base-type.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-base-type.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: %[[#FLOAT32:]] = OpTypeFloat 32
diff --git a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-bitcast-load.ll b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-bitcast-load.ll
index 132f10262432b2..1d846a35a65aac 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-bitcast-load.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-bitcast-load.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#INT8:]] = OpTypeInt 8 0
diff --git a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-kernel-arg-char.ll b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-kernel-arg-char.ll
index d2a65917bfd659..a5e891dae6f11d 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-kernel-arg-char.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-kernel-arg-char.ll
@@ -1,5 +1,5 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#INT8:]] = OpTypeInt 8 0
diff --git a/llvm/test/CodeGen/SPIRV/pointers/global-ptrtoint.ll b/llvm/test/CodeGen/SPIRV/pointers/global-ptrtoint.ll
index d0c64b4353ec68..7982893a0a9135 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/global-ptrtoint.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/global-ptrtoint.ll
@@ -1,9 +1,9 @@
; This test is to check that correct virtual register type is created after ptrtoint.
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpName %[[GlobalValue:.*]] "dev_global"
diff --git a/llvm/test/CodeGen/SPIRV/pointers/global-zeroinitializer.ll b/llvm/test/CodeGen/SPIRV/pointers/global-zeroinitializer.ll
index 679b0e436afc59..74320b36fd597b 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/global-zeroinitializer.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/global-zeroinitializer.ll
@@ -1,7 +1,7 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpName %[[#Var:]] "var"
diff --git a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-builtin-vload-type-discrapency.ll b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-builtin-vload-type-discrapency.ll
index b4948b66aed86d..e0e4276bc876ab 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-builtin-vload-type-discrapency.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-builtin-vload-type-discrapency.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#INT8:]] = OpTypeInt 8 0
diff --git a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-addressspace.ll b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-addressspace.ll
index a3a730ac67e782..2665923cc4e708 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-addressspace.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-addressspace.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#INT:]] = OpTypeInt 32 0
diff --git a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-bitcast-to-generic.ll b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-bitcast-to-generic.ll
index b74a3449980d97..c61902831acf3f 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-bitcast-to-generic.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-bitcast-to-generic.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#IMAGE:]] = OpTypeImage %2 2D 0 0 0 0 Unknown ReadOnly
diff --git a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-metadata.ll b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-metadata.ll
index a513d103970663..bc6b99e01ff212 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-metadata.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-metadata.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
define spir_kernel void @test(ptr addrspace(1) %srcimg) {
diff --git a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type.ll b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type.ll
index b8f205a68e5616..e246dac1f5abb9 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#FLOAT32:]] = OpTypeFloat 32
diff --git a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-i8-default-element-type.ll b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-i8-default-element-type.ll
index 55bddfdad699b2..f4c0ca3c46599c 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-i8-default-element-type.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-i8-default-element-type.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#CHAR:]] = OpTypeInt 8
diff --git a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-no-bitcast.ll b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-no-bitcast.ll
index 0d2a832c496b1b..f8af9ef763e156 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-no-bitcast.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-no-bitcast.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#CHAR:]] = OpTypeInt 8
diff --git a/llvm/test/CodeGen/SPIRV/pointers/load-addressspace.ll b/llvm/test/CodeGen/SPIRV/pointers/load-addressspace.ll
index 1667abc51be9fc..b3c68d22f9bdd4 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/load-addressspace.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/load-addressspace.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: %[[#INT8:]] = OpTypeInt 8 0
diff --git a/llvm/test/CodeGen/SPIRV/pointers/nested-struct-opaque-pointers.ll b/llvm/test/CodeGen/SPIRV/pointers/nested-struct-opaque-pointers.ll
index 77b895c7762fba..2094f71f60531f 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/nested-struct-opaque-pointers.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/nested-struct-opaque-pointers.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-NOT: OpTypeInt 8 0
diff --git a/llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byref.ll b/llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byref.ll
index 639906af3a952f..043af4b5708b0c 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byref.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byref.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
target triple = "spirv64-unknown-unknown"
diff --git a/llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byval.ll b/llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byval.ll
index 6b684bf41bbb09..5219be2d4e231a 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byval.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byval.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#VOID:]] = OpTypeVoid
diff --git a/llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-i8-ptr-as-value-operand.ll b/llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-i8-ptr-as-value-operand.ll
index 5adaf6f65688df..463cc7098b0f3a 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-i8-ptr-as-value-operand.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-i8-ptr-as-value-operand.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#CHAR:]] = OpTypeInt 8
diff --git a/llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-ptr-as-value-operand.ll b/llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-ptr-as-value-operand.ll
index e7ce3ef621e83a..f0821fc0c03124 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-ptr-as-value-operand.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-ptr-as-value-operand.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
define spir_kernel void @foo(ptr addrspace(1) %arg) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !4 {
diff --git a/llvm/test/CodeGen/SPIRV/pointers/store-operand-ptr-to-struct.ll b/llvm/test/CodeGen/SPIRV/pointers/store-operand-ptr-to-struct.ll
index 3a0d65e1e95f19..0a8321266eee1d 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/store-operand-ptr-to-struct.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/store-operand-ptr-to-struct.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; TODO: OpFunctionParameter should be a pointer of struct base type.
diff --git a/llvm/test/CodeGen/SPIRV/pointers/struct-opaque-pointers.ll b/llvm/test/CodeGen/SPIRV/pointers/struct-opaque-pointers.ll
index 6d4913f802c289..03ecf5e8d839a1 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/struct-opaque-pointers.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/struct-opaque-pointers.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: %[[TyInt64:.*]] = OpTypeInt 64 0
diff --git a/llvm/test/CodeGen/SPIRV/pointers/two-bitcast-or-param-users.ll b/llvm/test/CodeGen/SPIRV/pointers/two-bitcast-or-param-users.ll
index 23c3faaf88151f..d3b63ec9e1094c 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/two-bitcast-or-param-users.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/two-bitcast-or-param-users.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#INT:]] = OpTypeInt 32
diff --git a/llvm/test/CodeGen/SPIRV/pointers/two-subsequent-bitcasts.ll b/llvm/test/CodeGen/SPIRV/pointers/two-subsequent-bitcasts.ll
index 83234e3986c84f..8c01df44563efe 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/two-subsequent-bitcasts.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/two-subsequent-bitcasts.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#float:]] = OpTypeFloat 32
diff --git a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-args-rev.ll b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-args-rev.ll
index ae7fb99907b131..80b0b682266e1d 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-args-rev.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-args-rev.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV-DAG: OpName %[[FooArg:.*]] "known_type_ptr"
diff --git a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-args.ll b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-args.ll
index ee411f26466027..b25fe969b0579a 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-args.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-args.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV-DAG: OpName %[[FooArg:.*]] "unknown_type_ptr"
diff --git a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-chain.ll b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-chain.ll
index f060a97a57296b..dbc88cd1a78592 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-chain.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-chain.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV-DAG: OpName %[[ArgCum:.*]] "_arg_cum"
diff --git a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-complex.ll b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-complex.ll
index ea7a22c31d0e85..4802766ea2145b 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-complex.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-complex.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV-DAG: %[[Long:.*]] = OpTypeInt 32 0
diff --git a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-rev.ll b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-rev.ll
index 76769ab8743082..042909c291d139 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-rev.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-rev.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV-DAG: OpName %[[FooArg:.*]] "known_type_ptr"
diff --git a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call.ll b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call.ll
index 8cbf360a2e38d4..c329f05be7627c 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV-DAG: OpName %[[FooArg:.*]] "known_type_ptr"
diff --git a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-call-no-bitcast.ll b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-call-no-bitcast.ll
index edb31ffeee8e86..101116f4378114 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-call-no-bitcast.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-call-no-bitcast.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV-DAG: OpName %[[Foo:.*]] "foo"
diff --git a/llvm/test/CodeGen/SPIRV/pointers/typeof-ptr-int.ll b/llvm/test/CodeGen/SPIRV/pointers/typeof-ptr-int.ll
index f144418cf54259..a6921a01d5d026 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/typeof-ptr-int.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/typeof-ptr-int.ll
@@ -1,7 +1,7 @@
; This test is to check that two functions have different SPIR-V type
; definitions, even though their LLVM function types are identical.
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: OpName %[[Fun32:.*]] "tp_arg_i32"
diff --git a/llvm/test/CodeGen/SPIRV/pointers/variables-storage-class.ll b/llvm/test/CodeGen/SPIRV/pointers/variables-storage-class.ll
index 034feed72dc7bc..2d4c805ac9df15 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/variables-storage-class.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/variables-storage-class.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
@Ptr = addrspace(1) global ptr addrspace(1) null
>From 3b0540cd78182352dd39ba824125bbc7d0959f6d Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Tue, 20 Aug 2024 11:43:18 -0700
Subject: [PATCH 12/14] update tests with '-verify-machineinstrs'
---
llvm/test/CodeGen/SPIRV/constant/global-constants.ll | 2 +-
llvm/test/CodeGen/SPIRV/constant/local-aggregate-constant.ll | 2 +-
llvm/test/CodeGen/SPIRV/constant/local-bool-constants.ll | 2 +-
.../CodeGen/SPIRV/constant/local-float-point-constants.ll | 2 +-
llvm/test/CodeGen/SPIRV/constant/local-integers-constants.ll | 2 +-
llvm/test/CodeGen/SPIRV/constant/local-null-constants.ll | 2 +-
.../CodeGen/SPIRV/constant/local-vector-matrix-constants.ll | 2 +-
.../extensions/SPV_INTEL_arbitrary_precision_integers.ll | 2 +-
.../extensions/SPV_INTEL_bfloat16_conversion/bfloat16-conv.ll | 2 +-
.../decorate-prefetch-w-cache-controls.ll | 2 +-
.../extensions/SPV_INTEL_function_pointers/fp_two_calls.ll | 2 +-
.../global-var-decorations.ll | 2 +-
.../global-var-host-access.ll | 2 +-
llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_optnone.ll | 4 ++--
.../extensions/SPV_INTEL_subgroups/builtin-op-wrappers.ll | 2 +-
.../extensions/SPV_INTEL_subgroups/cl_intel_sub_groups.ll | 2 +-
.../SPV_INTEL_variable_length_array/builtin_alloca.ll | 2 +-
.../extensions/SPV_INTEL_variable_length_array/vararr.ll | 2 +-
.../SPV_INTEL_variable_length_array/vararr_spec_const.ll | 2 +-
.../test/CodeGen/SPIRV/extensions/SPV_KHR_bit_instructions.ll | 4 ++--
.../SPIRV/extensions/SPV_KHR_no_integer_wrap_decoration.ll | 2 +-
.../SPIRV/extensions/SPV_KHR_shader_clock/shader_clock.ll | 2 +-
.../extensions/SPV_KHR_subgroup_rotate/subgroup-rotate.ll | 2 +-
.../uniform-group-instructions.ll | 2 +-
.../CodeGen/SPIRV/extensions/enable-all-extensions-but-one.ll | 2 +-
llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions.ll | 2 +-
26 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/llvm/test/CodeGen/SPIRV/constant/global-constants.ll b/llvm/test/CodeGen/SPIRV/constant/global-constants.ll
index 74e28cbe7acb17..43dbed8b044b5e 100644
--- a/llvm/test/CodeGen/SPIRV/constant/global-constants.ll
+++ b/llvm/test/CodeGen/SPIRV/constant/global-constants.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
@global = addrspace(1) constant i32 1 ; OpenCL global memory
diff --git a/llvm/test/CodeGen/SPIRV/constant/local-aggregate-constant.ll b/llvm/test/CodeGen/SPIRV/constant/local-aggregate-constant.ll
index 355bd32e261a17..447cad6528dd42 100644
--- a/llvm/test/CodeGen/SPIRV/constant/local-aggregate-constant.ll
+++ b/llvm/test/CodeGen/SPIRV/constant/local-aggregate-constant.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
%aggregate = type { i8, i32 }
diff --git a/llvm/test/CodeGen/SPIRV/constant/local-bool-constants.ll b/llvm/test/CodeGen/SPIRV/constant/local-bool-constants.ll
index 73312c1e933727..c98f253aedfb4a 100644
--- a/llvm/test/CodeGen/SPIRV/constant/local-bool-constants.ll
+++ b/llvm/test/CodeGen/SPIRV/constant/local-bool-constants.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
define i1 @getConstantTrue() {
ret i1 true
diff --git a/llvm/test/CodeGen/SPIRV/constant/local-float-point-constants.ll b/llvm/test/CodeGen/SPIRV/constant/local-float-point-constants.ll
index 1bb795f14ab00a..5764e956342227 100644
--- a/llvm/test/CodeGen/SPIRV/constant/local-float-point-constants.ll
+++ b/llvm/test/CodeGen/SPIRV/constant/local-float-point-constants.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
define half @getConstantFP16() {
ret half 0x3ff1340000000000 ; 0x3c4d represented as double.
diff --git a/llvm/test/CodeGen/SPIRV/constant/local-integers-constants.ll b/llvm/test/CodeGen/SPIRV/constant/local-integers-constants.ll
index 5cfc0d2e9dc8f4..a7c04fa00e752b 100644
--- a/llvm/test/CodeGen/SPIRV/constant/local-integers-constants.ll
+++ b/llvm/test/CodeGen/SPIRV/constant/local-integers-constants.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
define i8 @getConstantI8() {
ret i8 2
diff --git a/llvm/test/CodeGen/SPIRV/constant/local-null-constants.ll b/llvm/test/CodeGen/SPIRV/constant/local-null-constants.ll
index 8009f488f6dd2f..210679021532a3 100644
--- a/llvm/test/CodeGen/SPIRV/constant/local-null-constants.ll
+++ b/llvm/test/CodeGen/SPIRV/constant/local-null-constants.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
;; OpenCL global memory
define ptr addrspace(1) @getConstant1() {
diff --git a/llvm/test/CodeGen/SPIRV/constant/local-vector-matrix-constants.ll b/llvm/test/CodeGen/SPIRV/constant/local-vector-matrix-constants.ll
index 0e35588221a498..981ab08dbef338 100644
--- a/llvm/test/CodeGen/SPIRV/constant/local-vector-matrix-constants.ll
+++ b/llvm/test/CodeGen/SPIRV/constant/local-vector-matrix-constants.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
;; TODO: Add test for matrix. But how are they represented in LLVM IR?
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_integers.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_integers.ll
index f49367c50e0ef0..41d4b58ed1157e 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_integers.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_integers.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_integers %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_integers %s -o - | FileCheck %s
define i6 @getConstantI6() {
ret i6 2
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_bfloat16_conversion/bfloat16-conv.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_bfloat16_conversion/bfloat16-conv.ll
index 91fa340e461121..7bc6f5b9d56f5a 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_bfloat16_conversion/bfloat16-conv.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_bfloat16_conversion/bfloat16-conv.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_bfloat16_conversion %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_bfloat16_conversion %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_bfloat16_conversion %s -o - -filetype=obj | spirv-val %}
; RUN: not llc -O0 -mtriple=spirv32-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cache_controls/decorate-prefetch-w-cache-controls.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cache_controls/decorate-prefetch-w-cache-controls.ll
index 9a13b720f61f74..4428a2049f9cef 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cache_controls/decorate-prefetch-w-cache-controls.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cache_controls/decorate-prefetch-w-cache-controls.ll
@@ -1,6 +1,6 @@
; Adapted from https://github.com/KhronosGroup/SPIRV-LLVM-Translator/tree/main/test/extensions/INTEL/SPV_INTEL_cache_controls
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_cache_controls %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_cache_controls %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV
; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_cache_controls %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV: Capability CacheControlsINTEL
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_two_calls.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_two_calls.ll
index b7fecefe9a5812..c5a2918f92c29e 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_two_calls.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_two_calls.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s
; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: OpCapability Int8
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_global_variable_fpga_decorations/global-var-decorations.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_global_variable_fpga_decorations/global-var-decorations.ll
index 40008873bf19bf..ece9502450032d 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_global_variable_fpga_decorations/global-var-decorations.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_global_variable_fpga_decorations/global-var-decorations.ll
@@ -1,6 +1,6 @@
; Adapted from https://github.com/KhronosGroup/SPIRV-LLVM-Translator/tree/main/test/extensions/INTEL/SPV_INTEL_global_variable_fpga_decorations
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_global_variable_fpga_decorations %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_global_variable_fpga_decorations %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV
; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_global_variable_fpga_decorations %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV: Capability GlobalVariableFPGADecorationsINTEL
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_global_variable_host_access/global-var-host-access.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_global_variable_host_access/global-var-host-access.ll
index 1397435efb2d4f..4256d3d0ce7cf0 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_global_variable_host_access/global-var-host-access.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_global_variable_host_access/global-var-host-access.ll
@@ -1,6 +1,6 @@
; Adapted from https://github.com/KhronosGroup/SPIRV-LLVM-Translator/tree/main/test/extensions/INTEL/SPV_INTEL_global_variable_host_access
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_global_variable_host_access,+SPV_INTEL_global_variable_fpga_decorations %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_global_variable_host_access,+SPV_INTEL_global_variable_fpga_decorations %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV
; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_global_variable_host_access,+SPV_INTEL_global_variable_fpga_decorations %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV-DAG: Capability GlobalVariableHostAccessINTEL
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_optnone.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_optnone.ll
index a611be8eb6ee79..1744ec96804019 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_optnone.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_optnone.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_optnone %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-EXTENSION
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NO-EXTENSION
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_optnone %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-EXTENSION
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NO-EXTENSION
; CHECK-EXTENSION: OpCapability OptNoneINTEL
; CHECK-EXTENSION: OpExtension "SPV_INTEL_optnone"
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroups/builtin-op-wrappers.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroups/builtin-op-wrappers.ll
index b15a788be7d715..8c145a463ed274 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroups/builtin-op-wrappers.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroups/builtin-op-wrappers.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_subgroups %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_subgroups %s -o - | FileCheck %s
; CHECK-DAG: Capability SubgroupShuffleINTEL
; CHECK-DAG: Capability SubgroupBufferBlockIOINTEL
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroups/cl_intel_sub_groups.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroups/cl_intel_sub_groups.ll
index df17ec435ad377..9374e154a0239f 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroups/cl_intel_sub_groups.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroups/cl_intel_sub_groups.ll
@@ -37,7 +37,7 @@
; RUN: not llc -O0 -mtriple=spirv32-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_subgroups %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_subgroups %s -o - | FileCheck %s
; CHECK-ERROR: LLVM ERROR: intel_sub_group_shuffle: the builtin requires the following SPIR-V extension: SPV_INTEL_subgroups
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/builtin_alloca.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/builtin_alloca.ll
index 4d6173e5b7232e..b3518f044a24fb 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/builtin_alloca.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/builtin_alloca.ll
@@ -23,7 +23,7 @@
; RUN: not llc -O0 -mtriple=spirv64-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_variable_length_array %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_variable_length_array %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_variable_length_array %s -o - -filetype=obj | spirv-val %}
; CHECK-ERROR: LLVM ERROR: array allocation: this instruction requires the following SPIR-V extension: SPV_INTEL_variable_length_array
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr.ll
index 8a54d22a539db1..3668dfcb4af75a 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr.ll
@@ -1,7 +1,7 @@
; Modified from: https://github.com/KhronosGroup/SPIRV-LLVM-Translator/test/extensions/INTEL/SPV_INTEL_variable_length_array/basic.ll
; RUN: not llc -O0 -mtriple=spirv32-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_variable_length_array %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_variable_length_array %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_variable_length_array %s -o - -filetype=obj | spirv-val %}
; CHECK-ERROR: LLVM ERROR: array allocation: this instruction requires the following SPIR-V extension: SPV_INTEL_variable_length_array
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr_spec_const.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr_spec_const.ll
index 7b9f75d74db997..dea04c9a21a1ca 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr_spec_const.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr_spec_const.ll
@@ -1,6 +1,6 @@
; Modified from: https://github.com/KhronosGroup/SPIRV-LLVM-Translator/test/extensions/INTEL/SPV_INTEL_variable_length_array/vla_spec_const.ll
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_variable_length_array %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_variable_length_array %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_variable_length_array %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV: Capability VariableLengthArrayINTEL
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bit_instructions.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bit_instructions.ll
index 100f02faba8575..40e2aff0d755a3 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bit_instructions.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bit_instructions.ll
@@ -1,5 +1,5 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s --spirv-ext=+SPV_KHR_bit_instructions -o - | FileCheck %s --check-prefix=CHECK-EXTENSION
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-NO-EXTENSION
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s --spirv-ext=+SPV_KHR_bit_instructions -o - | FileCheck %s --check-prefix=CHECK-EXTENSION
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-NO-EXTENSION
; CHECK-EXTENSION: OpCapability BitInstructions
; CHECK-EXTENSION-NEXT: OpExtension "SPV_KHR_bit_instructions"
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_no_integer_wrap_decoration.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_no_integer_wrap_decoration.ll
index 0d9ab4ab65ceaa..dac22c0d84c2e1 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_no_integer_wrap_decoration.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_no_integer_wrap_decoration.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_KHR_no_integer_wrap_decoration %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_KHR_no_integer_wrap_decoration %s -o - | FileCheck %s
; CHECK-DAG: OpExtension "SPV_KHR_no_integer_wrap_decoration"
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_shader_clock/shader_clock.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_shader_clock/shader_clock.ll
index e219f61b5c6e34..8ecd0a2b25ebcf 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_shader_clock/shader_clock.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_shader_clock/shader_clock.ll
@@ -1,5 +1,5 @@
; RUN: not llc -O0 -mtriple=spirv64-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_KHR_shader_clock %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_KHR_shader_clock %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_KHR_shader_clock %s -o - -filetype=obj | spirv-val %}
; CHECK-ERROR: LLVM ERROR: clock_read_device: the builtin requires the following SPIR-V extension: SPV_KHR_shader_clock
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_subgroup_rotate/subgroup-rotate.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_subgroup_rotate/subgroup-rotate.ll
index a38c9072ed1bd4..1391fddfcdb369 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_subgroup_rotate/subgroup-rotate.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_subgroup_rotate/subgroup-rotate.ll
@@ -1,5 +1,5 @@
; RUN: not llc -O0 -mtriple=spirv32-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_KHR_subgroup_rotate %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_KHR_subgroup_rotate %s -o - | FileCheck %s
; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_KHR_subgroup_rotate %s -o - -filetype=obj | spirv-val %}
; CHECK-ERROR: LLVM ERROR: OpGroupNonUniformRotateKHR instruction requires the following SPIR-V extension: SPV_KHR_subgroup_rotate
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_uniform_group_instructions/uniform-group-instructions.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_uniform_group_instructions/uniform-group-instructions.ll
index 0de654be8ed7d5..96e74149f44dbb 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_uniform_group_instructions/uniform-group-instructions.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_uniform_group_instructions/uniform-group-instructions.ll
@@ -1,6 +1,6 @@
; RUN: not llc -O0 -mtriple=spirv32-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_KHR_uniform_group_instructions %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_KHR_uniform_group_instructions %s -o - | FileCheck %s
; CHECK-ERROR: LLVM ERROR: __spirv_GroupBitwiseAndKHR: the builtin requires the following SPIR-V extension: SPV_KHR_uniform_group_instructions
diff --git a/llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions-but-one.ll b/llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions-but-one.ll
index 973a5e6f60569f..02d21a1abafa5f 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions-but-one.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions-but-one.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=all,-SPV_INTEL_arbitrary_precision_integers %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=all,-SPV_INTEL_arbitrary_precision_integers %s -o - | FileCheck %s
define i6 @foo() {
%call = tail call i32 @llvm.bitreverse.i32(i32 42)
diff --git a/llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions.ll b/llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions.ll
index a5b979469b931d..f745794e11de13 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=all %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=all %s -o - | FileCheck %s
define i6 @getConstantI6() {
ret i6 2
>From 74992ab4deeee9b8fa3779f10785fc93a3ecd901 Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Tue, 20 Aug 2024 11:45:57 -0700
Subject: [PATCH 13/14] update tests with '-verify-machineinstrs'
---
llvm/test/CodeGen/SPIRV/function/alloca-load-store.ll | 2 +-
llvm/test/CodeGen/SPIRV/function/identity-function.ll | 2 +-
.../CodeGen/SPIRV/function/multiple-anonymous-functions.ll | 2 +-
.../CodeGen/SPIRV/function/trivial-function-definition.ll | 2 +-
.../SPIRV/function/trivial-function-with-attributes.ll | 2 +-
.../test/CodeGen/SPIRV/function/trivial-function-with-call.ll | 2 +-
llvm/test/CodeGen/SPIRV/image/sampler.ll | 2 +-
llvm/test/CodeGen/SPIRV/instructions/atomic-ptr.ll | 4 ++--
llvm/test/CodeGen/SPIRV/instructions/atomic_acqrel.ll | 2 +-
llvm/test/CodeGen/SPIRV/instructions/atomic_seq.ll | 2 +-
llvm/test/CodeGen/SPIRV/instructions/call-complex-function.ll | 2 +-
llvm/test/CodeGen/SPIRV/instructions/call-trivial-function.ll | 2 +-
llvm/test/CodeGen/SPIRV/instructions/fcmp.ll | 2 +-
llvm/test/CodeGen/SPIRV/instructions/float-casts.ll | 2 +-
llvm/test/CodeGen/SPIRV/instructions/float-fast-flags.ll | 2 +-
llvm/test/CodeGen/SPIRV/instructions/icmp.ll | 2 +-
llvm/test/CodeGen/SPIRV/instructions/intrinsics.ll | 2 +-
llvm/test/CodeGen/SPIRV/instructions/nested-composites.ll | 2 +-
.../CodeGen/SPIRV/instructions/scalar-bitwise-operations.ll | 2 +-
.../SPIRV/instructions/scalar-floating-point-arithmetic.ll | 2 +-
.../CodeGen/SPIRV/instructions/scalar-integer-arithmetic.ll | 2 +-
llvm/test/CodeGen/SPIRV/instructions/select-ptr-load.ll | 4 ++--
llvm/test/CodeGen/SPIRV/instructions/select.ll | 4 ++--
.../SPIRV/instructions/undef-nested-composite-store.ll | 2 +-
.../SPIRV/instructions/undef-simple-composite-store.ll | 2 +-
llvm/test/CodeGen/SPIRV/instructions/unreachable.ll | 2 +-
.../CodeGen/SPIRV/instructions/vector-bitwise-operations.ll | 2 +-
.../SPIRV/instructions/vector-floating-point-arithmetic.ll | 2 +-
.../CodeGen/SPIRV/instructions/vector-integer-arithmetic.ll | 2 +-
29 files changed, 32 insertions(+), 32 deletions(-)
diff --git a/llvm/test/CodeGen/SPIRV/function/alloca-load-store.ll b/llvm/test/CodeGen/SPIRV/function/alloca-load-store.ll
index 5c06d65b6b4e61..55ab715feff3dd 100644
--- a/llvm/test/CodeGen/SPIRV/function/alloca-load-store.ll
+++ b/llvm/test/CodeGen/SPIRV/function/alloca-load-store.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName %[[#BAR:]] "bar"
; CHECK-DAG: OpName %[[#FOO:]] "foo"
diff --git a/llvm/test/CodeGen/SPIRV/function/identity-function.ll b/llvm/test/CodeGen/SPIRV/function/identity-function.ll
index 005f1061f4fbb1..0acfa4666dfa09 100644
--- a/llvm/test/CodeGen/SPIRV/function/identity-function.ll
+++ b/llvm/test/CodeGen/SPIRV/function/identity-function.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName %[[#VALUE:]] "value"
; CHECK-DAG: OpName %[[#IDENTITY:]] "identity"
diff --git a/llvm/test/CodeGen/SPIRV/function/multiple-anonymous-functions.ll b/llvm/test/CodeGen/SPIRV/function/multiple-anonymous-functions.ll
index 93bdbe3c1c2117..1b21658af32aa1 100644
--- a/llvm/test/CodeGen/SPIRV/function/multiple-anonymous-functions.ll
+++ b/llvm/test/CodeGen/SPIRV/function/multiple-anonymous-functions.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
;; Types:
; CHECK-DAG: %[[#I32:]] = OpTypeInt 32
diff --git a/llvm/test/CodeGen/SPIRV/function/trivial-function-definition.ll b/llvm/test/CodeGen/SPIRV/function/trivial-function-definition.ll
index cbef5862e54a64..a0e304f175acdd 100644
--- a/llvm/test/CodeGen/SPIRV/function/trivial-function-definition.ll
+++ b/llvm/test/CodeGen/SPIRV/function/trivial-function-definition.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
;; Debug info:
; CHECK: OpName %[[#FOO:]] "foo"
diff --git a/llvm/test/CodeGen/SPIRV/function/trivial-function-with-attributes.ll b/llvm/test/CodeGen/SPIRV/function/trivial-function-with-attributes.ll
index 6c11993bc6dcc6..924163232056af 100644
--- a/llvm/test/CodeGen/SPIRV/function/trivial-function-with-attributes.ll
+++ b/llvm/test/CodeGen/SPIRV/function/trivial-function-with-attributes.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
;; FIXME: Are there any attributes that would make the IR invalid for SPIR-V?
diff --git a/llvm/test/CodeGen/SPIRV/function/trivial-function-with-call.ll b/llvm/test/CodeGen/SPIRV/function/trivial-function-with-call.ll
index 87f45ffb3435a1..d3e2b6b46b8fed 100644
--- a/llvm/test/CodeGen/SPIRV/function/trivial-function-with-call.ll
+++ b/llvm/test/CodeGen/SPIRV/function/trivial-function-with-call.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
;; Debug info:
; CHECK: OpName %[[#FOO:]] "foo"
diff --git a/llvm/test/CodeGen/SPIRV/image/sampler.ll b/llvm/test/CodeGen/SPIRV/image/sampler.ll
index 7b45c95f5ed433..f6ac3510ab6751 100644
--- a/llvm/test/CodeGen/SPIRV/image/sampler.ll
+++ b/llvm/test/CodeGen/SPIRV/image/sampler.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#i32:]] = OpTypeInt 32 0
diff --git a/llvm/test/CodeGen/SPIRV/instructions/atomic-ptr.ll b/llvm/test/CodeGen/SPIRV/instructions/atomic-ptr.ll
index 86e9be15a7c08f..9469d24b20af26 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/atomic-ptr.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/atomic-ptr.ll
@@ -3,8 +3,8 @@
; of spirv-val in this case, because there is a difference of accepted return types
; between atomicrmw and OpAtomicExchange.
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: %[[#LongTy:]] = OpTypeInt 64 0
; CHECK-DAG: %[[#PtrLongTy:]] = OpTypePointer CrossWorkgroup %[[#LongTy]]
diff --git a/llvm/test/CodeGen/SPIRV/instructions/atomic_acqrel.ll b/llvm/test/CodeGen/SPIRV/instructions/atomic_acqrel.ll
index d0c4531a75b65f..07d1a5cf662eca 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/atomic_acqrel.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/atomic_acqrel.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: OpName [[ADD:%.*]] "test_add"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/atomic_seq.ll b/llvm/test/CodeGen/SPIRV/instructions/atomic_seq.ll
index fc1d6dafa1b08f..4078ffe1a10b87 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/atomic_seq.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/atomic_seq.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: OpName [[ADD:%.*]] "test_add"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/call-complex-function.ll b/llvm/test/CodeGen/SPIRV/instructions/call-complex-function.ll
index a5b40b2e72c8da..8b2f14288772ce 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/call-complex-function.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/call-complex-function.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[FUN:%.+]] "fun"
; CHECK-DAG: OpName [[FOO:%.+]] "foo"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/call-trivial-function.ll b/llvm/test/CodeGen/SPIRV/instructions/call-trivial-function.ll
index 6924b7006f8373..3777be6c9ebcf9 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/call-trivial-function.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/call-trivial-function.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[VALUE:%.+]] "value"
; CHECK-DAG: OpName [[IDENTITY:%.+]] "identity"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/fcmp.ll b/llvm/test/CodeGen/SPIRV/instructions/fcmp.ll
index 01d4fc44f83a56..eb3da9e33f1e64 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/fcmp.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/fcmp.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[UEQ:%.*]] "test_ueq"
; CHECK-DAG: OpName [[OEQ:%.*]] "test_oeq"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/float-casts.ll b/llvm/test/CodeGen/SPIRV/instructions/float-casts.ll
index 3b311d841623dd..8833d3bb084a92 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/float-casts.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/float-casts.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[TRUNC32_16:%.*]] "f32tof16"
; CHECK-DAG: OpName [[EXT16_32:%.*]] "f16tof32"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/float-fast-flags.ll b/llvm/test/CodeGen/SPIRV/instructions/float-fast-flags.ll
index 1db5f8bb0ee36f..43336db4e86fa8 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/float-fast-flags.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/float-fast-flags.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; DISABLED-CHECK-DAG: OpName [[FNEG:%.+]] "scalar_fneg"
; CHECK-DAG: OpName [[FADD:%.+]] "test_fadd"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/icmp.ll b/llvm/test/CodeGen/SPIRV/instructions/icmp.ll
index 28c14a99d2a080..bbf947f84c09a7 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/icmp.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/icmp.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[EQ:%.*]] "test_eq"
; CHECK-DAG: OpName [[NE:%.*]] "test_ne"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/intrinsics.ll b/llvm/test/CodeGen/SPIRV/instructions/intrinsics.ll
index fe900d186a9f72..e859dee51a6c3d 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/intrinsics.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/intrinsics.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 %s -mtriple=spirv32-unknown-unknown -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 %s -mtriple=spirv32-unknown-unknown -o - | FileCheck %s
declare float @llvm.fabs.f32(float)
declare float @llvm.rint.f32(float)
diff --git a/llvm/test/CodeGen/SPIRV/instructions/nested-composites.ll b/llvm/test/CodeGen/SPIRV/instructions/nested-composites.ll
index b326a929e783ce..88e992f1834527 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/nested-composites.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/nested-composites.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[FOOBAR:%.+]] "foobar"
; CHECK-DAG: OpName [[PRODUCER:%.+]] "producer"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/scalar-bitwise-operations.ll b/llvm/test/CodeGen/SPIRV/instructions/scalar-bitwise-operations.ll
index 5424fb457bc7d2..81f19b7e8ad64e 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/scalar-bitwise-operations.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/scalar-bitwise-operations.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[SCALAR_SHL:%.+]] "scalar_shl"
; CHECK-DAG: OpName [[SCALAR_LSHR:%.+]] "scalar_lshr"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/scalar-floating-point-arithmetic.ll b/llvm/test/CodeGen/SPIRV/instructions/scalar-floating-point-arithmetic.ll
index 8aa0f05ccfc256..7ce43c2e1b05d2 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/scalar-floating-point-arithmetic.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/scalar-floating-point-arithmetic.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; DISABLED-CHECK-DAG: OpName [[SCALAR_FNEG:%.+]] "scalar_fneg"
; CHECK-DAG: OpName [[SCALAR_FADD:%.+]] "scalar_fadd"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/scalar-integer-arithmetic.ll b/llvm/test/CodeGen/SPIRV/instructions/scalar-integer-arithmetic.ll
index da32feecc6d6db..d222dfa570cf78 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/scalar-integer-arithmetic.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/scalar-integer-arithmetic.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[SCALAR_ADD:%.+]] "scalar_add"
; CHECK-DAG: OpName [[SCALAR_SUB:%.+]] "scalar_sub"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/select-ptr-load.ll b/llvm/test/CodeGen/SPIRV/instructions/select-ptr-load.ll
index 0ff28952f8081a..6e6cd2f68a9713 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/select-ptr-load.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/select-ptr-load.ll
@@ -1,7 +1,7 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV-DAG: %[[Float:.*]] = OpTypeFloat 32
diff --git a/llvm/test/CodeGen/SPIRV/instructions/select.ll b/llvm/test/CodeGen/SPIRV/instructions/select.ll
index 9234b97157d9d8..91d5f12c4b7ba7 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/select.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/select.ll
@@ -1,7 +1,7 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: OpName [[SCALARi32:%.+]] "select_i32"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/undef-nested-composite-store.ll b/llvm/test/CodeGen/SPIRV/instructions/undef-nested-composite-store.ll
index 7425b303f8a87c..98993ef3bced09 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/undef-nested-composite-store.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/undef-nested-composite-store.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: %[[#I32:]] = OpTypeInt 32
; CHECK-DAG: %[[#I16:]] = OpTypeInt 16
diff --git a/llvm/test/CodeGen/SPIRV/instructions/undef-simple-composite-store.ll b/llvm/test/CodeGen/SPIRV/instructions/undef-simple-composite-store.ll
index cb2c89be28f1f1..d03704bf30a81d 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/undef-simple-composite-store.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/undef-simple-composite-store.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: %[[#I32:]] = OpTypeInt 32
; CHECK-DAG: %[[#I16:]] = OpTypeInt 16
diff --git a/llvm/test/CodeGen/SPIRV/instructions/unreachable.ll b/llvm/test/CodeGen/SPIRV/instructions/unreachable.ll
index 0a4538c6de2804..f8949cdf9032ea 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/unreachable.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/unreachable.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK: OpUnreachable
define void @test_unreachable() {
diff --git a/llvm/test/CodeGen/SPIRV/instructions/vector-bitwise-operations.ll b/llvm/test/CodeGen/SPIRV/instructions/vector-bitwise-operations.ll
index 664c42d805f63b..05d8042fe91214 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/vector-bitwise-operations.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/vector-bitwise-operations.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[VECTOR_SHL:%.+]] "vector_shl"
; CHECK-DAG: OpName [[VECTOR_LSHR:%.+]] "vector_lshr"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/vector-floating-point-arithmetic.ll b/llvm/test/CodeGen/SPIRV/instructions/vector-floating-point-arithmetic.ll
index 5513ddac1765ab..1823b4f4cf03b5 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/vector-floating-point-arithmetic.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/vector-floating-point-arithmetic.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[VECTOR_FNEG:%.+]] "vector_fneg"
; CHECK-DAG: OpName [[VECTOR_FADD:%.+]] "vector_fadd"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/vector-integer-arithmetic.ll b/llvm/test/CodeGen/SPIRV/instructions/vector-integer-arithmetic.ll
index 1e61c7ac1d4043..fc4113894dee13 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/vector-integer-arithmetic.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/vector-integer-arithmetic.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[VECTOR_ADD:%.+]] "vector_add"
; CHECK-DAG: OpName [[VECTOR_SUB:%.+]] "vector_sub"
>From 14d7a7250ef9fca400e25019a8f07271d2edf761 Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Tue, 20 Aug 2024 13:29:41 -0700
Subject: [PATCH 14/14] fix instruction selection for pointers; clang-format
---
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 3 ++-
llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp | 6 ------
llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp | 12 +-----------
3 files changed, 3 insertions(+), 18 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 88a005b0013730..66cf163a1a0ac2 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -2451,7 +2451,8 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
if (OrigRetTy && !OrigRetTy->isVoidTy()) {
ReturnType = GR->assignTypeToVReg(OrigRetTy, ReturnRegister, MIRBuilder);
if (!MIRBuilder.getMRI()->getRegClassOrNull(ReturnRegister))
- MIRBuilder.getMRI()->setRegClass(ReturnRegister, GR->getRegClass(ReturnType));
+ MIRBuilder.getMRI()->setRegClass(ReturnRegister,
+ GR->getRegClass(ReturnType));
} else if (OrigRetTy && OrigRetTy->isVoidTy()) {
ReturnRegister = MIRBuilder.getMRI()->createVirtualRegister(&IDRegClass);
MIRBuilder.getMRI()->setType(ReturnRegister, LLT::scalar(64));
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
index 4cc4dbbde8e6a0..8db9808bb87e1d 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
@@ -413,12 +413,6 @@ void SPIRVTargetLowering::finalizeLowering(MachineFunction &MF) const {
validateForwardCalls(STI, MRI, GR, MI);
break;
- case SPIRV::OpIAddS:
- if (GR.isScalarOrVectorOfType(MI.getOperand(1).getReg(),
- SPIRV::OpTypeBool))
- MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpLogicalOr));
- break;
-
// ensure that LLVM IR bitwise instructions result in logical SPIR-V
// instructions when applied to bool type
case SPIRV::OpBitwiseOrS:
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index b35ac7ba74373c..1104b6a7212935 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -311,7 +311,7 @@ void SPIRVInstructionSelector::resetVRegsType(MachineFunction &MF) {
if (RegType.isScalar())
MRI.setType(Reg, LLT::scalar(64));
else if (RegType.isPointer())
- MRI.setType(Reg, LLT::pointer(RegType.getAddressSpace(), 64));
+ MRI.setType(Reg, LLT::pointer(0, 64));
else if (RegType.isVector())
MRI.setType(Reg, LLT::fixed_vector(2, LLT::scalar(64)));
}
@@ -371,16 +371,6 @@ bool SPIRVInstructionSelector::select(MachineInstr &I) {
} else if (I.getNumDefs() == 1) {
// Make all vregs 64 bits (for SPIR-V IDs).
MRI->setType(I.getOperand(0).getReg(), LLT::scalar(64));
-/*
- Register Reg = I.getOperand(0).getReg();
- LLT RegType = MRI->getType(Reg);
- if (RegType.isScalar())
- MRI->setType(Reg, LLT::scalar(64));
- else if (RegType.isPointer())
- MRI->setType(Reg, LLT::pointer(RegType.getAddressSpace(), 64));
- else if (RegType.isVector())
- MRI->setType(Reg, LLT::fixed_vector(2, LLT::scalar(64)));
-*/
}
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
}
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