[llvm] [AArch64][GlobalISel] Legalize 128-bit types for FABS (PR #104753)

[Thorsten Schütt via llvm-commits]

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@@ -8456,6 +8458,21 @@ LegalizerHelper::lowerAbsToCNeg(MachineInstr &MI) {
   return Legalized;
 }
 
+LegalizerHelper::LegalizeResult LegalizerHelper::lowerFAbs(MachineInstr &MI) {
+  Register SrcReg = MI.getOperand(1).getReg();
+  Register DstReg = MI.getOperand(0).getReg();
+
+  LLT Ty = MRI.getType(DstReg);
+
+  // Reset sign bit
+  MIRBuilder.buildAnd(DstReg, SrcReg,
+                      MIRBuilder.buildConstant(
+                          Ty, APInt::getSignedMaxValue(Ty.getSizeInBits())));
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tschuett wrote:

`Ty.getScalarSizeIniBts()` to support vectors? And vector support is not testet.

https://github.com/llvm/llvm-project/pull/104753