[llvm] [RISCV] Decompose LMUL > 1 reverses into LMUL * M1 vrgather.vv (PR #104574)

[Craig Topper via llvm-commits]

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@@ -269,7 +269,8 @@ def SIFIVE_P470 : RISCVProcessorModel<"sifive-p470", SiFiveP400Model,
                                        FeatureUnalignedScalarMem,
                                        FeatureUnalignedVectorMem]),
                                       !listconcat(SiFiveP400TuneFeatures,
-                                                  [TuneNoSinkSplatOperands])>;
+                                                  [TuneNoSinkSplatOperands,
+                                                   TuneOptimizedVectorGather])>;
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topperc wrote:

I looked back over our internal documentation. I think this might still be profitable on these CPUs. There's an additional constant overhead for LMUL>1 even when the indices only read a single source.

https://github.com/llvm/llvm-project/pull/104574