[llvm] [AMDGPU] Correctly insert s_nops for dst forwarding hazard (PR #100276)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 20 10:52:55 PDT 2024
================
@@ -1038,11 +1093,45 @@ int GCNHazardRecognizer::checkInlineAsmHazards(MachineInstr *IA) {
for (const MachineOperand &Op :
llvm::drop_begin(IA->operands(), InlineAsm::MIOp_FirstOperand)) {
if (Op.isReg() && Op.isDef()) {
- WaitStatesNeeded =
- std::max(WaitStatesNeeded, checkVALUHazardsHelper(Op, MRI));
+ if (!TRI.isVectorRegister(MRI, Op.getReg()))
+ continue;
+
+ if (ST.has12DWordStoreHazard()) {
+ WaitStatesNeeded =
+ std::max(WaitStatesNeeded, checkVALUHazardsHelper(Op, MRI));
+ }
}
}
+ if (ST.hasDstSelForwardingHazard()) {
+ const int Shift16DefWaitstates = 1;
+
+ auto IsShift16BitDefFn = [this, &IA](const MachineInstr &MI) {
+ const MachineOperand *Dst = getDstSelForwardingOperand(MI, ST);
+ // Assume inline asm reads the dst
+ if (Dst)
+ return IA->modifiesRegister(Dst->getReg(), &TRI) ||
+ IA->readsRegister(Dst->getReg(), &TRI);
+
+ if (MI.isInlineAsm()) {
+ // If MI is inline asm, assume it has dst forwarding hazard
+ for (auto &Def : MI.all_defs()) {
+ if (IA->modifiesRegister(Def.getReg(), &TRI) ||
+ IA->readsRegister(Def.getReg(), &TRI)) {
+ return true;
+ }
----------------
arsenm wrote:
Not sure why we have readsWritesVirtualRegister, but you have to handle reads and writes separately for physical registers
https://github.com/llvm/llvm-project/pull/100276
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