[llvm] [AMDGPU] Correctly insert s_nops for dst forwarding hazard (PR #100276)

[Jeffrey Byrnes via llvm-commits]

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@@ -1038,11 +1093,45 @@ int GCNHazardRecognizer::checkInlineAsmHazards(MachineInstr *IA) {
   for (const MachineOperand &Op :
        llvm::drop_begin(IA->operands(), InlineAsm::MIOp_FirstOperand)) {
     if (Op.isReg() && Op.isDef()) {
-      WaitStatesNeeded =
-          std::max(WaitStatesNeeded, checkVALUHazardsHelper(Op, MRI));
+      if (!TRI.isVectorRegister(MRI, Op.getReg()))
+        continue;
+
+      if (ST.has12DWordStoreHazard()) {
+        WaitStatesNeeded =
+            std::max(WaitStatesNeeded, checkVALUHazardsHelper(Op, MRI));
+      }
     }
   }
 
+  if (ST.hasDstSelForwardingHazard()) {
+    const int Shift16DefWaitstates = 1;
+
+    auto IsShift16BitDefFn = [this, &IA](const MachineInstr &MI) {
+      const MachineOperand *Dst = getDstSelForwardingOperand(MI, ST);
+      // Assume inline asm reads the dst
+      if (Dst)
+        return IA->modifiesRegister(Dst->getReg(), &TRI) ||
+               IA->readsRegister(Dst->getReg(), &TRI);
+
+      if (MI.isInlineAsm()) {
+        // If MI is inline asm, assume it has dst forwarding hazard
+        for (auto &Def : MI.all_defs()) {
+          if (IA->modifiesRegister(Def.getReg(), &TRI) ||
+              IA->readsRegister(Def.getReg(), &TRI)) {
+            return true;
+          }
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jrbyrnes wrote:

I think part of my confusion is that both of the instructions are inlineasm .. 

In this case, my thinking is that for any def in the first asm instruction, if there is a WAW (modifiesRegister) or RAW (readsRegister) on that reg in the second asm instruction, then assume there's a hazard to resolve.

https://github.com/llvm/llvm-project/pull/100276