[llvm] [ARM] Fix failure to register-allocate CMP_SWAP_64 pseudo-inst (PR #104039)

[Matt Arsenault via llvm-commits]

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@@ -1368,6 +1371,40 @@ void RegAllocFastImpl::findAndSortDefOperandIndexes(const MachineInstr &MI) {
   });
 }
 
+/// Compute \ref UseOperandIndexes so it contains the indices of "use" operands
+/// that are to be allocated. Those are ordered in a way that high-priority
+/// classes are allocated first.
+void RegAllocFastImpl::findAndSortUseOperandIndexes(const MachineInstr &MI) {
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arsenm wrote:

This is actually a big problem for AMDGPU. There are a number of heuristics around that assume the number of registers in a class are distinctly allocatable, and does not consider overlapping cases. We really need a separate query for the number of distinct registers in the class. The priority is still a workaround for not having this information, and requires this subtle maintenance burden of keeping class priorities ordered 

https://github.com/llvm/llvm-project/pull/104039