[llvm] fd83b86 - [InstCombine] Thwart complexity-based canonicalization in test (NFC)

[Nikita Popov via llvm-commits]

Author: Nikita Popov
Date: 2024-08-20T16:09:43+02:00
New Revision: fd83b86bf6da6486d447d67f2c8204aa1a94dfd6

URL: https://github.com/llvm/llvm-project/commit/fd83b86bf6da6486d447d67f2c8204aa1a94dfd6
DIFF: https://github.com/llvm/llvm-project/commit/fd83b86bf6da6486d447d67f2c8204aa1a94dfd6.diff

LOG: [InstCombine] Thwart complexity-based canonicalization in test (NFC)

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/bit-checks.ll

Removed: 
    


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diff  --git a/llvm/test/Transforms/InstCombine/bit-checks.ll b/llvm/test/Transforms/InstCombine/bit-checks.ll
index aea8d3465268a9..c7e1fbb8945493 100644
--- a/llvm/test/Transforms/InstCombine/bit-checks.ll
+++ b/llvm/test/Transforms/InstCombine/bit-checks.ll
@@ -806,14 +806,18 @@ define i32 @main7a_logical(i32 %argc, i32 %argc2, i32 %argc3) {
 }
 
 ; B == (A & B) & D == (A & D)
-define i32 @main7b(i32 %argc, i32 %argc2, i32 %argc3) {
+define i32 @main7b(i32 %argc, i32 %argc2, i32 %argc3x) {
 ; CHECK-LABEL: @main7b(
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
-; CHECK-NEXT:    [[AND_COND:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32
+; CHECK-NEXT:    [[ARGC3:%.*]] = mul i32 [[ARGC3X:%.*]], 42
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]]
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[AND1]], [[ARGC2]]
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[ARGC3]], [[ARGC]]
+; CHECK-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[ARGC3]], [[AND2]]
+; CHECK-NEXT:    [[AND_COND_NOT:%.*]] = or i1 [[TOBOOL]], [[TOBOOL3]]
+; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[AND_COND_NOT]] to i32
 ; CHECK-NEXT:    ret i32 [[STOREMERGE]]
 ;
+  %argc3 = mul i32 %argc3x, 42 ; thwart complexity-based canonicalization
   %and1 = and i32 %argc, %argc2
   %tobool = icmp eq i32 %argc2, %and1
   %and2 = and i32 %argc, %argc3
@@ -843,14 +847,18 @@ define i32 @main7b_logical(i32 %argc, i32 %argc2, i32 %argc3) {
 }
 
 ; B == (B & A) & D == (D & A)
-define i32 @main7c(i32 %argc, i32 %argc2, i32 %argc3) {
+define i32 @main7c(i32 %argc, i32 %argc2, i32 %argc3x) {
 ; CHECK-LABEL: @main7c(
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
-; CHECK-NEXT:    [[AND_COND:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32
+; CHECK-NEXT:    [[ARGC3:%.*]] = mul i32 [[ARGC3X:%.*]], 42
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC:%.*]]
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[AND1]], [[ARGC2]]
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[ARGC3]], [[ARGC]]
+; CHECK-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[ARGC3]], [[AND2]]
+; CHECK-NEXT:    [[AND_COND_NOT:%.*]] = or i1 [[TOBOOL]], [[TOBOOL3]]
+; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[AND_COND_NOT]] to i32
 ; CHECK-NEXT:    ret i32 [[STOREMERGE]]
 ;
+  %argc3 = mul i32 %argc3x, 42 ; thwart complexity-based canonicalization
   %and1 = and i32 %argc2, %argc
   %tobool = icmp eq i32 %argc2, %and1
   %and2 = and i32 %argc3, %argc