[clang] [llvm] [RISCV] Add Hazard3 Core as taped out for RP2350 (PR #102452)

[Sam Elliott via llvm-commits]

lenary wrote:

The commit this was stacked on is merged, and I think we have sorted out naming issues and pinned down the exact cpu configuration, so I think this is ready for review and merge.

https://github.com/llvm/llvm-project/pull/102452