[llvm] [RISCV][MC] Name the vector tuple registers. NFC (PR #102726)

[Brandon Wu via llvm-commits]

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@@ -1008,19 +1008,6 @@ static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
       } else if (RISCV::FPR64RegClass.contains(Reg)) {
         Reg = TRI->getSubReg(Reg, RISCV::sub_32);
         assert(Reg && "Superregister does not exist");
-      } else if (RISCV::VRN2M1RegClass.contains(Reg) ||
-                 RISCV::VRN2M2RegClass.contains(Reg) ||
-                 RISCV::VRN2M4RegClass.contains(Reg) ||
-                 RISCV::VRN3M1RegClass.contains(Reg) ||
-                 RISCV::VRN3M2RegClass.contains(Reg) ||
-                 RISCV::VRN4M1RegClass.contains(Reg) ||
-                 RISCV::VRN4M2RegClass.contains(Reg) ||
-                 RISCV::VRN5M1RegClass.contains(Reg) ||
-                 RISCV::VRN6M1RegClass.contains(Reg) ||
-                 RISCV::VRN7M1RegClass.contains(Reg) ||
-                 RISCV::VRN8M1RegClass.contains(Reg)) {
-        Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
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4vtomat wrote:

No it won't. I think it should, so let me change it back.

https://github.com/llvm/llvm-project/pull/102726