[llvm] [AMDGPU] Correctly insert s_nops for dst forwarding hazard (PR #100276)

[Jeffrey Byrnes via llvm-commits]

================
@@ -1098,35 +1100,35 @@ int GCNHazardRecognizer::checkInlineAsmHazards(MachineInstr *IA) {
         WaitStatesNeeded =
             std::max(WaitStatesNeeded, checkVALUHazardsHelper(Op, MRI));
       }
+    }
+  }
 
-      if (ST.hasDstSelForwardingHazard()) {
-        const int Shift16DefWaitstates = 1;
+  if (ST.hasDstSelForwardingHazard()) {
+    const int Shift16DefWaitstates = 1;
 
-        auto IsShift16BitDefFn = [this, &IA](const MachineInstr &MI) {
-          const MachineOperand *Dst = getDstSelForwardingOperand(MI, ST);
-          // Assume inline asm reads the dst
-          if (Dst)
-            return true;
+    auto IsShift16BitDefFn = [this, &IA](const MachineInstr &MI) {
+      const MachineOperand *Dst = getDstSelForwardingOperand(MI, ST);
+      // Assume inline asm reads the dst
+      if (Dst)
+        return true;
 
-          if (MI.isInlineAsm()) {
-            // If MI is inline asm, assume it has dst forwarding hazard
-            for (auto &Op :
-                 drop_begin(MI.operands(), InlineAsm::MIOp_FirstOperand)) {
-              if (Op.isReg() && IA->modifiesRegister(Op.getReg(), &TRI)) {
-                return true;
-              }
-            }
+      if (MI.isInlineAsm()) {
+        // If MI is inline asm, assume it has dst forwarding hazard
+        for (auto &Op :
+             drop_begin(MI.operands(), InlineAsm::MIOp_FirstOperand)) {
+          if (Op.isReg() && IA->modifiesRegister(Op.getReg(), &TRI)) {
+            return true;
           }
----------------
jrbyrnes wrote:

I think we should at least check all the defs for the inline asm?

Of course, for a typical VALU instruciton, only the destination register will have the forwarded dest hazard, but I'm not sure if we inline asm  has API to query the dest reg?

https://github.com/llvm/llvm-project/pull/100276