[llvm] [Work In Progress][LLVM][AArch64] Enable verifyTargetSDNode for scalable vectors and fix the fallout. (PR #104820)

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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


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git-clang-format --diff 9e318bac5b26245c7be7c007975b7589cfcfd8d3 245d3c6491fdcacd29dbaf632741072e48865803 --extensions cpp -- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 265a425125..1351a78cad 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -22703,16 +22703,20 @@ static SDValue performUzpCombine(SDNode *N, SelectionDAG &DAG,
     return Urshr;
 
   if (Op0.getOpcode() == AArch64ISD::NVCAST &&
-      ResVT.getVectorElementCount() == Op0.getOperand(0).getValueType().getVectorElementCount()*2){
-    if (SDValue Rshrnb = trySimplifySrlAddToRshrnb(Op0->getOperand(0), DAG, Subtarget)) {
+      ResVT.getVectorElementCount() ==
+          Op0.getOperand(0).getValueType().getVectorElementCount() * 2) {
+    if (SDValue Rshrnb =
+            trySimplifySrlAddToRshrnb(Op0->getOperand(0), DAG, Subtarget)) {
       Rshrnb = DAG.getNode(AArch64ISD::NVCAST, DL, ResVT, Rshrnb);
       return DAG.getNode(AArch64ISD::UZP1, DL, ResVT, Rshrnb, Op1);
     }
   }
 
   if (Op1.getOpcode() == AArch64ISD::NVCAST &&
-      ResVT.getVectorElementCount() == Op1.getOperand(0).getValueType().getVectorElementCount()*2){
-    if (SDValue Rshrnb = trySimplifySrlAddToRshrnb(Op1->getOperand(0), DAG, Subtarget)) {
+      ResVT.getVectorElementCount() ==
+          Op1.getOperand(0).getValueType().getVectorElementCount() * 2) {
+    if (SDValue Rshrnb =
+            trySimplifySrlAddToRshrnb(Op1->getOperand(0), DAG, Subtarget)) {
       Rshrnb = DAG.getNode(AArch64ISD::NVCAST, DL, ResVT, Rshrnb);
       return DAG.getNode(AArch64ISD::UZP1, DL, ResVT, Op0, Rshrnb);
     }
@@ -29305,7 +29309,7 @@ void AArch64TargetLowering::verifyTargetSDNode(const SDNode *N) const {
            VT.isInteger() && "Expected integer vectors!");
     assert(OpVT.getSizeInBits() == VT.getSizeInBits() &&
            "Expected vectors of equal size!");
-    assert(OpVT.getVectorElementCount() == VT.getVectorElementCount()*2 &&
+    assert(OpVT.getVectorElementCount() == VT.getVectorElementCount() * 2 &&
            "Expected result vector with half the lanes of its input!");
     break;
   }

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https://github.com/llvm/llvm-project/pull/104820