[llvm] RISC-V: Add fminimumnum and fmaximumnum support (PR #104411)

[Craig Topper via llvm-commits]

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@@ -0,0 +1,734 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=riscv32 --mattr=+f,-d,+zfh < %s | FileCheck %s --check-prefix=RV32FH
+; RUN: llc --mtriple=riscv32 --mattr=+d,+zfh < %s | FileCheck %s --check-prefix=RV32DH
+; RUN: llc --mtriple=riscv64 --mattr=+f,-d,+zfh < %s | FileCheck %s --check-prefix=RV64FH
+; RUN: llc --mtriple=riscv64 --mattr=+d,+zfh < %s | FileCheck %s --check-prefix=RV64DH
+; RUN: llc --mtriple=riscv32 --mattr=+d,-zfh < %s | FileCheck %s --check-prefix=RV32DNH
+; RUN: llc --mtriple=riscv64 --mattr=+d,-zfh < %s | FileCheck %s --check-prefix=RV64DNH
+
+declare float @llvm.maximumnum.f32(float, float)
+declare double @llvm.maximumnum.f64(double, double)
+declare float @llvm.minimumnum.f32(float, float)
+declare double @llvm.minimumnum.f64(double, double)
+
+define float @maximumnum_float(float %x, float %y) {
+; RV32FH-LABEL: maximumnum_float:
+; RV32FH:       # %bb.0:
+; RV32FH-NEXT:    fmax.s fa0, fa0, fa1
+; RV32FH-NEXT:    ret
+;
+; RV32DH-LABEL: maximumnum_float:
+; RV32DH:       # %bb.0:
+; RV32DH-NEXT:    fmax.s fa0, fa0, fa1
+; RV32DH-NEXT:    ret
+;
+; RV64FH-LABEL: maximumnum_float:
+; RV64FH:       # %bb.0:
+; RV64FH-NEXT:    fmax.s fa0, fa0, fa1
+; RV64FH-NEXT:    ret
+;
+; RV64DH-LABEL: maximumnum_float:
+; RV64DH:       # %bb.0:
+; RV64DH-NEXT:    fmax.s fa0, fa0, fa1
+; RV64DH-NEXT:    ret
+;
+; RV32DNH-LABEL: maximumnum_float:
+; RV32DNH:       # %bb.0:
+; RV32DNH-NEXT:    fmax.s fa0, fa0, fa1
+; RV32DNH-NEXT:    ret
+;
+; RV64DNH-LABEL: maximumnum_float:
+; RV64DNH:       # %bb.0:
+; RV64DNH-NEXT:    fmax.s fa0, fa0, fa1
+; RV64DNH-NEXT:    ret
+  %z = call float @llvm.maximumnum.f32(float %x, float %y)
+  ret float %z
+}
+
+define float @maximumnum_float_nsz(float %x, float %y) {
+; RV32FH-LABEL: maximumnum_float_nsz:
+; RV32FH:       # %bb.0:
+; RV32FH-NEXT:    fmax.s fa0, fa0, fa1
+; RV32FH-NEXT:    ret
+;
+; RV32DH-LABEL: maximumnum_float_nsz:
+; RV32DH:       # %bb.0:
+; RV32DH-NEXT:    fmax.s fa0, fa0, fa1
+; RV32DH-NEXT:    ret
+;
+; RV64FH-LABEL: maximumnum_float_nsz:
+; RV64FH:       # %bb.0:
+; RV64FH-NEXT:    fmax.s fa0, fa0, fa1
+; RV64FH-NEXT:    ret
+;
+; RV64DH-LABEL: maximumnum_float_nsz:
+; RV64DH:       # %bb.0:
+; RV64DH-NEXT:    fmax.s fa0, fa0, fa1
+; RV64DH-NEXT:    ret
+;
+; RV32DNH-LABEL: maximumnum_float_nsz:
+; RV32DNH:       # %bb.0:
+; RV32DNH-NEXT:    fmax.s fa0, fa0, fa1
+; RV32DNH-NEXT:    ret
+;
+; RV64DNH-LABEL: maximumnum_float_nsz:
+; RV64DNH:       # %bb.0:
+; RV64DNH-NEXT:    fmax.s fa0, fa0, fa1
+; RV64DNH-NEXT:    ret
+  %z = call nsz float @llvm.maximumnum.f32(float %x, float %y)
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topperc wrote:

Are the fast math flag tests interesting for RISC-V? We do the same thing regardless of the flags right?

https://github.com/llvm/llvm-project/pull/104411