[llvm] AMDGPU: Update live intervals in convertToThreeAddress (PR #104610)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 19 06:28:55 PDT 2024
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/104610
>From 59a075f43dc9d4956670d82ac2e01d63a7d425bd Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Fri, 16 Aug 2024 18:13:40 +0400
Subject: [PATCH 1/3] AMDGPU: Update live intervals in convertToThreeAddress
Fixes #98741
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 37 ++++--
.../test/CodeGen/AMDGPU/gfx10-twoaddr-fma.mir | 113 ++++++++++++++++--
2 files changed, 132 insertions(+), 18 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 6dce41d1605fa4..ca3bb5c82d2204 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -3947,14 +3947,32 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
(ST.getConstantBusLimit(Opc) > 1 || !Src0->isReg() ||
!RI.isSGPRReg(MBB.getParent()->getRegInfo(), Src0->getReg()))) {
MachineInstr *DefMI;
- const auto killDef = [&]() -> void {
+ const auto killDef = [&](SlotIndex NewIdx) -> void {
const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
// The only user is the instruction which will be killed.
Register DefReg = DefMI->getOperand(0).getReg();
+
+ if (LIS) {
+ LiveInterval &DefLI = LIS->getInterval(DefReg);
+ LiveRange::Segment *OldSeg = DefLI.getSegmentContaining(NewIdx);
+
+ if (OldSeg->end == NewIdx.getRegSlot()) {
+ DefLI.removeSegment(OldSeg->start, NewIdx.getRegSlot(), true);
+
+ for (auto &SR : DefLI.subranges()) {
+ LiveRange::Segment *OldSegSR = SR.getSegmentContaining(NewIdx);
+ SR.removeSegment(OldSegSR->start, NewIdx.getRegSlot(), true);
+ }
+
+ DefLI.removeEmptySubRanges();
+ }
+ }
+
if (!MRI.hasOneNonDBGUse(DefReg))
return;
// We cannot just remove the DefMI here, calling pass will crash.
DefMI->setDesc(get(AMDGPU::IMPLICIT_DEF));
+ DefMI->getOperand(0).setIsDead(true);
for (unsigned I = DefMI->getNumOperands() - 1; I != 0; --I)
DefMI->removeOperand(I);
if (LV)
@@ -3976,9 +3994,10 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
.addImm(Imm)
.setMIFlags(MI.getFlags());
updateLiveVariables(LV, MI, *MIB);
+ SlotIndex NewIdx;
if (LIS)
- LIS->ReplaceMachineInstrInMaps(MI, *MIB);
- killDef();
+ NewIdx = LIS->ReplaceMachineInstrInMaps(MI, *MIB);
+ killDef(NewIdx);
return MIB;
}
}
@@ -3996,9 +4015,11 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
.add(*Src2)
.setMIFlags(MI.getFlags());
updateLiveVariables(LV, MI, *MIB);
+
+ SlotIndex NewIdx;
if (LIS)
- LIS->ReplaceMachineInstrInMaps(MI, *MIB);
- killDef();
+ NewIdx = LIS->ReplaceMachineInstrInMaps(MI, *MIB);
+ killDef(NewIdx);
return MIB;
}
}
@@ -4018,10 +4039,12 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
.add(*Src2)
.setMIFlags(MI.getFlags());
updateLiveVariables(LV, MI, *MIB);
+
+ SlotIndex NewIdx;
if (LIS)
- LIS->ReplaceMachineInstrInMaps(MI, *MIB);
+ NewIdx = LIS->ReplaceMachineInstrInMaps(MI, *MIB);
if (DefMI)
- killDef();
+ killDef(NewIdx);
return MIB;
}
}
diff --git a/llvm/test/CodeGen/AMDGPU/gfx10-twoaddr-fma.mir b/llvm/test/CodeGen/AMDGPU/gfx10-twoaddr-fma.mir
index 0f20b8a2f1e29f..e0843c33d23ad4 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx10-twoaddr-fma.mir
+++ b/llvm/test/CodeGen/AMDGPU/gfx10-twoaddr-fma.mir
@@ -1,29 +1,120 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 %s -run-pass twoaddressinstruction -verify-machineinstrs -o - | FileCheck --check-prefixes=GFX10 %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 %s --passes=two-address-instruction -o - | FileCheck --check-prefixes=GFX10 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass liveintervals,twoaddressinstruction -verify-machineinstrs %s -o -
# GFX10-LABEL: name: test_fmamk_reg_imm_f16
-# GFX10: %2:vgpr_32 = IMPLICIT_DEF
+# GFX10: dead %2:vgpr_32 = IMPLICIT_DEF
# GFX10-NOT: V_MOV_B32
# GFX10: V_FMAMK_F16 killed %0.sub0, 1078523331, killed %1, implicit $mode, implicit $exec
---
name: test_fmamk_reg_imm_f16
-registers:
- - { id: 0, class: vreg_64 }
- - { id: 1, class: vgpr_32 }
- - { id: 2, class: vgpr_32 }
- - { id: 3, class: vgpr_32 }
body: |
bb.0:
- %0 = IMPLICIT_DEF
- %1 = COPY %0.sub1
- %2 = V_MOV_B32_e32 1078523331, implicit $exec
- %3 = V_FMAC_F16_e32 killed %0.sub0, %2, killed %1, implicit $mode, implicit $exec
+ %0:vreg_64 = IMPLICIT_DEF
+ %1:vgpr_32 = COPY %0.sub1
+ %2:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec
+ %3:vgpr_32 = V_FMAC_F16_e32 killed %0.sub0, %2, killed %1, implicit $mode, implicit $exec
+
+...
+
+# GFX10-LABEL: name: test_fmamk_reg_imm_f16__imm_is_subreg
+# GFX10: %0:vreg_64 = IMPLICIT_DEF
+# GFX10: %1:vgpr_32 = COPY %0.sub1
+# GFX10: dead undef %2.sub0:vreg_64 = IMPLICIT_DEF
+# GFX10: %3:vgpr_32 = V_FMAMK_F16 killed %0.sub0, 1078523331, killed %1, implicit $mode, implicit $exec
+---
+name: test_fmamk_reg_imm_f16__imm_is_subreg
+body: |
+ bb.0:
+
+ %0:vreg_64 = IMPLICIT_DEF
+ %1:vgpr_32 = COPY %0.sub1
+ undef %2.sub0:vreg_64 = V_MOV_B32_e32 1078523331, implicit $exec
+ %3:vgpr_32 = V_FMAC_F16_e32 killed %0.sub0, %2.sub0, killed %1, implicit $mode, implicit $exec
+
+...
+
+# GFX10-LABEL: name: test_fmamk_reg_imm_f16__imm_is_subreg_fully_defined
+# GFX10: %0:vreg_64 = IMPLICIT_DEF
+# GFX10: %1:vgpr_32 = COPY %0.sub1
+# GFX10: undef %2.sub1:vreg_64 = V_MOV_B32_e32 9999, implicit $exec
+# GFX10: %2.sub0:vreg_64 = V_MOV_B32_e32 1078523331, implicit $exec
+# GFX10: %3:vgpr_32 = V_FMA_F16_gfx9_e64 0, killed %0.sub0, 0, %2.sub0, 0, killed %1, 0, 0, 0, implicit $mode, implicit $e
+---
+name: test_fmamk_reg_imm_f16__imm_is_subreg_fully_defined
+body: |
+ bb.0:
+
+ %0:vreg_64 = IMPLICIT_DEF
+ %1:vgpr_32 = COPY %0.sub1
+ undef %2.sub1 = V_MOV_B32_e32 9999, implicit $exec
+ %2.sub0:vreg_64 = V_MOV_B32_e32 1078523331, implicit $exec
+ %3:vgpr_32 = V_FMAC_F16_e32 killed %0.sub0, %2.sub0, killed %1, implicit $mode, implicit $exec
+
+...
+
+# GFX10-LABEL: name: test_fmamk_reg_imm_f16__use_imm_before_mac
+# GFX10: %0:vreg_64 = IMPLICIT_DEF
+# GFX10: %1:vgpr_32 = COPY %0.sub1
+# GFX10: %2:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec
+# GFX10: S_NOP 0, implicit %2
+# GFX10: %3:vgpr_32 = V_FMAMK_F16 killed %0.sub0, 1078523331, killed %1, implicit $mode, implicit $exec
+---
+name: test_fmamk_reg_imm_f16__use_imm_before_mac
+body: |
+ bb.0:
+
+ %0:vreg_64 = IMPLICIT_DEF
+ %1:vgpr_32 = COPY %0.sub1
+ %2:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec
+ S_NOP 0, implicit %2
+ %3:vgpr_32 = V_FMAC_F16_e32 killed %0.sub0, %2, killed %1, implicit $mode, implicit $exec
+
+...
+
+# GFX10-LABEL: name: test_fmamk_reg_imm_f16__use_imm_after_mac
+# GFX10: %0:vreg_64 = IMPLICIT_DEF
+# GFX10: %1:vgpr_32 = COPY %0.sub1
+# GFX10: %2:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec
+# GFX10: %3:vgpr_32 = V_FMAMK_F16 killed %0.sub0, 1078523331, killed %1, implicit $mode, implicit $exec
+---
+name: test_fmamk_reg_imm_f16__use_imm_after_mac
+body: |
+ bb.0:
+
+ %0:vreg_64 = IMPLICIT_DEF
+ %1:vgpr_32 = COPY %0.sub1
+ %2:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec
+ %3:vgpr_32 = V_FMAC_F16_e32 killed %0.sub0, %2, killed %1, implicit $mode, implicit $exec
+ S_NOP 0, implicit %2
+
+...
+
+# GFX10-LABEL: name: test_fmamk_reg_imm_f16__use_imm_before_after_mac
+# GFX10: %0:vreg_64 = IMPLICIT_DEF
+# GFX10: %1:vgpr_32 = COPY %0.sub1
+# GFX10: %2:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec
+# GFX10: S_NOP 0, implicit %2
+# GFX10: %3:vgpr_32 = V_FMAMK_F16 killed %0.sub0, 1078523331, killed %1, implicit $mode, implicit $exec
+# GFX10: S_NOP 0, implicit %2
+
+---
+name: test_fmamk_reg_imm_f16__use_imm_before_after_mac
+body: |
+ bb.0:
+
+ %0:vreg_64 = IMPLICIT_DEF
+ %1:vgpr_32 = COPY %0.sub1
+ %2:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec
+ S_NOP 0, implicit %2
+ %3:vgpr_32 = V_FMAC_F16_e32 killed %0.sub0, %2, killed %1, implicit $mode, implicit $exec
+ S_NOP 0, implicit %2
...
# GFX10-LABEL: name: test_fmamk_imm_reg_f16
-# GFX10: %2:vgpr_32 = IMPLICIT_DEF
+# GFX10: dead %2:vgpr_32 = IMPLICIT_DEF
# GFX10-NOT: V_MOV_B32
# GFX10: V_FMAMK_F16 killed %0.sub0, 1078523331, killed %1, implicit $mode, implicit $exec
---
>From 0cccd5fb327acd41921036403e6e0f504a485f26 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Mon, 19 Aug 2024 17:25:26 +0400
Subject: [PATCH 2/3] Comments
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index ca3bb5c82d2204..fdf1318f1b1afb 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -3955,13 +3955,15 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
if (LIS) {
LiveInterval &DefLI = LIS->getInterval(DefReg);
LiveRange::Segment *OldSeg = DefLI.getSegmentContaining(NewIdx);
+ assert(OldSeg && "segment not found for instruction in LiveInterval");
if (OldSeg->end == NewIdx.getRegSlot()) {
- DefLI.removeSegment(OldSeg->start, NewIdx.getRegSlot(), true);
+ DefLI.removeSegment(*OldSeg, true);
for (auto &SR : DefLI.subranges()) {
LiveRange::Segment *OldSegSR = SR.getSegmentContaining(NewIdx);
- SR.removeSegment(OldSegSR->start, NewIdx.getRegSlot(), true);
+ if (OldSegSR->end == NewIdx.getRegSlot())
+ SR.removeSegment(*OldSegSR, true);
}
DefLI.removeEmptySubRanges();
>From 5b1d89754e8c5370321cf2845e638e8c82f8df22 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Mon, 19 Aug 2024 17:28:27 +0400
Subject: [PATCH 3/3] Rename variable
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index fdf1318f1b1afb..9b759d569adcb3 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -3947,22 +3947,22 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
(ST.getConstantBusLimit(Opc) > 1 || !Src0->isReg() ||
!RI.isSGPRReg(MBB.getParent()->getRegInfo(), Src0->getReg()))) {
MachineInstr *DefMI;
- const auto killDef = [&](SlotIndex NewIdx) -> void {
+ const auto killDef = [&](SlotIndex OldDefIdx) -> void {
const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
// The only user is the instruction which will be killed.
Register DefReg = DefMI->getOperand(0).getReg();
if (LIS) {
LiveInterval &DefLI = LIS->getInterval(DefReg);
- LiveRange::Segment *OldSeg = DefLI.getSegmentContaining(NewIdx);
+ LiveRange::Segment *OldSeg = DefLI.getSegmentContaining(OldDefIdx);
assert(OldSeg && "segment not found for instruction in LiveInterval");
- if (OldSeg->end == NewIdx.getRegSlot()) {
+ if (OldSeg->end == OldDefIdx.getRegSlot()) {
DefLI.removeSegment(*OldSeg, true);
for (auto &SR : DefLI.subranges()) {
- LiveRange::Segment *OldSegSR = SR.getSegmentContaining(NewIdx);
- if (OldSegSR->end == NewIdx.getRegSlot())
+ LiveRange::Segment *OldSegSR = SR.getSegmentContaining(OldDefIdx);
+ if (OldSegSR->end == OldDefIdx.getRegSlot())
SR.removeSegment(*OldSegSR, true);
}
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