[llvm] [DAG] Add select_cc -> abd folds (PR #102137)
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llvm-commits at lists.llvm.org
Mon Aug 19 06:12:04 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Simon Pilgrim (RKSimon)
<details>
<summary>Changes</summary>
Fixes #<!-- -->100810
---
Patch is 51.01 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/102137.diff
13 Files Affected:
- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+2)
- (modified) llvm/test/CodeGen/AArch64/abds-neg.ll (+7-7)
- (modified) llvm/test/CodeGen/AArch64/abds.ll (+7-9)
- (modified) llvm/test/CodeGen/AArch64/abdu-neg.ll (+9-9)
- (modified) llvm/test/CodeGen/AArch64/abdu.ll (+7-9)
- (modified) llvm/test/CodeGen/AMDGPU/sad.ll (+8-13)
- (modified) llvm/test/CodeGen/RISCV/abds-neg.ll (+138-123)
- (modified) llvm/test/CodeGen/RISCV/abds.ll (+55-77)
- (modified) llvm/test/CodeGen/RISCV/abdu-neg.ll (+186-169)
- (modified) llvm/test/CodeGen/RISCV/abdu.ll (+65-58)
- (modified) llvm/test/CodeGen/X86/abds-neg.ll (+10-11)
- (modified) llvm/test/CodeGen/X86/abds.ll (+25-35)
- (modified) llvm/test/CodeGen/X86/abdu.ll (+8-12)
``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 80fdedcf9c6259..4180dcc8a720d5 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -27919,6 +27919,8 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
return S;
if (SDValue S = PerformUMinFpToSatCombine(N0, N1, N2, N3, CC, DAG))
return S;
+ if (SDValue ABD = foldSelectToABD(N0, N1, N2, N3, CC, DL))
+ return ABD;
return SDValue();
}
diff --git a/llvm/test/CodeGen/AArch64/abds-neg.ll b/llvm/test/CodeGen/AArch64/abds-neg.ll
index 8c9c9f7188d4dc..74e325d3bc4c2b 100644
--- a/llvm/test/CodeGen/AArch64/abds-neg.ll
+++ b/llvm/test/CodeGen/AArch64/abds-neg.ll
@@ -377,7 +377,7 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x1, x0
; CHECK-NEXT: subs x9, x0, x1
-; CHECK-NEXT: csel x0, x8, x9, lt
+; CHECK-NEXT: csel x0, x9, x8, gt
; CHECK-NEXT: ret
%cmp = icmp slt i64 %a, %b
%ab = sub i64 %a, %b
@@ -389,12 +389,12 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
; CHECK-LABEL: abd_cmp_i128:
; CHECK: // %bb.0:
-; CHECK-NEXT: cmp x0, x2
-; CHECK-NEXT: sbc x8, x1, x3
-; CHECK-NEXT: subs x9, x2, x0
-; CHECK-NEXT: sbc x10, x3, x1
-; CHECK-NEXT: subs x11, x0, x2
-; CHECK-NEXT: sbcs xzr, x1, x3
+; CHECK-NEXT: cmp x2, x0
+; CHECK-NEXT: sbc x8, x3, x1
+; CHECK-NEXT: subs x9, x0, x2
+; CHECK-NEXT: sbc x10, x1, x3
+; CHECK-NEXT: subs x11, x2, x0
+; CHECK-NEXT: sbcs xzr, x3, x1
; CHECK-NEXT: csel x0, x9, x11, lt
; CHECK-NEXT: csel x1, x10, x8, lt
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/abds.ll b/llvm/test/CodeGen/AArch64/abds.ll
index d861ee64b99514..01d1a438c6856a 100644
--- a/llvm/test/CodeGen/AArch64/abds.ll
+++ b/llvm/test/CodeGen/AArch64/abds.ll
@@ -301,10 +301,9 @@ define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: abd_cmp_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: sxtb w8, w0
-; CHECK-NEXT: sub w9, w0, w1
-; CHECK-NEXT: sub w10, w1, w0
-; CHECK-NEXT: cmp w8, w1, sxtb
-; CHECK-NEXT: csel w0, w9, w10, gt
+; CHECK-NEXT: sub w8, w8, w1, sxtb
+; CHECK-NEXT: cmp w8, #0
+; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%cmp = icmp sgt i8 %a, %b
%ab = sub i8 %a, %b
@@ -317,10 +316,9 @@ define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_cmp_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: sxth w8, w0
-; CHECK-NEXT: sub w9, w0, w1
-; CHECK-NEXT: sub w10, w1, w0
-; CHECK-NEXT: cmp w8, w1, sxth
-; CHECK-NEXT: csel w0, w9, w10, ge
+; CHECK-NEXT: sub w8, w8, w1, sxth
+; CHECK-NEXT: cmp w8, #0
+; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%cmp = icmp sge i16 %a, %b
%ab = sub i16 %a, %b
@@ -334,7 +332,7 @@ define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w1, w0
; CHECK-NEXT: subs w9, w0, w1
-; CHECK-NEXT: csel w0, w8, w9, lt
+; CHECK-NEXT: csel w0, w9, w8, gt
; CHECK-NEXT: ret
%cmp = icmp slt i32 %a, %b
%ab = sub i32 %a, %b
diff --git a/llvm/test/CodeGen/AArch64/abdu-neg.ll b/llvm/test/CodeGen/AArch64/abdu-neg.ll
index 1613cbce4b8c8a..b148a29a72976c 100644
--- a/llvm/test/CodeGen/AArch64/abdu-neg.ll
+++ b/llvm/test/CodeGen/AArch64/abdu-neg.ll
@@ -379,7 +379,7 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x1, x0
; CHECK-NEXT: subs x9, x0, x1
-; CHECK-NEXT: csel x0, x8, x9, lo
+; CHECK-NEXT: csel x0, x9, x8, hi
; CHECK-NEXT: ret
%cmp = icmp ult i64 %a, %b
%ab = sub i64 %a, %b
@@ -391,14 +391,14 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
; CHECK-LABEL: abd_cmp_i128:
; CHECK: // %bb.0:
-; CHECK-NEXT: cmp x0, x2
-; CHECK-NEXT: sbc x8, x1, x3
-; CHECK-NEXT: subs x9, x2, x0
-; CHECK-NEXT: sbc x10, x3, x1
-; CHECK-NEXT: subs x11, x0, x2
-; CHECK-NEXT: sbcs xzr, x1, x3
-; CHECK-NEXT: csel x0, x9, x11, lo
-; CHECK-NEXT: csel x1, x10, x8, lo
+; CHECK-NEXT: subs x8, x0, x2
+; CHECK-NEXT: sbcs x9, x1, x3
+; CHECK-NEXT: cset w10, lo
+; CHECK-NEXT: sbfx x10, x10, #0, #1
+; CHECK-NEXT: eor x8, x8, x10
+; CHECK-NEXT: eor x9, x9, x10
+; CHECK-NEXT: subs x0, x8, x10
+; CHECK-NEXT: sbc x1, x9, x10
; CHECK-NEXT: ret
%cmp = icmp ult i128 %a, %b
%ab = sub i128 %a, %b
diff --git a/llvm/test/CodeGen/AArch64/abdu.ll b/llvm/test/CodeGen/AArch64/abdu.ll
index 2baa4f0ca43a7a..22d41dfb85a629 100644
--- a/llvm/test/CodeGen/AArch64/abdu.ll
+++ b/llvm/test/CodeGen/AArch64/abdu.ll
@@ -301,10 +301,9 @@ define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: abd_cmp_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xff
-; CHECK-NEXT: sub w9, w0, w1
-; CHECK-NEXT: sub w10, w1, w0
-; CHECK-NEXT: cmp w8, w1, uxtb
-; CHECK-NEXT: csel w0, w9, w10, hi
+; CHECK-NEXT: sub w8, w8, w1, uxtb
+; CHECK-NEXT: cmp w8, #0
+; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%cmp = icmp ugt i8 %a, %b
%ab = sub i8 %a, %b
@@ -317,10 +316,9 @@ define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_cmp_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xffff
-; CHECK-NEXT: sub w9, w0, w1
-; CHECK-NEXT: sub w10, w1, w0
-; CHECK-NEXT: cmp w8, w1, uxth
-; CHECK-NEXT: csel w0, w9, w10, hs
+; CHECK-NEXT: sub w8, w8, w1, uxth
+; CHECK-NEXT: cmp w8, #0
+; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%cmp = icmp uge i16 %a, %b
%ab = sub i16 %a, %b
@@ -334,7 +332,7 @@ define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w1, w0
; CHECK-NEXT: subs w9, w0, w1
-; CHECK-NEXT: csel w0, w8, w9, lo
+; CHECK-NEXT: csel w0, w9, w8, hi
; CHECK-NEXT: ret
%cmp = icmp ult i32 %a, %b
%ab = sub i32 %a, %b
diff --git a/llvm/test/CodeGen/AMDGPU/sad.ll b/llvm/test/CodeGen/AMDGPU/sad.ll
index e4309a29193637..c2132cf907fdb2 100644
--- a/llvm/test/CodeGen/AMDGPU/sad.ll
+++ b/llvm/test/CodeGen/AMDGPU/sad.ll
@@ -258,10 +258,9 @@ define amdgpu_kernel void @v_sad_u32_multi_use_select_pat2(ptr addrspace(1) %out
; GCN-NEXT: s_add_u32 s16, s16, s13
; GCN-NEXT: s_addc_u32 s17, s17, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_sub_i32 s3, s0, s1
-; GCN-NEXT: s_sub_i32 s6, s1, s0
-; GCN-NEXT: s_cmp_gt_u32 s0, s1
-; GCN-NEXT: s_cselect_b32 s0, s3, s6
+; GCN-NEXT: s_min_u32 s3, s0, s1
+; GCN-NEXT: s_max_u32 s0, s0, s1
+; GCN-NEXT: s_sub_i32 s0, s0, s3
; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: v_mov_b32_e32 v2, s0
; GCN-NEXT: s_add_i32 s0, s0, s2
@@ -477,18 +476,14 @@ define amdgpu_kernel void @s_sad_u32_i8_pat2(ptr addrspace(1) %out, i8 zeroext %
; GCN-NEXT: s_load_dword s2, s[6:7], 0x2
; GCN-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_lshr_b32 s4, s2, 8
; GCN-NEXT: s_and_b32 s3, s2, 0xff
-; GCN-NEXT: s_bfe_u32 s5, s2, 0x80008
-; GCN-NEXT: s_lshr_b32 s6, s2, 16
-; GCN-NEXT: s_sub_i32 s7, s2, s4
-; GCN-NEXT: s_sub_i32 s2, s4, s2
-; GCN-NEXT: s_cmp_gt_u32 s3, s5
-; GCN-NEXT: s_cselect_b32 s2, s7, s2
-; GCN-NEXT: s_add_i32 s2, s2, s6
+; GCN-NEXT: s_bfe_u32 s4, s2, 0x80008
+; GCN-NEXT: s_lshr_b32 s2, s2, 16
+; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: v_mov_b32_e32 v1, s2
+; GCN-NEXT: v_sad_u32 v2, s3, v0, v1
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
-; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: flat_store_byte v[0:1], v2
; GCN-NEXT: s_endpgm
%icmp0 = icmp ugt i8 %a, %b
diff --git a/llvm/test/CodeGen/RISCV/abds-neg.ll b/llvm/test/CodeGen/RISCV/abds-neg.ll
index 9bd28b91dd4c95..058f105e8f7358 100644
--- a/llvm/test/CodeGen/RISCV/abds-neg.ll
+++ b/llvm/test/CodeGen/RISCV/abds-neg.ll
@@ -1791,64 +1791,61 @@ define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: abd_cmp_i64:
; RV32I: # %bb.0:
-; RV32I-NEXT: sltu a4, a0, a2
+; RV32I-NEXT: sltu a4, a2, a0
; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: beq a1, a3, .LBB21_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: slt a5, a1, a3
+; RV32I-NEXT: slt a5, a3, a1
; RV32I-NEXT: .LBB21_2:
; RV32I-NEXT: bnez a5, .LBB21_4
; RV32I-NEXT: # %bb.3:
-; RV32I-NEXT: sub a1, a1, a3
+; RV32I-NEXT: sub a1, a3, a1
; RV32I-NEXT: sub a1, a1, a4
-; RV32I-NEXT: sub a0, a0, a2
+; RV32I-NEXT: sub a0, a2, a0
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB21_4:
-; RV32I-NEXT: sltu a4, a2, a0
-; RV32I-NEXT: sub a1, a3, a1
+; RV32I-NEXT: sltu a4, a0, a2
+; RV32I-NEXT: sub a1, a1, a3
; RV32I-NEXT: sub a1, a1, a4
-; RV32I-NEXT: sub a0, a2, a0
+; RV32I-NEXT: sub a0, a0, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: abd_cmp_i64:
; RV64I: # %bb.0:
-; RV64I-NEXT: blt a0, a1, .LBB21_2
+; RV64I-NEXT: blt a1, a0, .LBB21_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: sub a0, a1, a0
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB21_2:
-; RV64I-NEXT: sub a0, a1, a0
+; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: ret
;
; RV32ZBB-LABEL: abd_cmp_i64:
; RV32ZBB: # %bb.0:
-; RV32ZBB-NEXT: sltu a4, a0, a2
+; RV32ZBB-NEXT: sltu a4, a2, a0
; RV32ZBB-NEXT: mv a5, a4
; RV32ZBB-NEXT: beq a1, a3, .LBB21_2
; RV32ZBB-NEXT: # %bb.1:
-; RV32ZBB-NEXT: slt a5, a1, a3
+; RV32ZBB-NEXT: slt a5, a3, a1
; RV32ZBB-NEXT: .LBB21_2:
; RV32ZBB-NEXT: bnez a5, .LBB21_4
; RV32ZBB-NEXT: # %bb.3:
-; RV32ZBB-NEXT: sub a1, a1, a3
+; RV32ZBB-NEXT: sub a1, a3, a1
; RV32ZBB-NEXT: sub a1, a1, a4
-; RV32ZBB-NEXT: sub a0, a0, a2
+; RV32ZBB-NEXT: sub a0, a2, a0
; RV32ZBB-NEXT: ret
; RV32ZBB-NEXT: .LBB21_4:
-; RV32ZBB-NEXT: sltu a4, a2, a0
-; RV32ZBB-NEXT: sub a1, a3, a1
+; RV32ZBB-NEXT: sltu a4, a0, a2
+; RV32ZBB-NEXT: sub a1, a1, a3
; RV32ZBB-NEXT: sub a1, a1, a4
-; RV32ZBB-NEXT: sub a0, a2, a0
+; RV32ZBB-NEXT: sub a0, a0, a2
; RV32ZBB-NEXT: ret
;
; RV64ZBB-LABEL: abd_cmp_i64:
; RV64ZBB: # %bb.0:
-; RV64ZBB-NEXT: blt a0, a1, .LBB21_2
-; RV64ZBB-NEXT: # %bb.1:
-; RV64ZBB-NEXT: sub a0, a0, a1
-; RV64ZBB-NEXT: ret
-; RV64ZBB-NEXT: .LBB21_2:
-; RV64ZBB-NEXT: sub a0, a1, a0
+; RV64ZBB-NEXT: min a2, a0, a1
+; RV64ZBB-NEXT: max a0, a0, a1
+; RV64ZBB-NEXT: sub a0, a0, a2
; RV64ZBB-NEXT: ret
%cmp = icmp slt i64 %a, %b
%ab = sub i64 %a, %b
@@ -1860,176 +1857,194 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: abd_cmp_i128:
; RV32I: # %bb.0:
-; RV32I-NEXT: lw a3, 0(a2)
-; RV32I-NEXT: lw a4, 0(a1)
-; RV32I-NEXT: lw a5, 4(a2)
-; RV32I-NEXT: lw a6, 8(a2)
-; RV32I-NEXT: lw a7, 8(a1)
-; RV32I-NEXT: lw a2, 12(a2)
+; RV32I-NEXT: lw a3, 0(a1)
+; RV32I-NEXT: lw a5, 0(a2)
+; RV32I-NEXT: lw a4, 4(a1)
+; RV32I-NEXT: lw a6, 8(a1)
+; RV32I-NEXT: lw a7, 8(a2)
; RV32I-NEXT: lw t0, 12(a1)
-; RV32I-NEXT: lw a1, 4(a1)
-; RV32I-NEXT: sltu t1, a7, a6
-; RV32I-NEXT: mv t4, t1
-; RV32I-NEXT: beq t0, a2, .LBB22_2
+; RV32I-NEXT: lw t1, 12(a2)
+; RV32I-NEXT: lw a1, 4(a2)
+; RV32I-NEXT: sltu a2, a7, a6
+; RV32I-NEXT: mv t4, a2
+; RV32I-NEXT: beq t0, t1, .LBB22_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: slt t4, t0, a2
+; RV32I-NEXT: slt t4, t1, t0
; RV32I-NEXT: .LBB22_2:
-; RV32I-NEXT: sltu t2, a4, a3
+; RV32I-NEXT: sltu t2, a5, a3
+; RV32I-NEXT: sltu t5, a1, a4
; RV32I-NEXT: mv t3, t2
-; RV32I-NEXT: beq a1, a5, .LBB22_4
+; RV32I-NEXT: beq a4, a1, .LBB22_4
; RV32I-NEXT: # %bb.3:
-; RV32I-NEXT: sltu t3, a1, a5
+; RV32I-NEXT: mv t3, t5
; RV32I-NEXT: .LBB22_4:
-; RV32I-NEXT: xor t5, t0, a2
-; RV32I-NEXT: xor t6, a7, a6
-; RV32I-NEXT: or t5, t6, t5
-; RV32I-NEXT: mv t6, t3
-; RV32I-NEXT: beqz t5, .LBB22_6
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor t6, t0, t1
+; RV32I-NEXT: xor s0, a6, a7
+; RV32I-NEXT: or t6, s0, t6
+; RV32I-NEXT: beqz t6, .LBB22_6
; RV32I-NEXT: # %bb.5:
-; RV32I-NEXT: mv t6, t4
+; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: .LBB22_6:
-; RV32I-NEXT: sltu t4, a3, a4
-; RV32I-NEXT: mv t5, t4
-; RV32I-NEXT: beq a1, a5, .LBB22_8
+; RV32I-NEXT: mv t4, t2
+; RV32I-NEXT: beq a1, a4, .LBB22_8
; RV32I-NEXT: # %bb.7:
-; RV32I-NEXT: sltu t5, a5, a1
+; RV32I-NEXT: mv t4, t5
; RV32I-NEXT: .LBB22_8:
-; RV32I-NEXT: bnez t6, .LBB22_10
+; RV32I-NEXT: sltu t5, a3, a5
+; RV32I-NEXT: mv t6, t5
+; RV32I-NEXT: beq a4, a1, .LBB22_10
; RV32I-NEXT: # %bb.9:
-; RV32I-NEXT: sub a2, t0, a2
+; RV32I-NEXT: sltu t6, a4, a1
+; RV32I-NEXT: .LBB22_10:
+; RV32I-NEXT: bnez t3, .LBB22_12
+; RV32I-NEXT: # %bb.11:
+; RV32I-NEXT: sub t0, t1, t0
; RV32I-NEXT: sub a6, a7, a6
-; RV32I-NEXT: sub a2, a2, t1
-; RV32I-NEXT: sltu a7, a6, t3
-; RV32I-NEXT: sub a1, a1, a5
+; RV32I-NEXT: sub a2, t0, a2
+; RV32I-NEXT: sltu a7, a6, t4
; RV32I-NEXT: sub a2, a2, a7
-; RV32I-NEXT: sub a6, a6, t3
+; RV32I-NEXT: sub a3, a5, a3
+; RV32I-NEXT: sub a1, a1, a4
; RV32I-NEXT: sub a1, a1, t2
-; RV32I-NEXT: sub a3, a4, a3
-; RV32I-NEXT: j .LBB22_11
-; RV32I-NEXT: .LBB22_10:
-; RV32I-NEXT: sltu t1, a6, a7
-; RV32I-NEXT: sub a2, a2, t0
-; RV32I-NEXT: sub a2, a2, t1
+; RV32I-NEXT: sub a4, a6, t4
+; RV32I-NEXT: j .LBB22_13
+; RV32I-NEXT: .LBB22_12:
+; RV32I-NEXT: sltu a2, a6, a7
+; RV32I-NEXT: sub t0, t0, t1
+; RV32I-NEXT: sub a2, t0, a2
; RV32I-NEXT: sub a6, a6, a7
-; RV32I-NEXT: sltu a7, a6, t5
+; RV32I-NEXT: sltu a7, a6, t6
; RV32I-NEXT: sub a2, a2, a7
-; RV32I-NEXT: sub a6, a6, t5
-; RV32I-NEXT: sub a5, a5, a1
-; RV32I-NEXT: sub a1, a5, t4
-; RV32I-NEXT: sub a3, a3, a4
-; RV32I-NEXT: .LBB22_11:
-; RV32I-NEXT: sw a6, 8(a0)
+; RV32I-NEXT: sub a3, a3, a5
+; RV32I-NEXT: sub a4, a4, a1
+; RV32I-NEXT: sub a1, a4, t5
+; RV32I-NEXT: sub a4, a6, t6
+; RV32I-NEXT: .LBB22_13:
+; RV32I-NEXT: sw a4, 8(a0)
; RV32I-NEXT: sw a1, 4(a0)
; RV32I-NEXT: sw a3, 0(a0)
; RV32I-NEXT: sw a2, 12(a0)
+; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: abd_cmp_i128:
; RV64I: # %bb.0:
-; RV64I-NEXT: sltu a4, a0, a2
+; RV64I-NEXT: sltu a4, a2, a0
; RV64I-NEXT: mv a5, a4
; RV64I-NEXT: beq a1, a3, .LBB22_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: slt a5, a1, a3
+; RV64I-NEXT: slt a5, a3, a1
; RV64I-NEXT: .LBB22_2:
; RV64I-NEXT: bnez a5, .LBB22_4
; RV64I-NEXT: # %bb.3:
-; RV64I-NEXT: sub a1, a1, a3
+; RV64I-NEXT: sub a1, a3, a1
; RV64I-NEXT: sub a1, a1, a4
-; RV64I-NEXT: sub a0, a0, a2
+; RV64I-NEXT: sub a0, a2, a0
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB22_4:
-; RV64I-NEXT: sltu a4, a2, a0
-; RV64I-NEXT: sub a1, a3, a1
+; RV64I-NEXT: sltu a4, a0, a2
+; RV64I-NEXT: sub a1, a1, a3
; RV64I-NEXT: sub a1, a1, a4
-; RV64I-NEXT: sub a0, a2, a0
+; RV64I-NEXT: sub a0, a0, a2
; RV64I-NEXT: ret
;
; RV32ZBB-LABEL: abd_cmp_i128:
; RV32ZBB: # %bb.0:
-; RV32ZBB-NEXT: lw a3, 0(a2)
-; RV32ZBB-NEXT: lw a4, 0(a1)
-; RV32ZBB-NEXT: lw a5, 4(a2)
-; RV32ZBB-NEXT: lw a6, 8(a2)
-; RV32ZBB-NEXT: lw a7, 8(a1)
-; RV32ZBB-NEXT: lw a2, 12(a2)
+; RV32ZBB-NEXT: lw a3, 0(a1)
+; RV32ZBB-NEXT: lw a5, 0(a2)
+; RV32ZBB-NEXT: lw a4, 4(a1)
+; RV32ZBB-NEXT: lw a6, 8(a1)
+; RV32ZBB-NEXT: lw a7, 8(a2)
; RV32ZBB-NEXT: lw t0, 12(a1)
-; RV32ZBB-NEXT: lw a1, 4(a1)
-; RV32ZBB-NEXT: sltu t1, a7, a6
-; RV32ZBB-NEXT: mv t4, t1
-; RV32ZBB-NEXT: beq t0, a2, .LBB22_2
+; RV32ZBB-NEXT: lw t1, 12(a2)
+; RV32ZBB-NEXT: lw a1, 4(a2)
+; RV32ZBB-NEXT: sltu a2, a7, a6
+; RV32ZBB-NEXT: mv t4, a2
+; RV32ZBB-NEXT: beq t0, t1, .LBB22_2
; RV32ZBB-NEXT: # %bb.1:
-; RV32ZBB-NEXT: slt t4, t0, a2
+; RV32ZBB-NEXT: slt t4, t1, t0
; RV32ZBB-NEXT: .LBB22_2:
-; RV32ZBB-NEXT: sltu t2, a4, a3
+; RV32ZBB-NEXT: sltu t2, a5, a3
+; RV32ZBB-NEXT: sltu t5, a1, a4
; RV32ZBB-NEXT: mv t3, t2
-; RV32ZBB-NEXT: beq a1, a5, .LBB22_4
+; RV32ZBB-NEXT: beq a4, a1, .LBB22_4
; RV32ZBB-NEXT: # %bb.3:
-; RV32ZBB-NEXT: sltu t3, a1, a5
+; RV32ZBB-NEXT: mv t3, t5
; RV32ZBB-NEXT: .LBB22_4:
-; RV32ZBB-NEXT: xor t5, t0, a2
-; RV32ZBB-NEXT: xor t6, a7, a6
-; RV32ZBB-NEXT: or t5, t6, t5
-; RV32ZBB-NEXT: mv t6, t3
-; RV32ZBB-NEXT: beqz t5, .LBB22_6
+; RV32ZBB-NEXT: addi sp, sp, -16
+; RV32ZBB-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
+; RV32ZBB-NEXT: xor t6, t0, t1
+; RV32ZBB-NEXT: xor s0, a6, a7
+; RV32ZBB-NEXT: or t6, s0, t6
+; RV32ZBB-NEXT: beqz t6, .LBB22_6
; RV32ZBB-NEXT: # %bb.5:
-; RV32ZBB-NEXT: mv t6, t4
+; RV32ZBB-NEXT: mv t3, t4
; RV32ZBB-NEXT: .LBB22_6:
-; RV32ZBB-NEXT: sltu t4, a3, a4
-; RV32ZBB-NEXT: mv t5, t4
-; RV32ZBB-NEXT: beq a1, a5, .LBB22_8
+; RV32ZBB-NEXT: mv t4, t2
+; RV32ZBB-NEXT: beq a1, a4, .LBB22_8
; RV32ZBB-NEXT: # %bb.7:
-; RV32ZBB-NEXT: sltu t5, a5, a1
+; RV32ZBB-NEXT: mv t4, t5
; RV32ZBB-NEXT: .LBB22_8:
-; RV32ZBB-NEXT: bnez t6, .LBB22_10
+; RV32ZBB-NEXT: sltu t5, a3, a5
+; RV32ZBB-NEXT: mv t6, t5
+; RV32ZBB-NEXT: beq a4, a1, .LBB22_10
; RV32ZBB-NEXT: # %bb.9:
-; RV32ZBB-NEXT: sub a2, t0, a2
+; RV32ZBB-NEXT: sltu t6, a4, a1
+; RV32ZBB-NEXT: .LBB22_10:
+; RV32ZBB-NEXT: bnez t3, .LBB22_12
+; RV32ZBB-NEXT: # %bb.11:
+; RV32ZBB-NEXT: sub t0, t1, t0
; RV32ZBB-NEXT: sub a6, a7, a6
-; RV32ZBB-NEXT: sub a2, a2, t1
-; RV32ZBB-NEXT: sltu a7, a6, t3
-; RV32ZBB-NEXT: sub a1, a1, a5
+; RV32ZBB-NEXT: sub a2, t0, a2
+; RV32ZBB-NEXT: sltu a7, a6, t4
; RV32ZBB-NEXT: sub a2, a2, a7
-; RV32ZBB-NEXT: sub a6, a6, t3
+; RV32ZBB-NEXT: sub a3, a5, a3
+; RV32ZBB-NEXT: sub a1, a1, a4
; RV32ZBB-NEXT: sub a1, a1, t2
-; RV32ZBB-NEXT: sub a3, a4, a3
-; RV32ZBB-NEXT: j .LBB22_11
-; RV32ZBB-NEXT: .LBB22_10:
-; RV32ZBB-NEXT: sltu t1, a6, a7
-; RV32ZBB-NEXT: sub a2, a2, t0
-; RV32ZBB-NEXT: sub a2, a2, t1
+; RV32ZBB-NEXT: sub a4, a6, t4
+; RV32ZBB-NEXT: j .LBB22_13
+; RV32ZBB-NEXT: .LBB22_12:
+; RV32ZBB-NEXT: sltu a2, a6, a7
+; RV32ZBB-NEXT: sub t0, t0, t1
+; RV32ZBB-NEXT: sub a2, t0, a2
; RV32ZBB-NEXT: sub a6, a6, a7
-; RV32ZBB-NEXT: sltu a7, a6, t5
+; RV32ZBB-NEXT: sltu a7, a6, t6
; RV32ZBB-NEXT: sub a2, a2, a7
-; RV32ZBB-NEXT: sub a6, a6, t5
-; RV32ZBB-NEXT: sub a5, a5, a1
-; RV32ZBB-NEXT: sub a1, a5, t4
-; RV32ZBB-NEXT: sub a3, a3, a4
-; RV32ZBB-NEXT: .LBB22_11:
-; RV32ZBB-NEXT: sw a6, 8(a0)
+; RV32ZBB-NEXT: sub a3, a3, a5
+; RV32ZBB-NEXT: sub a4, a4, a1
+; RV32ZBB-NEXT: sub a1, a4, t5
+; RV32ZBB-NEXT: sub a4, a6, t6
+; RV32ZBB-NEXT: .LBB22_13:
+; RV32ZBB-NEXT: sw a4, 8(a0)
; RV32ZBB-NEXT: sw a1, 4(a0)
; RV32ZBB-NEXT: sw a3, 0(a0)
; RV32ZBB-NEXT: sw a2, 12(a0)
+; RV32ZBB-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
+; RV32ZBB-NEXT: addi sp, sp, 16
; RV32ZBB-NEXT: ret
;
; RV64ZBB-LABEL: abd_cmp_i128:
; RV64ZBB: # %bb.0:
-; RV64ZBB-NEXT: sltu a4, a0, a2
+; RV64ZBB-NEXT: sltu a4, a2, a0
; RV64ZBB-NEXT: mv a5, a4
; RV64ZBB-NEXT: beq a1, a3, .LBB22_2
; RV64ZBB-NEXT: # %bb.1:
-; RV64ZBB-NEXT: slt a5, a1, a3
+; RV64ZBB-NEXT: slt a5, a3, a1
; RV64ZBB-NEXT: .LBB22_2:
; RV64ZBB-NEXT: bnez a5, .LBB22_4
; RV64ZBB-NEXT: # %bb.3:
-; RV64ZBB-NEXT: sub a1, a1, a3
+; RV64ZBB-NEXT: sub a1, a3, a1
; RV64ZBB-NEXT: sub a1, a1, a4
-; RV64ZBB-NEXT: sub a0, a0, a2
+; RV64ZBB-NEXT: sub a0, a2, a0
; RV64ZBB-NEXT: ret
; RV64ZBB-NEXT: .LBB22_4:
-; RV64ZBB-NEXT: sltu a4, a2, a0
-; RV64ZBB-NEXT: sub a1, a3, a1
+; RV64ZBB-NEXT: sltu a4, a0, a2
+; RV64ZBB-NEXT: sub a1, a1, a3
; RV64ZBB-NEXT: sub a1, a1, a4
-; RV64ZBB-NEXT: sub a0, a2, a0
+; RV64ZBB-NEXT: sub a0, a0, a2
; RV64ZBB-NEXT: ret
%cmp = icmp slt i128 %a, %b
%ab = sub i128 %a, %b
diff --git a/llvm/test/CodeGen/RISCV/abds.ll b/llvm/test/CodeGen/RISCV/abds.ll
i...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/102137
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