[llvm] e59c824 - [RISCV] Remove unused tablegen classes from unratified Zbp instructions. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 17 23:42:10 PDT 2024
Author: Craig Topper
Date: 2024-08-17T23:41:18-07:00
New Revision: e59c8241fa6a5a9c8f9175b0ed7b0dfdb5c945cf
URL: https://github.com/llvm/llvm-project/commit/e59c8241fa6a5a9c8f9175b0ed7b0dfdb5c945cf
DIFF: https://github.com/llvm/llvm-project/commit/e59c8241fa6a5a9c8f9175b0ed7b0dfdb5c945cf.diff
LOG: [RISCV] Remove unused tablegen classes from unratified Zbp instructions. NFC
These weren't removed when we removed Zbp.
Added:
Modified:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 5ade54dc3fccd4..f299e823aa3f50 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1483,10 +1483,6 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
if (isRV64())
return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 6) - 1);
return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5) - 1);
- case Match_InvalidUImmLog2XLenHalf:
- if (isRV64())
- return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1);
- return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 1);
case Match_InvalidUImm1:
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 1) - 1);
case Match_InvalidUImm2:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 0cc0605ea87014..f27039b1c658d2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -45,30 +45,6 @@ def riscv_clmul : SDNode<"RISCVISD::CLMUL", SDTIntBinOp>;
def riscv_clmulh : SDNode<"RISCVISD::CLMULH", SDTIntBinOp>;
def riscv_clmulr : SDNode<"RISCVISD::CLMULR", SDTIntBinOp>;
-def UImmLog2XLenHalfAsmOperand : AsmOperandClass {
- let Name = "UImmLog2XLenHalf";
- let RenderMethod = "addImmOperands";
- let DiagnosticType = "InvalidUImmLog2XLenHalf";
-}
-
-def shfl_uimm : RISCVOp, ImmLeaf<XLenVT, [{
- if (Subtarget->is64Bit())
- return isUInt<5>(Imm);
- return isUInt<4>(Imm);
-}]> {
- let ParserMatchClass = UImmLog2XLenHalfAsmOperand;
- let DecoderMethod = "decodeUImmOperand<5>";
- let OperandType = "OPERAND_UIMM_SHFL";
- let MCOperandPredicate = [{
- int64_t Imm;
- if (!MCOp.evaluateAsConstantImm(Imm))
- return false;
- if (STI.getTargetTriple().isArch64Bit())
- return isUInt<5>(Imm);
- return isUInt<4>(Imm);
- }];
-}
-
def BCLRXForm : SDNodeXForm<imm, [{
// Find the lowest 0.
return CurDAG->getTargetConstant(llvm::countr_one(N->getZExtValue()),
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