[llvm] e6ceb29 - [RISCV] Use getAllOnesConstant/getSignedConstant.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 17 00:26:00 PDT 2024
Author: Craig Topper
Date: 2024-08-17T00:18:41-07:00
New Revision: e6ceb29ab6bb5632cac79e99da4d248e9bb7d378
URL: https://github.com/llvm/llvm-project/commit/e6ceb29ab6bb5632cac79e99da4d248e9bb7d378
DIFF: https://github.com/llvm/llvm-project/commit/e6ceb29ab6bb5632cac79e99da4d248e9bb7d378.diff
LOG: [RISCV] Use getAllOnesConstant/getSignedConstant.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index d95cb3cbe3e4ab..11210e6cec177f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -177,7 +177,8 @@ static SDValue selectImmSeq(SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT,
RISCVMatInt::InstSeq &Seq) {
SDValue SrcReg = CurDAG->getRegister(RISCV::X0, VT);
for (const RISCVMatInt::Inst &Inst : Seq) {
- SDValue SDImm = CurDAG->getTargetConstant(Inst.getImm(), DL, VT);
+ SDValue SDImm =
+ CurDAG->getSignedConstant(Inst.getImm(), DL, VT, /*isTarget=*/true);
SDNode *Result = nullptr;
switch (Inst.getOpndKind()) {
case RISCVMatInt::Imm:
@@ -208,10 +209,10 @@ static SDValue selectImm(SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT,
// Use a rematerializable pseudo instruction for short sequences if enabled.
if (Seq.size() == 2 && UsePseudoMovImm)
- return SDValue(
- CurDAG->getMachineNode(RISCV::PseudoMovImm, DL, VT,
- CurDAG->getTargetConstant(Imm, DL, VT)),
- 0);
+ return SDValue(CurDAG->getMachineNode(RISCV::PseudoMovImm, DL, VT,
+ CurDAG->getSignedConstant(
+ Imm, DL, VT, /*isTarget=*/true)),
+ 0);
// See if we can create this constant as (ADD (SLLI X, C), X) where X is at
// worst an LUI+ADDIW. This will require an extra register, but avoids a
@@ -670,9 +671,9 @@ bool RISCVDAGToDAGISel::tryShrinkShlLogicImm(SDNode *Node) {
unsigned ShOpc = SignExt ? RISCV::SLLIW : RISCV::SLLI;
- SDNode *BinOp =
- CurDAG->getMachineNode(BinOpc, DL, VT, Shift.getOperand(0),
- CurDAG->getTargetConstant(ShiftedVal, DL, VT));
+ SDNode *BinOp = CurDAG->getMachineNode(
+ BinOpc, DL, VT, Shift.getOperand(0),
+ CurDAG->getSignedConstant(ShiftedVal, DL, VT, /*isTarget=*/true));
SDNode *SLLI =
CurDAG->getMachineNode(ShOpc, DL, VT, SDValue(BinOp, 0),
CurDAG->getTargetConstant(ShAmt, DL, VT));
@@ -802,7 +803,8 @@ bool RISCVDAGToDAGISel::tryIndexedLoad(SDNode *Node) {
EVT Ty = Ld->getOffset().getValueType();
SDValue Ops[] = {Ld->getBasePtr(),
- CurDAG->getTargetConstant(Offset >> Shift, SDLoc(Node), Ty),
+ CurDAG->getSignedConstant(Offset >> Shift, SDLoc(Node), Ty,
+ /*isTarget=*/true),
CurDAG->getTargetConstant(Shift, SDLoc(Node), Ty),
Ld->getChain()};
SDNode *New = CurDAG->getMachineNode(Opcode, SDLoc(Node), Ld->getValueType(0),
@@ -2486,8 +2488,8 @@ bool RISCVDAGToDAGISel::SelectFrameAddrRegImm(SDValue Addr, SDValue &Base,
if (isInt<12>(CVal)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(),
Subtarget->getXLenVT());
- Offset = CurDAG->getTargetConstant(CVal, SDLoc(Addr),
- Subtarget->getXLenVT());
+ Offset = CurDAG->getSignedConstant(
+ CVal, SDLoc(Addr), Subtarget->getXLenVT(), /*isTarget=*/true);
return true;
}
}
@@ -2523,7 +2525,7 @@ static bool selectConstantAddr(SelectionDAG *CurDAG, const SDLoc &DL,
} else {
Base = CurDAG->getRegister(RISCV::X0, VT);
}
- Offset = CurDAG->getTargetConstant(Lo12, DL, VT);
+ Offset = CurDAG->getSignedConstant(Lo12, DL, VT, /*isTarget=*/true);
return true;
}
@@ -2543,7 +2545,7 @@ static bool selectConstantAddr(SelectionDAG *CurDAG, const SDLoc &DL,
assert(!Seq.empty() && "Expected more instructions in sequence");
Base = selectImmSeq(CurDAG, DL, VT, Seq);
- Offset = CurDAG->getTargetConstant(Lo12, DL, VT);
+ Offset = CurDAG->getSignedConstant(Lo12, DL, VT, /*isTarget=*/true);
return true;
}
@@ -2668,7 +2670,7 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
if (auto *FIN = dyn_cast<FrameIndexSDNode>(Base))
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), VT);
- Offset = CurDAG->getTargetConstant(CVal, DL, VT);
+ Offset = CurDAG->getSignedConstant(CVal, DL, VT, /*isTarget=*/true);
return true;
}
}
@@ -2685,10 +2687,11 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
if (isInt<12>(CVal / 2) && isInt<12>(CVal - CVal / 2)) {
int64_t Adj = CVal < 0 ? -2048 : 2047;
Base = SDValue(
- CurDAG->getMachineNode(RISCV::ADDI, DL, VT, Addr.getOperand(0),
- CurDAG->getTargetConstant(Adj, DL, VT)),
+ CurDAG->getMachineNode(
+ RISCV::ADDI, DL, VT, Addr.getOperand(0),
+ CurDAG->getSignedConstant(Adj, DL, VT, /*isTarget=*/true)),
0);
- Offset = CurDAG->getTargetConstant(CVal - Adj, DL, VT);
+ Offset = CurDAG->getSignedConstant(CVal - Adj, DL, VT, /*isTarget=*/true);
return true;
}
@@ -2741,7 +2744,7 @@ bool RISCVDAGToDAGISel::SelectAddrRegImmLsb00000(SDValue Addr, SDValue &Base,
if (auto *FIN = dyn_cast<FrameIndexSDNode>(Base))
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), VT);
- Offset = CurDAG->getTargetConstant(CVal, DL, VT);
+ Offset = CurDAG->getSignedConstant(CVal, DL, VT, /*isTarget=*/true);
return true;
}
}
@@ -2759,9 +2762,10 @@ bool RISCVDAGToDAGISel::SelectAddrRegImmLsb00000(SDValue Addr, SDValue &Base,
int64_t AdjustedOffset = CVal - Adj;
Base = SDValue(CurDAG->getMachineNode(
RISCV::ADDI, DL, VT, Addr.getOperand(0),
- CurDAG->getTargetConstant(AdjustedOffset, DL, VT)),
+ CurDAG->getSignedConstant(AdjustedOffset, DL, VT,
+ /*isTarget=*/true)),
0);
- Offset = CurDAG->getTargetConstant(Adj, DL, VT);
+ Offset = CurDAG->getSignedConstant(Adj, DL, VT, /*isTarget=*/true);
return true;
}
@@ -2857,9 +2861,9 @@ bool RISCVDAGToDAGISel::selectShiftMask(SDValue N, unsigned ShiftWidth,
if (Imm % ShiftWidth == ShiftWidth - 1) {
SDLoc DL(ShAmt);
EVT VT = ShAmt.getValueType();
- MachineSDNode *Not =
- CurDAG->getMachineNode(RISCV::XORI, DL, VT, ShAmt.getOperand(1),
- CurDAG->getTargetConstant(-1, DL, VT));
+ MachineSDNode *Not = CurDAG->getMachineNode(
+ RISCV::XORI, DL, VT, ShAmt.getOperand(1),
+ CurDAG->getAllOnesConstant(DL, VT, /*isTarget=*/true));
ShAmt = SDValue(Not, 0);
return true;
}
@@ -2906,21 +2910,21 @@ bool RISCVDAGToDAGISel::selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal,
// If the RHS is -2048, we can use xori to produce 0 if the LHS is -2048 and
// non-zero otherwise.
if (CVal == -2048) {
- Val =
- SDValue(CurDAG->getMachineNode(
- RISCV::XORI, DL, N->getValueType(0), LHS,
- CurDAG->getTargetConstant(CVal, DL, N->getValueType(0))),
- 0);
+ Val = SDValue(CurDAG->getMachineNode(
+ RISCV::XORI, DL, N->getValueType(0), LHS,
+ CurDAG->getSignedConstant(CVal, DL, N->getValueType(0),
+ /*isTarget=*/true)),
+ 0);
return true;
}
// If the RHS is [-2047,2048], we can use addi with -RHS to produce 0 if the
// LHS is equal to the RHS and non-zero otherwise.
if (isInt<12>(CVal) || CVal == 2048) {
- Val =
- SDValue(CurDAG->getMachineNode(
- RISCV::ADDI, DL, N->getValueType(0), LHS,
- CurDAG->getTargetConstant(-CVal, DL, N->getValueType(0))),
- 0);
+ Val = SDValue(CurDAG->getMachineNode(
+ RISCV::ADDI, DL, N->getValueType(0), LHS,
+ CurDAG->getSignedConstant(-CVal, DL, N->getValueType(0),
+ /*isTarget=*/true)),
+ 0);
return true;
}
}
@@ -3326,7 +3330,8 @@ bool RISCVDAGToDAGISel::selectSimm5Shl2(SDValue N, SDValue &Simm5,
return false;
EVT Ty = N->getValueType(0);
- Simm5 = CurDAG->getTargetConstant(Offset >> Shift, SDLoc(N), Ty);
+ Simm5 = CurDAG->getSignedConstant(Offset >> Shift, SDLoc(N), Ty,
+ /*isTarget=*/true);
Shl2 = CurDAG->getTargetConstant(Shift, SDLoc(N), Ty);
return true;
}
@@ -3343,16 +3348,16 @@ bool RISCVDAGToDAGISel::selectVLOp(SDValue N, SDValue &VL) {
N->getValueType(0));
} else if (C && C->isAllOnes()) {
// Treat all ones as VLMax.
- VL = CurDAG->getTargetConstant(RISCV::VLMaxSentinel, SDLoc(N),
- N->getValueType(0));
+ VL = CurDAG->getSignedConstant(RISCV::VLMaxSentinel, SDLoc(N),
+ N->getValueType(0), /*isTarget=*/true);
} else if (isa<RegisterSDNode>(N) &&
cast<RegisterSDNode>(N)->getReg() == RISCV::X0) {
// All our VL operands use an operand that allows GPRNoX0 or an immediate
// as the register class. Convert X0 to a special immediate to pass the
// MachineVerifier. This is recognized specially by the vsetvli insertion
// pass.
- VL = CurDAG->getTargetConstant(RISCV::VLMaxSentinel, SDLoc(N),
- N->getValueType(0));
+ VL = CurDAG->getSignedConstant(RISCV::VLMaxSentinel, SDLoc(N),
+ N->getValueType(0), /*isTarget=*/true);
} else {
VL = N;
}
@@ -3410,7 +3415,8 @@ static bool selectVSplatImmHelper(SDValue N, SDValue &SplatVal,
if (!ValidateImm(SplatImm))
return false;
- SplatVal = DAG.getTargetConstant(SplatImm, SDLoc(N), Subtarget.getXLenVT());
+ SplatVal = DAG.getSignedConstant(SplatImm, SDLoc(N), Subtarget.getXLenVT(),
+ /*isTarget=*/true);
return true;
}
@@ -3504,7 +3510,8 @@ bool RISCVDAGToDAGISel::selectRVVSimm5(SDValue N, unsigned Width,
if (!isInt<5>(ImmVal))
return false;
- Imm = CurDAG->getTargetConstant(ImmVal, SDLoc(N), Subtarget->getXLenVT());
+ Imm = CurDAG->getSignedConstant(ImmVal, SDLoc(N), Subtarget->getXLenVT(),
+ /*isTarget=*/true);
return true;
}
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index da937960f1ea76..62980ae71d60b6 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3596,7 +3596,7 @@ static SDValue lowerBuildVectorOfConstants(SDValue Op, SelectionDAG &DAG,
if (I % NumViaIntegerBits == 0 || I == NumElts) {
if (NumViaIntegerBits <= 32)
Bits = SignExtend64<32>(Bits);
- SDValue Elt = DAG.getConstant(Bits, DL, XLenVT);
+ SDValue Elt = DAG.getSignedConstant(Bits, DL, XLenVT);
Elts[IntegerEltIdx] = Elt;
Bits = 0;
BitPos = 0;
@@ -3675,7 +3675,7 @@ static SDValue lowerBuildVectorOfConstants(SDValue Op, SelectionDAG &DAG,
VID = convertFromScalableVector(VIDVT, VID, DAG, Subtarget);
if ((StepOpcode == ISD::MUL && SplatStepVal != 1) ||
(StepOpcode == ISD::SHL && SplatStepVal != 0)) {
- SDValue SplatStep = DAG.getConstant(SplatStepVal, DL, VIDVT);
+ SDValue SplatStep = DAG.getSignedConstant(SplatStepVal, DL, VIDVT);
VID = DAG.getNode(StepOpcode, DL, VIDVT, VID, SplatStep);
}
if (StepDenominator != 1) {
@@ -3684,7 +3684,7 @@ static SDValue lowerBuildVectorOfConstants(SDValue Op, SelectionDAG &DAG,
VID = DAG.getNode(ISD::SRL, DL, VIDVT, VID, SplatStep);
}
if (Addend != 0 || Negate) {
- SDValue SplatAddend = DAG.getConstant(Addend, DL, VIDVT);
+ SDValue SplatAddend = DAG.getSignedConstant(Addend, DL, VIDVT);
VID = DAG.getNode(Negate ? ISD::SUB : ISD::ADD, DL, VIDVT, SplatAddend,
VID);
}
@@ -3723,12 +3723,13 @@ static SDValue lowerBuildVectorOfConstants(SDValue Op, SelectionDAG &DAG,
// On RV64, sign-extend from 32 to 64 bits where possible in order to
// achieve better constant materializion.
- if (Subtarget.is64Bit() && ViaIntVT == MVT::i32)
+ // On RV32, we need to sign-extend to use getSignedConstant.
+ if (ViaIntVT == MVT::i32)
SplatValue = SignExtend64<32>(SplatValue);
SDValue Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ViaVecVT,
DAG.getUNDEF(ViaVecVT),
- DAG.getConstant(SplatValue, DL, XLenVT),
+ DAG.getSignedConstant(SplatValue, DL, XLenVT),
DAG.getVectorIdxConstant(0, DL));
if (ViaVecLen != 1)
Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
@@ -3780,7 +3781,8 @@ static SDValue lowerBuildVectorOfConstants(SDValue Op, SelectionDAG &DAG,
// On RV64, sign-extend from 32 to 64 bits where possible in order to
// achieve better constant materializion.
- if (Subtarget.is64Bit() && ViaIntVT == MVT::i32)
+ // On RV32, we need to sign-extend to use getSignedConstant.
+ if (ViaIntVT == MVT::i32)
SplatValue = SignExtend64<32>(SplatValue);
// Since we can't introduce illegal i64 types at this stage, we can only
@@ -3797,7 +3799,7 @@ static SDValue lowerBuildVectorOfConstants(SDValue Op, SelectionDAG &DAG,
SDValue Splat =
DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ViaContainerVT,
DAG.getUNDEF(ViaContainerVT),
- DAG.getConstant(SplatValue, DL, XLenVT), ViaVL);
+ DAG.getSignedConstant(SplatValue, DL, XLenVT), ViaVL);
Splat = convertFromScalableVector(ViaVecVT, Splat, DAG, Subtarget);
if (ViaVecLen != RequiredVL)
Splat = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
@@ -6810,7 +6812,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
// Using getSetCCSwappedOperands will convert SET(U)GT->SET(U)LT.
CCVal = ISD::getSetCCSwappedOperands(CCVal);
SDValue SetCC = DAG.getSetCC(
- DL, VT, LHS, DAG.getConstant(Imm + 1, DL, OpVT), CCVal);
+ DL, VT, LHS, DAG.getSignedConstant(Imm + 1, DL, OpVT), CCVal);
return DAG.getLogicalNOT(DL, SetCC, VT);
}
}
@@ -7760,8 +7762,9 @@ SDValue RISCVTargetLowering::lowerFRAMEADDR(SDValue Op,
unsigned Depth = Op.getConstantOperandVal(0);
while (Depth--) {
int Offset = -(XLenInBytes * 2);
- SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
- DAG.getIntPtrConstant(Offset, DL));
+ SDValue Ptr = DAG.getNode(
+ ISD::ADD, DL, VT, FrameAddr,
+ DAG.getSignedConstant(Offset, DL, getPointerTy(DAG.getDataLayout())));
FrameAddr =
DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
}
@@ -7786,7 +7789,7 @@ SDValue RISCVTargetLowering::lowerRETURNADDR(SDValue Op,
if (Depth) {
int Off = -XLenInBytes;
SDValue FrameAddr = lowerFRAMEADDR(Op, DAG);
- SDValue Offset = DAG.getConstant(Off, DL, VT);
+ SDValue Offset = DAG.getSignedConstant(Off, DL, VT);
return DAG.getLoad(VT, DL, DAG.getEntryNode(),
DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
MachinePointerInfo());
@@ -7815,7 +7818,7 @@ SDValue RISCVTargetLowering::lowerShiftLeftParts(SDValue Op,
SDValue Zero = DAG.getConstant(0, DL, VT);
SDValue One = DAG.getConstant(1, DL, VT);
- SDValue MinusXLen = DAG.getConstant(-(int)Subtarget.getXLen(), DL, VT);
+ SDValue MinusXLen = DAG.getSignedConstant(-(int)Subtarget.getXLen(), DL, VT);
SDValue XLenMinus1 = DAG.getConstant(Subtarget.getXLen() - 1, DL, VT);
SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusXLen);
SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt);
@@ -7865,7 +7868,7 @@ SDValue RISCVTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
SDValue Zero = DAG.getConstant(0, DL, VT);
SDValue One = DAG.getConstant(1, DL, VT);
- SDValue MinusXLen = DAG.getConstant(-(int)Subtarget.getXLen(), DL, VT);
+ SDValue MinusXLen = DAG.getSignedConstant(-(int)Subtarget.getXLen(), DL, VT);
SDValue XLenMinus1 = DAG.getConstant(Subtarget.getXLen() - 1, DL, VT);
SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusXLen);
SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt);
@@ -7958,7 +7961,7 @@ SDValue RISCVTargetLowering::lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
if (VecVT.isScalableVector()) {
SDValue SplatZero = DAG.getConstant(0, DL, VecVT);
- SDValue SplatTrueVal = DAG.getConstant(ExtTrueVal, DL, VecVT);
+ SDValue SplatTrueVal = DAG.getSignedConstant(ExtTrueVal, DL, VecVT);
return DAG.getNode(ISD::VSELECT, DL, VecVT, Src, SplatTrueVal, SplatZero);
}
@@ -7972,7 +7975,7 @@ SDValue RISCVTargetLowering::lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
MVT XLenVT = Subtarget.getXLenVT();
SDValue SplatZero = DAG.getConstant(0, DL, XLenVT);
- SDValue SplatTrueVal = DAG.getConstant(ExtTrueVal, DL, XLenVT);
+ SDValue SplatTrueVal = DAG.getSignedConstant(ExtTrueVal, DL, XLenVT);
SplatZero = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerVT,
DAG.getUNDEF(ContainerVT), SplatZero, VL);
@@ -8359,7 +8362,7 @@ SDValue RISCVTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
const auto *CVal = cast<ConstantSDNode>(Val);
if (isInt<32>(CVal->getSExtValue())) {
IsLegalInsert = true;
- Val = DAG.getConstant(CVal->getSExtValue(), DL, MVT::i32);
+ Val = DAG.getSignedConstant(CVal->getSExtValue(), DL, MVT::i32);
}
}
@@ -10986,7 +10989,7 @@ SDValue RISCVTargetLowering::lowerVPExtMaskOp(SDValue Op,
SDValue ZeroSplat = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerVT,
DAG.getUNDEF(ContainerVT), Zero, VL);
- SDValue SplatValue = DAG.getConstant(
+ SDValue SplatValue = DAG.getSignedConstant(
Op.getOpcode() == ISD::VP_ZERO_EXTEND ? 1 : -1, DL, XLenVT);
SDValue Splat = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerVT,
DAG.getUNDEF(ContainerVT), SplatValue, VL);
@@ -11116,7 +11119,7 @@ SDValue RISCVTargetLowering::lowerVPFPIntConvOp(SDValue Op,
SDValue Zero = DAG.getConstant(0, DL, XLenVT);
SDValue ZeroSplat = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, IntVT,
DAG.getUNDEF(IntVT), Zero, VL);
- SDValue One = DAG.getConstant(
+ SDValue One = DAG.getSignedConstant(
RISCVISDExtOpc == RISCVISD::VZEXT_VL ? 1 : -1, DL, XLenVT);
SDValue OneSplat = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, IntVT,
DAG.getUNDEF(IntVT), One, VL);
@@ -12998,10 +13001,10 @@ static SDValue transformAddImmMulImm(SDNode *N, SelectionDAG &DAG,
// Build new nodes (add (mul (add x, c1/c0), c0), c1%c0).
SDLoc DL(N);
SDValue New0 = DAG.getNode(ISD::ADD, DL, VT, N0->getOperand(0),
- DAG.getConstant(CA, DL, VT));
+ DAG.getSignedConstant(CA, DL, VT));
SDValue New1 =
- DAG.getNode(ISD::MUL, DL, VT, New0, DAG.getConstant(C0, DL, VT));
- return DAG.getNode(ISD::ADD, DL, VT, New1, DAG.getConstant(CB, DL, VT));
+ DAG.getNode(ISD::MUL, DL, VT, New0, DAG.getSignedConstant(C0, DL, VT));
+ return DAG.getNode(ISD::ADD, DL, VT, New1, DAG.getSignedConstant(CB, DL, VT));
}
// add (zext, zext) -> zext (add (zext, zext))
@@ -15885,10 +15888,11 @@ static SDValue performCONCAT_VECTORSCombine(SDNode *N, SelectionDAG &DAG,
return SDValue();
auto [StrideVariant, MustNegateStride] = *BaseDiff;
- SDValue Stride = std::holds_alternative<SDValue>(StrideVariant)
- ? std::get<SDValue>(StrideVariant)
- : DAG.getConstant(std::get<int64_t>(StrideVariant), DL,
- Lds[0]->getOffset().getValueType());
+ SDValue Stride =
+ std::holds_alternative<SDValue>(StrideVariant)
+ ? std::get<SDValue>(StrideVariant)
+ : DAG.getSignedConstant(std::get<int64_t>(StrideVariant), DL,
+ Lds[0]->getOffset().getValueType());
if (MustNegateStride)
Stride = DAG.getNegative(Stride, DL, Stride.getValueType());
@@ -16599,7 +16603,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
DAG.getConstant(Subtarget.getXLen() - 1, DL, VT));
SDValue AND =
DAG.getNode(ISD::AND, DL, VT, SRA,
- DAG.getConstant(TrueSImm - FalseSImm, DL, VT));
+ DAG.getSignedConstant(TrueSImm - FalseSImm, DL, VT));
return DAG.getNode(ISD::ADD, DL, VT, AND, FalseV);
}
@@ -16754,14 +16758,14 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
assert(MGN->getBasePtr()->getValueType(0) == PtrVT);
assert(IndexType == ISD::UNSIGNED_SCALED);
SDValue BasePtr = DAG.getNode(ISD::ADD, DL, PtrVT, MGN->getBasePtr(),
- DAG.getConstant(Addend, DL, PtrVT));
+ DAG.getSignedConstant(Addend, DL, PtrVT));
SDValue EVL = DAG.getElementCount(DL, Subtarget.getXLenVT(),
VT.getVectorElementCount());
- SDValue StridedLoad =
- DAG.getStridedLoadVP(VT, DL, MGN->getChain(), BasePtr,
- DAG.getConstant(StepNumerator, DL, XLenVT),
- MGN->getMask(), EVL, MGN->getMemOperand());
+ SDValue StridedLoad = DAG.getStridedLoadVP(
+ VT, DL, MGN->getChain(), BasePtr,
+ DAG.getSignedConstant(StepNumerator, DL, XLenVT), MGN->getMask(),
+ EVL, MGN->getMemOperand());
SDValue VPSelect = DAG.getNode(ISD::VP_SELECT, DL, VT, MGN->getMask(),
StridedLoad, MGN->getPassThru(), EVL);
return DAG.getMergeValues({VPSelect, SDValue(StridedLoad.getNode(), 1)},
@@ -17217,7 +17221,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
EVT VT = N->getValueType(0);
if (IntNo == Intrinsic::riscv_vfirst ||
IntNo == Intrinsic::riscv_vfirst_mask)
- return DAG.getConstant(-1, DL, VT);
+ return DAG.getAllOnesConstant(DL, VT);
return DAG.getConstant(0, DL, VT);
}
}
@@ -20498,8 +20502,8 @@ void RISCVTargetLowering::LowerAsmOperandForConstraint(
if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
uint64_t CVal = C->getSExtValue();
if (isInt<12>(CVal))
- Ops.push_back(
- DAG.getTargetConstant(CVal, SDLoc(Op), Subtarget.getXLenVT()));
+ Ops.push_back(DAG.getSignedConstant(
+ CVal, SDLoc(Op), Subtarget.getXLenVT(), /*isTarget=*/true));
}
return;
case 'J':
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 41ef55544e7d2d..74406bf4b10471 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -403,14 +403,14 @@ def AddrRegImm : ComplexPattern<iPTR, 2, "SelectAddrRegImm">;
// Return the negation of an immediate value.
def NegImm : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(-N->getSExtValue(), SDLoc(N),
- N->getValueType(0));
+ return CurDAG->getSignedConstant(-N->getSExtValue(), SDLoc(N),
+ N->getValueType(0), /*isTarget=*/true);
}]>;
// Return an immediate value minus 32.
def ImmSub32 : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(N->getSExtValue() - 32, SDLoc(N),
- N->getValueType(0));
+ return CurDAG->getSignedConstant(N->getSExtValue() - 32, SDLoc(N),
+ N->getValueType(0), /*isTarget=*/true);
}]>;
// Return an immediate subtracted from XLen.
@@ -442,16 +442,16 @@ def AddiPair : PatLeaf<(imm), [{
def AddiPairImmSmall : SDNodeXForm<imm, [{
int64_t Imm = N->getSExtValue();
int64_t Adj = N->getSExtValue() < 0 ? -2048 : 2047;
- return CurDAG->getTargetConstant(Imm - Adj, SDLoc(N),
- N->getValueType(0));
+ return CurDAG->getSignedConstant(Imm - Adj, SDLoc(N),
+ N->getValueType(0), /*isTarget=*/true);
}]>;
// Return -2048 if immediate is negative or 2047 if positive. These are the
// largest simm12 values.
def AddiPairImmLarge : SDNodeXForm<imm, [{
int64_t Imm = N->getSExtValue() < 0 ? -2048 : 2047;
- return CurDAG->getTargetConstant(Imm, SDLoc(N),
- N->getValueType(0));
+ return CurDAG->getSignedConstant(Imm, SDLoc(N),
+ N->getValueType(0), /*isTarget=*/true);
}]>;
def TrailingZeros : SDNodeXForm<imm, [{
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index ab4d5a7e180df0..1b4303fbbcf809 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -92,8 +92,8 @@ def AVL : RegisterOperand<GPRNoX0> {
def VLOp : ComplexPattern<XLenVT, 1, "selectVLOp">;
def DecImm : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(N->getSExtValue() - 1, SDLoc(N),
- N->getValueType(0));
+ return CurDAG->getSignedConstant(N->getSExtValue() - 1, SDLoc(N),
+ N->getValueType(0), /*isTarget=*/true);
}]>;
defvar TAIL_AGNOSTIC = 1;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 8003bd98b8706a..0cc0605ea87014 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -169,8 +169,8 @@ def BCLRIANDIMask : PatLeaf<(imm), [{
}]>;
def BCLRIANDIMaskLow : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant((N->getZExtValue() & 0x7ff) | ~0x7ffull,
- SDLoc(N), N->getValueType(0));
+ return CurDAG->getSignedConstant((N->getZExtValue() & 0x7ff) | ~0x7ffull,
+ SDLoc(N), N->getValueType(0), /*isTarget=*/true);
}]>;
def CSImm12MulBy4 : PatLeaf<(imm), [{
@@ -191,13 +191,13 @@ def CSImm12MulBy8 : PatLeaf<(imm), [{
}]>;
def SimmShiftRightBy2XForm : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(N->getSExtValue() >> 2, SDLoc(N),
- N->getValueType(0));
+ return CurDAG->getSignedConstant(N->getSExtValue() >> 2, SDLoc(N),
+ N->getValueType(0), /*isTarget=*/true);
}]>;
def SimmShiftRightBy3XForm : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(N->getSExtValue() >> 3, SDLoc(N),
- N->getValueType(0));
+ return CurDAG->getSignedConstant(N->getSExtValue() >> 3, SDLoc(N),
+ N->getValueType(0), /*isTarget=*/true);
}]>;
// Pattern to exclude simm12 immediates from matching, namely `non_imm12`.
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