[llvm] 324b676 - Revert "[AArch64] Fold more load.x into load.i with large offset"
Thurston Dang via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 16 15:32:51 PDT 2024
Author: Thurston Dang
Date: 2024-08-16T22:32:12Z
New Revision: 324b676a3d0449add8d4e24047680125f9b9a716
URL: https://github.com/llvm/llvm-project/commit/324b676a3d0449add8d4e24047680125f9b9a716
DIFF: https://github.com/llvm/llvm-project/commit/324b676a3d0449add8d4e24047680125f9b9a716.diff
LOG: Revert "[AArch64] Fold more load.x into load.i with large offset"
This reverts commit 43ffe2eed0d9f73789dbe213023733d164999306.
Reason: buildbot breakage starting at https://lab.llvm.org/buildbot/#/builders/85/builds/1102
I manually bisected and found that clang crashed with 43ffe2eed0d9f73789dbe213023733d164999306 but not the immediately preceding commit (33190490c667aaf8b08d5af8b8ce84524f856e80)
Added:
Modified:
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
llvm/test/CodeGen/AArch64/arm64-addrmode.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 3ea2ba235ca39..697ae510a9565 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -4521,20 +4521,7 @@ AArch64InstrInfo::getLdStAmountOp(const MachineInstr &MI) {
switch (MI.getOpcode()) {
default:
llvm_unreachable("Unexpected opcode");
- case AArch64::LDRBroX:
case AArch64::LDRBBroX:
- case AArch64::LDRSBXroX:
- case AArch64::LDRSBWroX:
- case AArch64::LDRHroX:
- case AArch64::LDRHHroX:
- case AArch64::LDRSHXroX:
- case AArch64::LDRSHWroX:
- case AArch64::LDRWroX:
- case AArch64::LDRSroX:
- case AArch64::LDRSWroX:
- case AArch64::LDRDroX:
- case AArch64::LDRXroX:
- case AArch64::LDRQroX:
return MI.getOperand(4);
}
}
diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index de1727aa6ec70..8de3f8db84ae2 100644
--- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -509,38 +509,12 @@ static unsigned getPreIndexedOpcode(unsigned Opc) {
}
static unsigned getBaseAddressOpcode(unsigned Opc) {
- // TODO: Add more index address stores.
+ // TODO: Add more index address loads/stores.
switch (Opc) {
default:
llvm_unreachable("Opcode has no base address equivalent!");
- case AArch64::LDRBroX:
- return AArch64::LDRBui;
case AArch64::LDRBBroX:
return AArch64::LDRBBui;
- case AArch64::LDRSBXroX:
- return AArch64::LDRSBXui;
- case AArch64::LDRSBWroX:
- return AArch64::LDRSBWui;
- case AArch64::LDRHroX:
- return AArch64::LDRHui;
- case AArch64::LDRHHroX:
- return AArch64::LDRHHui;
- case AArch64::LDRSHXroX:
- return AArch64::LDRSHXui;
- case AArch64::LDRSHWroX:
- return AArch64::LDRSHWui;
- case AArch64::LDRWroX:
- return AArch64::LDRWui;
- case AArch64::LDRSroX:
- return AArch64::LDRSui;
- case AArch64::LDRSWroX:
- return AArch64::LDRSWui;
- case AArch64::LDRDroX:
- return AArch64::LDRDui;
- case AArch64::LDRXroX:
- return AArch64::LDRXui;
- case AArch64::LDRQroX:
- return AArch64::LDRQui;
}
}
@@ -792,31 +766,10 @@ static bool isMergeableIndexLdSt(MachineInstr &MI, int &Scale) {
default:
return false;
// Scaled instructions.
- // TODO: Add more index address stores.
- case AArch64::LDRBroX:
+ // TODO: Add more index address loads/stores.
case AArch64::LDRBBroX:
- case AArch64::LDRSBXroX:
- case AArch64::LDRSBWroX:
Scale = 1;
return true;
- case AArch64::LDRHroX:
- case AArch64::LDRHHroX:
- case AArch64::LDRSHXroX:
- case AArch64::LDRSHWroX:
- Scale = 2;
- return true;
- case AArch64::LDRWroX:
- case AArch64::LDRSroX:
- case AArch64::LDRSWroX:
- Scale = 4;
- return true;
- case AArch64::LDRDroX:
- case AArch64::LDRXroX:
- Scale = 8;
- return true;
- case AArch64::LDRQroX:
- Scale = 16;
- return true;
}
}
diff --git a/llvm/test/CodeGen/AArch64/arm64-addrmode.ll b/llvm/test/CodeGen/AArch64/arm64-addrmode.ll
index bfef61abd8c12..2181eaaee7db6 100644
--- a/llvm/test/CodeGen/AArch64/arm64-addrmode.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-addrmode.ll
@@ -239,8 +239,9 @@ define i32 @LdOffset_i8_zext32(ptr %a) {
define i32 @LdOffset_i8_sext32(ptr %a) {
; CHECK-LABEL: LdOffset_i8_sext32:
; CHECK: // %bb.0:
-; CHECK-NEXT: add x8, x0, #253, lsl #12 // =1036288
-; CHECK-NEXT: ldrsb w0, [x8, #3704]
+; CHECK-NEXT: mov w8, #56952 // =0xde78
+; CHECK-NEXT: movk w8, #15, lsl #16
+; CHECK-NEXT: ldrsb w0, [x0, x8]
; CHECK-NEXT: ret
%arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
%val = load i8, ptr %arrayidx, align 1
@@ -265,8 +266,9 @@ define i64 @LdOffset_i8_zext64(ptr %a) {
define i64 @LdOffset_i8_sext64(ptr %a) {
; CHECK-LABEL: LdOffset_i8_sext64:
; CHECK: // %bb.0:
-; CHECK-NEXT: add x8, x0, #253, lsl #12 // =1036288
-; CHECK-NEXT: ldrsb x0, [x8, #3704]
+; CHECK-NEXT: mov w8, #56952 // =0xde78
+; CHECK-NEXT: movk w8, #15, lsl #16
+; CHECK-NEXT: ldrsb x0, [x0, x8]
; CHECK-NEXT: ret
%arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
%val = load i8, ptr %arrayidx, align 1
@@ -278,8 +280,9 @@ define i64 @LdOffset_i8_sext64(ptr %a) {
define i16 @LdOffset_i16(ptr %a) {
; CHECK-LABEL: LdOffset_i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: add x8, x0, #506, lsl #12 // =2072576
-; CHECK-NEXT: ldrh w0, [x8, #7408]
+; CHECK-NEXT: mov w8, #48368 // =0xbcf0
+; CHECK-NEXT: movk w8, #31, lsl #16
+; CHECK-NEXT: ldrh w0, [x0, x8]
; CHECK-NEXT: ret
%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
%val = load i16, ptr %arrayidx, align 2
@@ -290,8 +293,9 @@ define i16 @LdOffset_i16(ptr %a) {
define i32 @LdOffset_i16_zext32(ptr %a) {
; CHECK-LABEL: LdOffset_i16_zext32:
; CHECK: // %bb.0:
-; CHECK-NEXT: add x8, x0, #506, lsl #12 // =2072576
-; CHECK-NEXT: ldrh w0, [x8, #7408]
+; CHECK-NEXT: mov w8, #48368 // =0xbcf0
+; CHECK-NEXT: movk w8, #31, lsl #16
+; CHECK-NEXT: ldrh w0, [x0, x8]
; CHECK-NEXT: ret
%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
%val = load i16, ptr %arrayidx, align 2
@@ -303,8 +307,9 @@ define i32 @LdOffset_i16_zext32(ptr %a) {
define i32 @LdOffset_i16_sext32(ptr %a) {
; CHECK-LABEL: LdOffset_i16_sext32:
; CHECK: // %bb.0:
-; CHECK-NEXT: add x8, x0, #506, lsl #12 // =2072576
-; CHECK-NEXT: ldrsh w0, [x8, #7408]
+; CHECK-NEXT: mov w8, #48368 // =0xbcf0
+; CHECK-NEXT: movk w8, #31, lsl #16
+; CHECK-NEXT: ldrsh w0, [x0, x8]
; CHECK-NEXT: ret
%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
%val = load i16, ptr %arrayidx, align 2
@@ -316,8 +321,9 @@ define i32 @LdOffset_i16_sext32(ptr %a) {
define i64 @LdOffset_i16_zext64(ptr %a) {
; CHECK-LABEL: LdOffset_i16_zext64:
; CHECK: // %bb.0:
-; CHECK-NEXT: add x8, x0, #506, lsl #12 // =2072576
-; CHECK-NEXT: ldrh w0, [x8, #7408]
+; CHECK-NEXT: mov w8, #48368 // =0xbcf0
+; CHECK-NEXT: movk w8, #31, lsl #16
+; CHECK-NEXT: ldrh w0, [x0, x8]
; CHECK-NEXT: ret
%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
%val = load i16, ptr %arrayidx, align 2
@@ -329,8 +335,9 @@ define i64 @LdOffset_i16_zext64(ptr %a) {
define i64 @LdOffset_i16_sext64(ptr %a) {
; CHECK-LABEL: LdOffset_i16_sext64:
; CHECK: // %bb.0:
-; CHECK-NEXT: add x8, x0, #506, lsl #12 // =2072576
-; CHECK-NEXT: ldrsh x0, [x8, #7408]
+; CHECK-NEXT: mov w8, #48368 // =0xbcf0
+; CHECK-NEXT: movk w8, #31, lsl #16
+; CHECK-NEXT: ldrsh x0, [x0, x8]
; CHECK-NEXT: ret
%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
%val = load i16, ptr %arrayidx, align 2
@@ -342,8 +349,9 @@ define i64 @LdOffset_i16_sext64(ptr %a) {
define i32 @LdOffset_i32(ptr %a) {
; CHECK-LABEL: LdOffset_i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: add x8, x0, #1012, lsl #12 // =4145152
-; CHECK-NEXT: ldr w0, [x8, #14816]
+; CHECK-NEXT: mov w8, #31200 // =0x79e0
+; CHECK-NEXT: movk w8, #63, lsl #16
+; CHECK-NEXT: ldr w0, [x0, x8]
; CHECK-NEXT: ret
%arrayidx = getelementptr inbounds i32, ptr %a, i64 1039992
%val = load i32, ptr %arrayidx, align 4
@@ -354,8 +362,9 @@ define i32 @LdOffset_i32(ptr %a) {
define i64 @LdOffset_i32_zext64(ptr %a) {
; CHECK-LABEL: LdOffset_i32_zext64:
; CHECK: // %bb.0:
-; CHECK-NEXT: add x8, x0, #1012, lsl #12 // =4145152
-; CHECK-NEXT: ldr w0, [x8, #14816]
+; CHECK-NEXT: mov w8, #31200 // =0x79e0
+; CHECK-NEXT: movk w8, #63, lsl #16
+; CHECK-NEXT: ldr w0, [x0, x8]
; CHECK-NEXT: ret
%arrayidx = getelementptr inbounds i32, ptr %a, i64 1039992
%val = load i32, ptr %arrayidx, align 2
@@ -367,8 +376,9 @@ define i64 @LdOffset_i32_zext64(ptr %a) {
define i64 @LdOffset_i32_sext64(ptr %a) {
; CHECK-LABEL: LdOffset_i32_sext64:
; CHECK: // %bb.0:
-; CHECK-NEXT: add x8, x0, #1012, lsl #12 // =4145152
-; CHECK-NEXT: ldrsw x0, [x8, #14816]
+; CHECK-NEXT: mov w8, #31200 // =0x79e0
+; CHECK-NEXT: movk w8, #63, lsl #16
+; CHECK-NEXT: ldrsw x0, [x0, x8]
; CHECK-NEXT: ret
%arrayidx = getelementptr inbounds i32, ptr %a, i64 1039992
%val = load i32, ptr %arrayidx, align 2
@@ -380,8 +390,9 @@ define i64 @LdOffset_i32_sext64(ptr %a) {
define i64 @LdOffset_i64(ptr %a) {
; CHECK-LABEL: LdOffset_i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: add x8, x0, #2024, lsl #12 // =8290304
-; CHECK-NEXT: ldr x0, [x8, #29632]
+; CHECK-NEXT: mov w8, #62400 // =0xf3c0
+; CHECK-NEXT: movk w8, #126, lsl #16
+; CHECK-NEXT: ldr x0, [x0, x8]
; CHECK-NEXT: ret
%arrayidx = getelementptr inbounds i64, ptr %a, i64 1039992
%val = load i64, ptr %arrayidx, align 4
@@ -392,8 +403,9 @@ define i64 @LdOffset_i64(ptr %a) {
define <2 x i32> @LdOffset_v2i32(ptr %a) {
; CHECK-LABEL: LdOffset_v2i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: add x8, x0, #2024, lsl #12 // =8290304
-; CHECK-NEXT: ldr d0, [x8, #29632]
+; CHECK-NEXT: mov w8, #62400 // =0xf3c0
+; CHECK-NEXT: movk w8, #126, lsl #16
+; CHECK-NEXT: ldr d0, [x0, x8]
; CHECK-NEXT: ret
%arrayidx = getelementptr inbounds <2 x i32>, ptr %a, i64 1039992
%val = load <2 x i32>, ptr %arrayidx, align 4
@@ -404,8 +416,9 @@ define <2 x i32> @LdOffset_v2i32(ptr %a) {
define <2 x i64> @LdOffset_v2i64(ptr %a) {
; CHECK-LABEL: LdOffset_v2i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: add x8, x0, #4048, lsl #12 // =16580608
-; CHECK-NEXT: ldr q0, [x8, #59264]
+; CHECK-NEXT: mov w8, #59264 // =0xe780
+; CHECK-NEXT: movk w8, #253, lsl #16
+; CHECK-NEXT: ldr q0, [x0, x8]
; CHECK-NEXT: ret
%arrayidx = getelementptr inbounds <2 x i64>, ptr %a, i64 1039992
%val = load <2 x i64>, ptr %arrayidx, align 4
@@ -416,8 +429,9 @@ define <2 x i64> @LdOffset_v2i64(ptr %a) {
define double @LdOffset_i8_f64(ptr %a) {
; CHECK-LABEL: LdOffset_i8_f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: add x8, x0, #253, lsl #12 // =1036288
-; CHECK-NEXT: ldrsb w8, [x8, #3704]
+; CHECK-NEXT: mov w8, #56952 // =0xde78
+; CHECK-NEXT: movk w8, #15, lsl #16
+; CHECK-NEXT: ldrsb w8, [x0, x8]
; CHECK-NEXT: scvtf d0, w8
; CHECK-NEXT: ret
%arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
@@ -430,8 +444,9 @@ define double @LdOffset_i8_f64(ptr %a) {
define double @LdOffset_i16_f64(ptr %a) {
; CHECK-LABEL: LdOffset_i16_f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: add x8, x0, #506, lsl #12 // =2072576
-; CHECK-NEXT: ldrsh w8, [x8, #7408]
+; CHECK-NEXT: mov w8, #48368 // =0xbcf0
+; CHECK-NEXT: movk w8, #31, lsl #16
+; CHECK-NEXT: ldrsh w8, [x0, x8]
; CHECK-NEXT: scvtf d0, w8
; CHECK-NEXT: ret
%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
@@ -444,8 +459,9 @@ define double @LdOffset_i16_f64(ptr %a) {
define double @LdOffset_i32_f64(ptr %a) {
; CHECK-LABEL: LdOffset_i32_f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: add x8, x0, #1012, lsl #12 // =4145152
-; CHECK-NEXT: ldr s0, [x8, #14816]
+; CHECK-NEXT: mov w8, #31200 // =0x79e0
+; CHECK-NEXT: movk w8, #63, lsl #16
+; CHECK-NEXT: ldr s0, [x0, x8]
; CHECK-NEXT: ucvtf d0, d0
; CHECK-NEXT: ret
%arrayidx = getelementptr inbounds i32, ptr %a, i64 1039992
@@ -458,8 +474,9 @@ define double @LdOffset_i32_f64(ptr %a) {
define double @LdOffset_i64_f64(ptr %a) {
; CHECK-LABEL: LdOffset_i64_f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: add x8, x0, #2024, lsl #12 // =8290304
-; CHECK-NEXT: ldr d0, [x8, #29632]
+; CHECK-NEXT: mov w8, #62400 // =0xf3c0
+; CHECK-NEXT: movk w8, #126, lsl #16
+; CHECK-NEXT: ldr d0, [x0, x8]
; CHECK-NEXT: scvtf d0, d0
; CHECK-NEXT: ret
%arrayidx = getelementptr inbounds i64, ptr %a, i64 1039992
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