[llvm] 8becb80 - [AArch64] Remove apple-a7-sysreg. (#102709)

[via llvm-commits]

Author: Ahmed Bougacha
Date: 2024-08-16T11:27:21-07:00
New Revision: 8becb80c43d567d12126a539514040e93892ef1a

URL: https://github.com/llvm/llvm-project/commit/8becb80c43d567d12126a539514040e93892ef1a
DIFF: https://github.com/llvm/llvm-project/commit/8becb80c43d567d12126a539514040e93892ef1a.diff

LOG: [AArch64] Remove apple-a7-sysreg. (#102709)

This feature provided CPM_IOACC_CTL_EL3, a lone system register that has
been carried over since the original ARM64 implementation, where it was
the only processor-specific register in a long list of architectural
sysregs. We don't need it here.

It's been used as a generic processor-specific sysreg in tests, but the
functionality they target is now better covered in other more exhaustive
tests.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64Features.td
    llvm/lib/Target/AArch64/AArch64Processors.td
    llvm/lib/Target/AArch64/AArch64SystemOperands.td

Removed: 
    llvm/test/CodeGen/AArch64/print-mrs-system-register.ll
    llvm/test/MC/AArch64/arm64-target-specific-sysreg.s
    llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/print-mrs.obj.macho-aarch64
    llvm/test/tools/llvm-objdump/MachO/AArch64/macho-print-mrs.test


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index 8ec13f17cf0a0d..f157b1053f59fa 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -721,9 +721,6 @@ def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
     "true", "Use an instruction sequence for taking the address of a global "
     "that allows a memory tag in the upper address bits">;
 
-def FeatureAppleA7SysReg  : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true",
-  "Apple A7 (the CPU formerly known as Cyclone)">;
-
 def FeatureEL2VMSA : SubtargetFeature<"el2vmsa", "HasEL2VMSA", "true",
   "Enable Exception Level 2 Virtual Memory System Architecture">;
 

diff  --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td
index 52b5c8a0903ea6..83f7fa761e00ea 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -835,7 +835,7 @@ def ProcessorFeatures {
                                      FeatureFullFP16, FeatureCRC, FeatureLSE, FeatureRAS, FeatureRDM,
                                      FeatureFPARMv8];
   list<SubtargetFeature> AppleA7  = [HasV8_0aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
-                                     FeatureNEON,FeaturePerfMon, FeatureAppleA7SysReg];
+                                     FeatureNEON,FeaturePerfMon];
   list<SubtargetFeature> AppleA10 = [HasV8_0aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
                                      FeatureNEON, FeaturePerfMon, FeatureCRC,
                                      FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH];

diff  --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index cd6e6bffda10bc..7476ab852a923b 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -1747,11 +1747,6 @@ foreach n = 0-31 in {
 let Requires = [{ {AArch64::FeatureSPE_EEF} }] in
 def : RWSysReg<"PMSNEVFR_EL1",      0b11, 0b000, 0b1001, 0b1001, 0b001>;
 
-// Cyclone specific system registers
-//                                 Op0    Op1     CRn     CRm    Op2
-let Requires = [{ {AArch64::FeatureAppleA7SysReg} }] in
-def : RWSysReg<"CPM_IOACC_CTL_EL3", 0b11, 0b111, 0b1111, 0b0010, 0b000>;
-
 // Scalable Matrix Extension (SME)
 //                                 Op0   Op1    CRn     CRm     Op2
 let Requires = [{ {AArch64::FeatureSME} }] in {

diff  --git a/llvm/test/CodeGen/AArch64/print-mrs-system-register.ll b/llvm/test/CodeGen/AArch64/print-mrs-system-register.ll
deleted file mode 100644
index 3411ed6161bdbd..00000000000000
--- a/llvm/test/CodeGen/AArch64/print-mrs-system-register.ll
+++ /dev/null
@@ -1,11 +0,0 @@
-; RUN: llc -mtriple=arm64-apple-darwin %s -o - | FileCheck %s
-
-; CHECK: mrs x0, CPM_IOACC_CTL_EL3
-
-define void @foo1() #0 {
-entry:
-  tail call void asm sideeffect "mrs x0, cpm_ioacc_ctl_el3", ""()
-  ret void
-}
-
-attributes #0 = { "target-cpu"="cyclone" }

diff  --git a/llvm/test/MC/AArch64/arm64-target-specific-sysreg.s b/llvm/test/MC/AArch64/arm64-target-specific-sysreg.s
deleted file mode 100644
index 05cea3ac2da55f..00000000000000
--- a/llvm/test/MC/AArch64/arm64-target-specific-sysreg.s
+++ /dev/null
@@ -1,10 +0,0 @@
-// RUN: not llvm-mc -triple arm64 -mcpu=generic -show-encoding < %s 2>&1 | \
-// RUN:   FileCheck %s --check-prefix=CHECK-GENERIC
-//
-// RUN: llvm-mc -triple arm64 -mcpu=cyclone -show-encoding < %s 2>&1 | \
-// RUN:   FileCheck %s --check-prefix=CHECK-CYCLONE
-
-msr CPM_IOACC_CTL_EL3, x0
-
-// CHECK-GENERIC: error: expected writable system register or pstate
-// CHECK-CYCLONE: msr CPM_IOACC_CTL_EL3, x0   // encoding: [0x00,0xf2,0x1f,0xd5]

diff  --git a/llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/print-mrs.obj.macho-aarch64 b/llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/print-mrs.obj.macho-aarch64
deleted file mode 100644
index 06cb13d07dafc5..00000000000000
Binary files a/llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/print-mrs.obj.macho-aarch64 and /dev/null 
diff er

diff  --git a/llvm/test/tools/llvm-objdump/MachO/AArch64/macho-print-mrs.test b/llvm/test/tools/llvm-objdump/MachO/AArch64/macho-print-mrs.test
deleted file mode 100644
index cd40f0e849c5e8..00000000000000
--- a/llvm/test/tools/llvm-objdump/MachO/AArch64/macho-print-mrs.test
+++ /dev/null
@@ -1,3 +0,0 @@
-RUN: llvm-objdump -d -m --no-show-raw-insn %p/Inputs/print-mrs.obj.macho-aarch64 | FileCheck %s
-
-CHECK: 0:  mrs x0, CPM_IOACC_CTL_EL3