[llvm] [RISCV] Decompose LMUL > 1 reverses into LMUL * M1 vrgather.vv (PR #104574)

[Wang Pengcheng via llvm-commits]

W-angler wrote:

For reverse operations in vectorizer, I think we can generate strided load/store with negative stride for some cases. This is what llvm-epi has done, and as far as I know, many downstreams do the same thing.

https://github.com/llvm/llvm-project/pull/104574