[llvm] 8d71016 - [RISCV] Merge shuffle reverse tests. NFC
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 16 00:49:31 PDT 2024
Author: Luke Lau
Date: 2024-08-16T15:49:08+08:00
New Revision: 8d71016eded39ee6a3d69a8219006f0327bea23c
URL: https://github.com/llvm/llvm-project/commit/8d71016eded39ee6a3d69a8219006f0327bea23c
DIFF: https://github.com/llvm/llvm-project/commit/8d71016eded39ee6a3d69a8219006f0327bea23c.diff
LOG: [RISCV] Merge shuffle reverse tests. NFC
shuffle-reverse.ll also tests reverse shuffles with two source
vectors, so copy them over.
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
Removed:
llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
index 2ea51515187e23..cb7fde9188e813 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
@@ -4,10 +4,6 @@
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVBB,RV32-ZVBB
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVBB,RV64-ZVBB
-;
-; VECTOR_REVERSE - masks
-;
-
define <2 x i1> @reverse_v2i1(<2 x i1> %a) {
; NO-ZVBB-LABEL: reverse_v2i1:
; NO-ZVBB: # %bb.0:
@@ -776,3 +772,463 @@ define <12 x i64> @reverse_v12i64(<12 x i64> %a) {
%res = shufflevector <12 x i64> %a, <12 x i64> poison, <12 x i32> <i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <12 x i64> %res
}
+
+define <4 x i8> @reverse_v4i8_2(<2 x i8> %a, <2 x i8> %b) {
+; NO-ZVBB-LABEL: reverse_v4i8_2:
+; NO-ZVBB: # %bb.0:
+; NO-ZVBB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; NO-ZVBB-NEXT: vslidedown.vi v10, v8, 1
+; NO-ZVBB-NEXT: vslideup.vi v10, v8, 1
+; NO-ZVBB-NEXT: vslidedown.vi v8, v9, 1
+; NO-ZVBB-NEXT: vslideup.vi v8, v9, 1
+; NO-ZVBB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; NO-ZVBB-NEXT: vslideup.vi v8, v10, 2
+; NO-ZVBB-NEXT: ret
+;
+; ZVBB-LABEL: reverse_v4i8_2:
+; ZVBB: # %bb.0:
+; ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVBB-NEXT: vrev8.v v10, v8
+; ZVBB-NEXT: vrev8.v v8, v9
+; ZVBB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v10, 2
+; ZVBB-NEXT: ret
+ %res = shufflevector <2 x i8> %a, <2 x i8> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+ ret <4 x i8> %res
+}
+
+define <8 x i8> @reverse_v8i8_2(<4 x i8> %a, <4 x i8> %b) {
+; CHECK-LABEL: reverse_v8i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
+; CHECK-NEXT: vid.v v11
+; CHECK-NEXT: vrsub.vi v12, v11, 7
+; CHECK-NEXT: vrgather.vv v10, v8, v12
+; CHECK-NEXT: vmv.v.i v0, 15
+; CHECK-NEXT: vrsub.vi v8, v11, 3
+; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: ret
+ %res = shufflevector <4 x i8> %a, <4 x i8> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <8 x i8> %res
+}
+
+define <16 x i8> @reverse_v16i8_2(<8 x i8> %a, <8 x i8> %b) {
+; CHECK-LABEL: reverse_v16i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vid.v v11
+; CHECK-NEXT: vrsub.vi v12, v11, 15
+; CHECK-NEXT: vrgather.vv v10, v8, v12
+; CHECK-NEXT: li a0, 255
+; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
+; CHECK-NEXT: vrsub.vi v8, v11, 7
+; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
+; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: ret
+ %res = shufflevector <8 x i8> %a, <8 x i8> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <16 x i8> %res
+}
+
+define <32 x i8> @reverse_v32i8_2(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: reverse_v32i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v12, v9
+; CHECK-NEXT: li a0, 32
+; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; CHECK-NEXT: vid.v v14
+; CHECK-NEXT: li a0, 31
+; CHECK-NEXT: vrsub.vx v16, v14, a0
+; CHECK-NEXT: vrgather.vv v10, v8, v16
+; CHECK-NEXT: vrsub.vi v8, v14, 15
+; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, mu
+; CHECK-NEXT: vrgather.vv v10, v12, v8, v0.t
+; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: ret
+ %res = shufflevector <16 x i8> %a, <16 x i8> %b, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <32 x i8> %res
+}
+
+define <4 x i16> @reverse_v4i16_2(<2 x i16> %a, <2 x i16> %b) {
+; NO-ZVBB-LABEL: reverse_v4i16_2:
+; NO-ZVBB: # %bb.0:
+; NO-ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; NO-ZVBB-NEXT: vslidedown.vi v10, v8, 1
+; NO-ZVBB-NEXT: vslideup.vi v10, v8, 1
+; NO-ZVBB-NEXT: vslidedown.vi v8, v9, 1
+; NO-ZVBB-NEXT: vslideup.vi v8, v9, 1
+; NO-ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; NO-ZVBB-NEXT: vslideup.vi v8, v10, 2
+; NO-ZVBB-NEXT: ret
+;
+; ZVBB-LABEL: reverse_v4i16_2:
+; ZVBB: # %bb.0:
+; ZVBB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; ZVBB-NEXT: vror.vi v10, v8, 16
+; ZVBB-NEXT: vror.vi v8, v9, 16
+; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v10, 2
+; ZVBB-NEXT: ret
+ %res = shufflevector <2 x i16> %a, <2 x i16> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+ ret <4 x i16> %res
+}
+
+define <8 x i16> @reverse_v8i16_2(<4 x i16> %a, <4 x i16> %b) {
+; CHECK-LABEL: reverse_v8i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
+; CHECK-NEXT: vid.v v11
+; CHECK-NEXT: vrsub.vi v12, v11, 7
+; CHECK-NEXT: vrgather.vv v10, v8, v12
+; CHECK-NEXT: vmv.v.i v0, 15
+; CHECK-NEXT: vrsub.vi v8, v11, 3
+; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
+; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: ret
+ %res = shufflevector <4 x i16> %a, <4 x i16> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <8 x i16> %res
+}
+
+define <16 x i16> @reverse_v16i16_2(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: reverse_v16i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v12, v9
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
+; CHECK-NEXT: vid.v v14
+; CHECK-NEXT: vrsub.vi v16, v14, 15
+; CHECK-NEXT: vrgather.vv v10, v8, v16
+; CHECK-NEXT: vrsub.vi v8, v14, 7
+; CHECK-NEXT: li a0, 255
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vrgather.vv v10, v12, v8, v0.t
+; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: ret
+ %res = shufflevector <8 x i16> %a, <8 x i16> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <16 x i16> %res
+}
+
+define <32 x i16> @reverse_v32i16_2(<16 x i16> %a, <16 x i16> %b) {
+; CHECK-LABEL: reverse_v32i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv2r.v v16, v10
+; CHECK-NEXT: li a0, 32
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: vid.v v20
+; CHECK-NEXT: li a0, 31
+; CHECK-NEXT: vrsub.vx v24, v20, a0
+; CHECK-NEXT: vrgather.vv v12, v8, v24
+; CHECK-NEXT: vrsub.vi v8, v20, 15
+; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, mu
+; CHECK-NEXT: vrgather.vv v12, v16, v8, v0.t
+; CHECK-NEXT: vmv.v.v v8, v12
+; CHECK-NEXT: ret
+ %res = shufflevector <16 x i16> %a, <16 x i16> %b, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <32 x i16> %res
+}
+
+define <4 x i32> @reverse_v4i32_2(<2 x i32> %a, < 2 x i32> %b) {
+; NO-ZVBB-LABEL: reverse_v4i32_2:
+; NO-ZVBB: # %bb.0:
+; NO-ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; NO-ZVBB-NEXT: vslidedown.vi v10, v8, 1
+; NO-ZVBB-NEXT: vslideup.vi v10, v8, 1
+; NO-ZVBB-NEXT: vslidedown.vi v8, v9, 1
+; NO-ZVBB-NEXT: vslideup.vi v8, v9, 1
+; NO-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; NO-ZVBB-NEXT: vslideup.vi v8, v10, 2
+; NO-ZVBB-NEXT: ret
+;
+; ZVBB-LABEL: reverse_v4i32_2:
+; ZVBB: # %bb.0:
+; ZVBB-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; ZVBB-NEXT: vror.vi v10, v8, 32
+; ZVBB-NEXT: vror.vi v8, v9, 32
+; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v10, 2
+; ZVBB-NEXT: ret
+ %res = shufflevector <2 x i32> %a, <2 x i32> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+ ret <4 x i32> %res
+}
+
+define <8 x i32> @reverse_v8i32_2(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: reverse_v8i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v12, v9
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vid.v v9
+; CHECK-NEXT: vrsub.vi v13, v9, 7
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v13
+; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vrsub.vi v8, v9, 3
+; CHECK-NEXT: vmv.v.i v0, 15
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; CHECK-NEXT: vrgatherei16.vv v10, v12, v8, v0.t
+; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: ret
+ %res = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <8 x i32> %res
+}
+
+define <16 x i32> @reverse_v16i32_2(<8 x i32> %a, <8 x i32> %b) {
+; CHECK-LABEL: reverse_v16i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv2r.v v16, v10
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vid.v v10
+; CHECK-NEXT: vrsub.vi v18, v10, 15
+; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vrgatherei16.vv v12, v8, v18
+; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vrsub.vi v8, v10, 7
+; CHECK-NEXT: li a0, 255
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
+; CHECK-NEXT: vrgatherei16.vv v12, v16, v8, v0.t
+; CHECK-NEXT: vmv.v.v v8, v12
+; CHECK-NEXT: ret
+ %res = shufflevector <8 x i32> %a, <8 x i32> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <16 x i32> %res
+}
+
+define <32 x i32> @reverse_v32i32_2(<16 x i32> %a, <16 x i32> %b) {
+; CHECK-LABEL: reverse_v32i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv4r.v v24, v12
+; CHECK-NEXT: vmv4r.v v16, v8
+; CHECK-NEXT: li a0, 32
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: vid.v v20
+; CHECK-NEXT: li a0, 31
+; CHECK-NEXT: vrsub.vx v28, v20, a0
+; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; CHECK-NEXT: vrgatherei16.vv v8, v16, v28
+; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; CHECK-NEXT: vrsub.vi v16, v20, 15
+; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vrgatherei16.vv v8, v24, v16, v0.t
+; CHECK-NEXT: ret
+ %res = shufflevector <16 x i32> %a, <16 x i32> %b, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <32 x i32> %res
+}
+
+define <4 x i64> @reverse_v4i64_2(<2 x i64> %a, < 2 x i64> %b) {
+; CHECK-LABEL: reverse_v4i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v8, 1
+; CHECK-NEXT: vslideup.vi v10, v8, 1
+; CHECK-NEXT: vslidedown.vi v8, v9, 1
+; CHECK-NEXT: vslideup.vi v8, v9, 1
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 2
+; CHECK-NEXT: ret
+ %res = shufflevector <2 x i64> %a, <2 x i64> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+ ret <4 x i64> %res
+}
+
+define <8 x i64> @reverse_v8i64_2(<4 x i64> %a, <4 x i64> %b) {
+; CHECK-LABEL: reverse_v8i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv2r.v v16, v10
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vid.v v10
+; CHECK-NEXT: vrsub.vi v11, v10, 7
+; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; CHECK-NEXT: vrgatherei16.vv v12, v8, v11
+; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vrsub.vi v8, v10, 3
+; CHECK-NEXT: vmv.v.i v0, 15
+; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; CHECK-NEXT: vrgatherei16.vv v12, v16, v8, v0.t
+; CHECK-NEXT: vmv.v.v v8, v12
+; CHECK-NEXT: ret
+ %res = shufflevector <4 x i64> %a, <4 x i64> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <8 x i64> %res
+}
+
+define <4 x half> @reverse_v4f16_2(<2 x half> %a, <2 x half> %b) {
+; NO-ZVBB-LABEL: reverse_v4f16_2:
+; NO-ZVBB: # %bb.0:
+; NO-ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; NO-ZVBB-NEXT: vslidedown.vi v10, v8, 1
+; NO-ZVBB-NEXT: vslideup.vi v10, v8, 1
+; NO-ZVBB-NEXT: vslidedown.vi v8, v9, 1
+; NO-ZVBB-NEXT: vslideup.vi v8, v9, 1
+; NO-ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; NO-ZVBB-NEXT: vslideup.vi v8, v10, 2
+; NO-ZVBB-NEXT: ret
+;
+; ZVBB-LABEL: reverse_v4f16_2:
+; ZVBB: # %bb.0:
+; ZVBB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; ZVBB-NEXT: vror.vi v10, v8, 16
+; ZVBB-NEXT: vror.vi v8, v9, 16
+; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v10, 2
+; ZVBB-NEXT: ret
+ %res = shufflevector <2 x half> %a, <2 x half> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+ ret <4 x half> %res
+}
+
+define <8 x half> @reverse_v8f16_2(<4 x half> %a, <4 x half> %b) {
+; CHECK-LABEL: reverse_v8f16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
+; CHECK-NEXT: vid.v v11
+; CHECK-NEXT: vrsub.vi v12, v11, 7
+; CHECK-NEXT: vrgather.vv v10, v8, v12
+; CHECK-NEXT: vmv.v.i v0, 15
+; CHECK-NEXT: vrsub.vi v8, v11, 3
+; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
+; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: ret
+ %res = shufflevector <4 x half> %a, <4 x half> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <8 x half> %res
+}
+
+define <16 x half> @reverse_v16f16_2(<8 x half> %a, <8 x half> %b) {
+; CHECK-LABEL: reverse_v16f16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v12, v9
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
+; CHECK-NEXT: vid.v v14
+; CHECK-NEXT: vrsub.vi v16, v14, 15
+; CHECK-NEXT: vrgather.vv v10, v8, v16
+; CHECK-NEXT: vrsub.vi v8, v14, 7
+; CHECK-NEXT: li a0, 255
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vrgather.vv v10, v12, v8, v0.t
+; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: ret
+ %res = shufflevector <8 x half> %a, <8 x half> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <16 x half> %res
+}
+
+define <32 x half> @reverse_v32f16_2(<16 x half> %a) {
+; CHECK-LABEL: reverse_v32f16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a0, 32
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: vid.v v12
+; CHECK-NEXT: li a0, 31
+; CHECK-NEXT: vrsub.vx v16, v12, a0
+; CHECK-NEXT: vrgather.vv v12, v8, v16
+; CHECK-NEXT: vmv.v.v v8, v12
+; CHECK-NEXT: ret
+ %res = shufflevector <16 x half> %a, <16 x half> poison, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <32 x half> %res
+}
+
+define <4 x float> @reverse_v4f32_2(<2 x float> %a, <2 x float> %b) {
+; NO-ZVBB-LABEL: reverse_v4f32_2:
+; NO-ZVBB: # %bb.0:
+; NO-ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; NO-ZVBB-NEXT: vslidedown.vi v10, v8, 1
+; NO-ZVBB-NEXT: vslideup.vi v10, v8, 1
+; NO-ZVBB-NEXT: vslidedown.vi v8, v9, 1
+; NO-ZVBB-NEXT: vslideup.vi v8, v9, 1
+; NO-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; NO-ZVBB-NEXT: vslideup.vi v8, v10, 2
+; NO-ZVBB-NEXT: ret
+;
+; ZVBB-LABEL: reverse_v4f32_2:
+; ZVBB: # %bb.0:
+; ZVBB-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; ZVBB-NEXT: vror.vi v10, v8, 32
+; ZVBB-NEXT: vror.vi v8, v9, 32
+; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v10, 2
+; ZVBB-NEXT: ret
+ %res = shufflevector <2 x float> %a, <2 x float> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+ ret <4 x float> %res
+}
+
+define <8 x float> @reverse_v8f32_2(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: reverse_v8f32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v12, v9
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vid.v v9
+; CHECK-NEXT: vrsub.vi v13, v9, 7
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v13
+; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vrsub.vi v8, v9, 3
+; CHECK-NEXT: vmv.v.i v0, 15
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; CHECK-NEXT: vrgatherei16.vv v10, v12, v8, v0.t
+; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: ret
+ %res = shufflevector <4 x float> %a, <4 x float> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <8 x float> %res
+}
+
+define <16 x float> @reverse_v16f32_2(<8 x float> %a, <8 x float> %b) {
+; CHECK-LABEL: reverse_v16f32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv2r.v v16, v10
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vid.v v10
+; CHECK-NEXT: vrsub.vi v18, v10, 15
+; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vrgatherei16.vv v12, v8, v18
+; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vrsub.vi v8, v10, 7
+; CHECK-NEXT: li a0, 255
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
+; CHECK-NEXT: vrgatherei16.vv v12, v16, v8, v0.t
+; CHECK-NEXT: vmv.v.v v8, v12
+; CHECK-NEXT: ret
+ %res = shufflevector <8 x float> %a, <8 x float> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <16 x float> %res
+}
+
+define <4 x double> @reverse_v4f64_2(<2 x double> %a, < 2 x double> %b) {
+; CHECK-LABEL: reverse_v4f64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v8, 1
+; CHECK-NEXT: vslideup.vi v10, v8, 1
+; CHECK-NEXT: vslidedown.vi v8, v9, 1
+; CHECK-NEXT: vslideup.vi v8, v9, 1
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 2
+; CHECK-NEXT: ret
+ %res = shufflevector <2 x double> %a, <2 x double> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+ ret <4 x double> %res
+}
+
+define <8 x double> @reverse_v8f64_2(<4 x double> %a, <4 x double> %b) {
+; CHECK-LABEL: reverse_v8f64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv2r.v v16, v10
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vid.v v10
+; CHECK-NEXT: vrsub.vi v11, v10, 7
+; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; CHECK-NEXT: vrgatherei16.vv v12, v8, v11
+; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vrsub.vi v8, v10, 3
+; CHECK-NEXT: vmv.v.i v0, 15
+; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; CHECK-NEXT: vrgatherei16.vv v12, v16, v8, v0.t
+; CHECK-NEXT: vmv.v.v v8, v12
+; CHECK-NEXT: ret
+ %res = shufflevector <4 x double> %a, <4 x double> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <8 x double> %res
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
deleted file mode 100644
index 9e62bb623a03bd..00000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
+++ /dev/null
@@ -1,734 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+f,+zfh,+zvfh,+d -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+f,+zfh,+zvfh,+d -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
-
-define <2 x i8> @v2i8(<2 x i8> %a) {
-; CHECK-LABEL: v2i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-NEXT: vslidedown.vi v9, v8, 1
-; CHECK-NEXT: vslideup.vi v9, v8, 1
-; CHECK-NEXT: vmv1r.v v8, v9
-; CHECK-NEXT: ret
- %v2i8 = shufflevector <2 x i8> %a, <2 x i8> undef, <2 x i32> <i32 1, i32 0>
- ret <2 x i8> %v2i8
-}
-
-define <4 x i8> @v2i8_2(<2 x i8> %a, <2 x i8> %b) {
-; CHECK-LABEL: v2i8_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-NEXT: vslidedown.vi v10, v8, 1
-; CHECK-NEXT: vslideup.vi v10, v8, 1
-; CHECK-NEXT: vslidedown.vi v8, v9, 1
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 2
-; CHECK-NEXT: ret
- %v4i8 = shufflevector <2 x i8> %a, <2 x i8> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
- ret <4 x i8> %v4i8
-}
-
-define <4 x i8> @v4i8(<4 x i8> %a) {
-; CHECK-LABEL: v4i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT: vid.v v9
-; CHECK-NEXT: vrsub.vi v10, v9, 3
-; CHECK-NEXT: vrgather.vv v9, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v9
-; CHECK-NEXT: ret
- %v4i8 = shufflevector <4 x i8> %a, <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
- ret <4 x i8> %v4i8
-}
-
-define <8 x i8> @v4i8_2(<4 x i8> %a, <4 x i8> %b) {
-; CHECK-LABEL: v4i8_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vid.v v11
-; CHECK-NEXT: vrsub.vi v12, v11, 7
-; CHECK-NEXT: vrgather.vv v10, v8, v12
-; CHECK-NEXT: vmv.v.i v0, 15
-; CHECK-NEXT: vrsub.vi v8, v11, 3
-; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v8, v10
-; CHECK-NEXT: ret
- %v8i8 = shufflevector <4 x i8> %a, <4 x i8> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <8 x i8> %v8i8
-}
-
-define <8 x i8> @v8i8(<8 x i8> %a) {
-; CHECK-LABEL: v8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vid.v v9
-; CHECK-NEXT: vrsub.vi v10, v9, 7
-; CHECK-NEXT: vrgather.vv v9, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v9
-; CHECK-NEXT: ret
- %v8i8 = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <8 x i8> %v8i8
-}
-
-define <16 x i8> @v8i8_2(<8 x i8> %a, <8 x i8> %b) {
-; CHECK-LABEL: v8i8_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT: vid.v v11
-; CHECK-NEXT: vrsub.vi v12, v11, 15
-; CHECK-NEXT: vrgather.vv v10, v8, v12
-; CHECK-NEXT: li a0, 255
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v11, 7
-; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
-; CHECK-NEXT: vmv.v.v v8, v10
-; CHECK-NEXT: ret
- %v16i8 = shufflevector <8 x i8> %a, <8 x i8> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <16 x i8> %v16i8
-}
-
-define <16 x i8> @v16i8(<16 x i8> %a) {
-; CHECK-LABEL: v16i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT: vid.v v9
-; CHECK-NEXT: vrsub.vi v10, v9, 15
-; CHECK-NEXT: vrgather.vv v9, v8, v10
-; CHECK-NEXT: vmv.v.v v8, v9
-; CHECK-NEXT: ret
- %v16i8 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <16 x i8> %v16i8
-}
-
-define <32 x i8> @v16i8_2(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-LABEL: v16i8_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v12, v9
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vid.v v14
-; CHECK-NEXT: li a0, 31
-; CHECK-NEXT: vrsub.vx v16, v14, a0
-; CHECK-NEXT: vrgather.vv v10, v8, v16
-; CHECK-NEXT: vrsub.vi v8, v14, 15
-; CHECK-NEXT: lui a0, 16
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, mu
-; CHECK-NEXT: vrgather.vv v10, v12, v8, v0.t
-; CHECK-NEXT: vmv.v.v v8, v10
-; CHECK-NEXT: ret
- %v32i8 = shufflevector <16 x i8> %a, <16 x i8> %b, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <32 x i8> %v32i8
-}
-
-define <2 x i16> @v2i16(<2 x i16> %a) {
-; CHECK-LABEL: v2i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v9, v8, 1
-; CHECK-NEXT: vslideup.vi v9, v8, 1
-; CHECK-NEXT: vmv1r.v v8, v9
-; CHECK-NEXT: ret
- %v2i16 = shufflevector <2 x i16> %a, <2 x i16> undef, <2 x i32> <i32 1, i32 0>
- ret <2 x i16> %v2i16
-}
-
-define <4 x i16> @v2i16_2(<2 x i16> %a, <2 x i16> %b) {
-; CHECK-LABEL: v2i16_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v10, v8, 1
-; CHECK-NEXT: vslideup.vi v10, v8, 1
-; CHECK-NEXT: vslidedown.vi v8, v9, 1
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 2
-; CHECK-NEXT: ret
- %v4i16 = shufflevector <2 x i16> %a, <2 x i16> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
- ret <4 x i16> %v4i16
-}
-
-define <4 x i16> @v4i16(<4 x i16> %a) {
-; CHECK-LABEL: v4i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vid.v v9
-; CHECK-NEXT: vrsub.vi v10, v9, 3
-; CHECK-NEXT: vrgather.vv v9, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v9
-; CHECK-NEXT: ret
- %v4i16 = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
- ret <4 x i16> %v4i16
-}
-
-define <8 x i16> @v4i16_2(<4 x i16> %a, <4 x i16> %b) {
-; CHECK-LABEL: v4i16_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vid.v v11
-; CHECK-NEXT: vrsub.vi v12, v11, 7
-; CHECK-NEXT: vrgather.vv v10, v8, v12
-; CHECK-NEXT: vmv.v.i v0, 15
-; CHECK-NEXT: vrsub.vi v8, v11, 3
-; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
-; CHECK-NEXT: vmv.v.v v8, v10
-; CHECK-NEXT: ret
- %v8i16 = shufflevector <4 x i16> %a, <4 x i16> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <8 x i16> %v8i16
-}
-
-define <8 x i16> @v8i16(<8 x i16> %a) {
-; CHECK-LABEL: v8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vid.v v9
-; CHECK-NEXT: vrsub.vi v10, v9, 7
-; CHECK-NEXT: vrgather.vv v9, v8, v10
-; CHECK-NEXT: vmv.v.v v8, v9
-; CHECK-NEXT: ret
- %v8i16 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <8 x i16> %v8i16
-}
-
-define <16 x i16> @v8i16_2(<8 x i16> %a, <8 x i16> %b) {
-; CHECK-LABEL: v8i16_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v12, v9
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vid.v v14
-; CHECK-NEXT: vrsub.vi v16, v14, 15
-; CHECK-NEXT: vrgather.vv v10, v8, v16
-; CHECK-NEXT: vrsub.vi v8, v14, 7
-; CHECK-NEXT: li a0, 255
-; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: vrgather.vv v10, v12, v8, v0.t
-; CHECK-NEXT: vmv.v.v v8, v10
-; CHECK-NEXT: ret
- %v16i16 = shufflevector <8 x i16> %a, <8 x i16> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <16 x i16> %v16i16
-}
-
-define <16 x i16> @v16i16(<16 x i16> %a) {
-; CHECK-LABEL: v16i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vid.v v10
-; CHECK-NEXT: vrsub.vi v12, v10, 15
-; CHECK-NEXT: vrgather.vv v10, v8, v12
-; CHECK-NEXT: vmv.v.v v8, v10
-; CHECK-NEXT: ret
- %v16i16 = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <16 x i16> %v16i16
-}
-
-define <32 x i16> @v16i16_2(<16 x i16> %a, <16 x i16> %b) {
-; CHECK-LABEL: v16i16_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vmv2r.v v16, v10
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vid.v v20
-; CHECK-NEXT: li a0, 31
-; CHECK-NEXT: vrsub.vx v24, v20, a0
-; CHECK-NEXT: vrgather.vv v12, v8, v24
-; CHECK-NEXT: vrsub.vi v8, v20, 15
-; CHECK-NEXT: lui a0, 16
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, mu
-; CHECK-NEXT: vrgather.vv v12, v16, v8, v0.t
-; CHECK-NEXT: vmv.v.v v8, v12
-; CHECK-NEXT: ret
- %v32i16 = shufflevector <16 x i16> %a, <16 x i16> %b, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <32 x i16> %v32i16
-}
-
-define <2 x i32> @v2i32(<2 x i32> %a) {
-; CHECK-LABEL: v2i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vi v9, v8, 1
-; CHECK-NEXT: vslideup.vi v9, v8, 1
-; CHECK-NEXT: vmv1r.v v8, v9
-; CHECK-NEXT: ret
- %v2i32 = shufflevector <2 x i32> %a, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
- ret <2 x i32> %v2i32
-}
-
-define <4 x i32> @v2i32_2(<2 x i32> %a, < 2 x i32> %b) {
-; CHECK-LABEL: v2i32_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vi v10, v8, 1
-; CHECK-NEXT: vslideup.vi v10, v8, 1
-; CHECK-NEXT: vslidedown.vi v8, v9, 1
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 2
-; CHECK-NEXT: ret
- %v4i32 = shufflevector <2 x i32> %a, <2 x i32> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
- ret <4 x i32> %v4i32
-}
-
-define <4 x i32> @v4i32(<4 x i32> %a) {
-; CHECK-LABEL: v4i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vid.v v9
-; CHECK-NEXT: vrsub.vi v10, v9, 3
-; CHECK-NEXT: vrgather.vv v9, v8, v10
-; CHECK-NEXT: vmv.v.v v8, v9
-; CHECK-NEXT: ret
- %v4i32 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
- ret <4 x i32> %v4i32
-}
-
-define <8 x i32> @v4i32_2(<4 x i32> %a, <4 x i32> %b) {
-; CHECK-LABEL: v4i32_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v12, v9
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vid.v v9
-; CHECK-NEXT: vrsub.vi v13, v9, 7
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v10, v8, v13
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT: vrsub.vi v8, v9, 3
-; CHECK-NEXT: vmv.v.i v0, 15
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v10, v12, v8, v0.t
-; CHECK-NEXT: vmv.v.v v8, v10
-; CHECK-NEXT: ret
- %v8i32 = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <8 x i32> %v8i32
-}
-
-define <8 x i32> @v8i32(<8 x i32> %a) {
-; CHECK-LABEL: v8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vid.v v10
-; CHECK-NEXT: vrsub.vi v12, v10, 7
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
-; CHECK-NEXT: vmv.v.v v8, v10
-; CHECK-NEXT: ret
- %v8i32 = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <8 x i32> %v8i32
-}
-
-define <16 x i32> @v8i32_2(<8 x i32> %a, <8 x i32> %b) {
-; CHECK-LABEL: v8i32_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vmv2r.v v16, v10
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vid.v v10
-; CHECK-NEXT: vrsub.vi v18, v10, 15
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v12, v8, v18
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vrsub.vi v8, v10, 7
-; CHECK-NEXT: li a0, 255
-; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v12, v16, v8, v0.t
-; CHECK-NEXT: vmv.v.v v8, v12
-; CHECK-NEXT: ret
- %v16i32 = shufflevector <8 x i32> %a, <8 x i32> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <16 x i32> %v16i32
-}
-
-define <16 x i32> @v16i32(<16 x i32> %a) {
-; CHECK-LABEL: v16i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vid.v v12
-; CHECK-NEXT: vrsub.vi v16, v12, 15
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v12, v8, v16
-; CHECK-NEXT: vmv.v.v v8, v12
-; CHECK-NEXT: ret
- %v16i32 = shufflevector <16 x i32> %a, <16 x i32> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <16 x i32> %v16i32
-}
-
-define <32 x i32> @v16i32_2(<16 x i32> %a, <16 x i32> %b) {
-; CHECK-LABEL: v16i32_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vmv4r.v v24, v12
-; CHECK-NEXT: vmv4r.v v16, v8
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vid.v v20
-; CHECK-NEXT: li a0, 31
-; CHECK-NEXT: vrsub.vx v28, v20, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v8, v16, v28
-; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vrsub.vi v16, v20, 15
-; CHECK-NEXT: lui a0, 16
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: vrgatherei16.vv v8, v24, v16, v0.t
-; CHECK-NEXT: ret
- %v32i32 = shufflevector <16 x i32> %a, <16 x i32> %b, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <32 x i32> %v32i32
-}
-
-define <2 x i64> @v2i64(<2 x i64> %a) {
-; CHECK-LABEL: v2i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v9, v8, 1
-; CHECK-NEXT: vslideup.vi v9, v8, 1
-; CHECK-NEXT: vmv.v.v v8, v9
-; CHECK-NEXT: ret
- %v2i64 = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
- ret <2 x i64> %v2i64
-}
-
-define <4 x i64> @v2i64_2(<2 x i64> %a, < 2 x i64> %b) {
-; CHECK-LABEL: v2i64_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v10, v8, 1
-; CHECK-NEXT: vslideup.vi v10, v8, 1
-; CHECK-NEXT: vslidedown.vi v8, v9, 1
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 2
-; CHECK-NEXT: ret
- %v4i64 = shufflevector <2 x i64> %a, <2 x i64> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
- ret <4 x i64> %v4i64
-}
-
-define <4 x i64> @v4i64(<4 x i64> %a) {
-; CHECK-LABEL: v4i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vid.v v10
-; CHECK-NEXT: vrsub.vi v12, v10, 3
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
-; CHECK-NEXT: vmv.v.v v8, v10
-; CHECK-NEXT: ret
- %v4i64 = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
- ret <4 x i64> %v4i64
-}
-
-define <8 x i64> @v4i64_2(<4 x i64> %a, <4 x i64> %b) {
-; CHECK-LABEL: v4i64_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vmv2r.v v16, v10
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vid.v v10
-; CHECK-NEXT: vrsub.vi v11, v10, 7
-; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v12, v8, v11
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT: vrsub.vi v8, v10, 3
-; CHECK-NEXT: vmv.v.i v0, 15
-; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v12, v16, v8, v0.t
-; CHECK-NEXT: vmv.v.v v8, v12
-; CHECK-NEXT: ret
- %v8i64 = shufflevector <4 x i64> %a, <4 x i64> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <8 x i64> %v8i64
-}
-
-define <2 x half> @v2f16(<2 x half> %a) {
-; CHECK-LABEL: v2f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v9, v8, 1
-; CHECK-NEXT: vslideup.vi v9, v8, 1
-; CHECK-NEXT: vmv1r.v v8, v9
-; CHECK-NEXT: ret
- %v2f16 = shufflevector <2 x half> %a, <2 x half> undef, <2 x i32> <i32 1, i32 0>
- ret <2 x half> %v2f16
-}
-
-define <4 x half> @v2f16_2(<2 x half> %a, <2 x half> %b) {
-; CHECK-LABEL: v2f16_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v10, v8, 1
-; CHECK-NEXT: vslideup.vi v10, v8, 1
-; CHECK-NEXT: vslidedown.vi v8, v9, 1
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 2
-; CHECK-NEXT: ret
- %v4f16 = shufflevector <2 x half> %a, <2 x half> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
- ret <4 x half> %v4f16
-}
-
-define <4 x half> @v4f16(<4 x half> %a) {
-; CHECK-LABEL: v4f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vid.v v9
-; CHECK-NEXT: vrsub.vi v10, v9, 3
-; CHECK-NEXT: vrgather.vv v9, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v9
-; CHECK-NEXT: ret
- %v4f16 = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
- ret <4 x half> %v4f16
-}
-
-define <8 x half> @v4f16_2(<4 x half> %a, <4 x half> %b) {
-; CHECK-LABEL: v4f16_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vid.v v11
-; CHECK-NEXT: vrsub.vi v12, v11, 7
-; CHECK-NEXT: vrgather.vv v10, v8, v12
-; CHECK-NEXT: vmv.v.i v0, 15
-; CHECK-NEXT: vrsub.vi v8, v11, 3
-; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
-; CHECK-NEXT: vmv.v.v v8, v10
-; CHECK-NEXT: ret
- %v8f16 = shufflevector <4 x half> %a, <4 x half> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <8 x half> %v8f16
-}
-
-define <8 x half> @v8f16(<8 x half> %a) {
-; CHECK-LABEL: v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vid.v v9
-; CHECK-NEXT: vrsub.vi v10, v9, 7
-; CHECK-NEXT: vrgather.vv v9, v8, v10
-; CHECK-NEXT: vmv.v.v v8, v9
-; CHECK-NEXT: ret
- %v8f16 = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <8 x half> %v8f16
-}
-
-define <16 x half> @v8f16_2(<8 x half> %a, <8 x half> %b) {
-; CHECK-LABEL: v8f16_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v12, v9
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vid.v v14
-; CHECK-NEXT: vrsub.vi v16, v14, 15
-; CHECK-NEXT: vrgather.vv v10, v8, v16
-; CHECK-NEXT: vrsub.vi v8, v14, 7
-; CHECK-NEXT: li a0, 255
-; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: vrgather.vv v10, v12, v8, v0.t
-; CHECK-NEXT: vmv.v.v v8, v10
-; CHECK-NEXT: ret
- %v16f16 = shufflevector <8 x half> %a, <8 x half> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <16 x half> %v16f16
-}
-
-define <16 x half> @v16f16(<16 x half> %a) {
-; CHECK-LABEL: v16f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vid.v v10
-; CHECK-NEXT: vrsub.vi v12, v10, 15
-; CHECK-NEXT: vrgather.vv v10, v8, v12
-; CHECK-NEXT: vmv.v.v v8, v10
-; CHECK-NEXT: ret
- %v16f16 = shufflevector <16 x half> %a, <16 x half> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <16 x half> %v16f16
-}
-
-define <32 x half> @v16f16_2(<16 x half> %a) {
-; CHECK-LABEL: v16f16_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vid.v v12
-; CHECK-NEXT: li a0, 31
-; CHECK-NEXT: vrsub.vx v16, v12, a0
-; CHECK-NEXT: vrgather.vv v12, v8, v16
-; CHECK-NEXT: vmv.v.v v8, v12
-; CHECK-NEXT: ret
- %v32f16 = shufflevector <16 x half> %a, <16 x half> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <32 x half> %v32f16
-}
-
-define <2 x float> @v2f32(<2 x float> %a) {
-; CHECK-LABEL: v2f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vi v9, v8, 1
-; CHECK-NEXT: vslideup.vi v9, v8, 1
-; CHECK-NEXT: vmv1r.v v8, v9
-; CHECK-NEXT: ret
- %v2f32 = shufflevector <2 x float> %a, <2 x float> undef, <2 x i32> <i32 1, i32 0>
- ret <2 x float> %v2f32
-}
-
-define <4 x float> @v2f32_2(<2 x float> %a, <2 x float> %b) {
-; CHECK-LABEL: v2f32_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vi v10, v8, 1
-; CHECK-NEXT: vslideup.vi v10, v8, 1
-; CHECK-NEXT: vslidedown.vi v8, v9, 1
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 2
-; CHECK-NEXT: ret
- %v4f32 = shufflevector <2 x float> %a, <2 x float> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
- ret <4 x float> %v4f32
-}
-
-define <4 x float> @v4f32(<4 x float> %a) {
-; CHECK-LABEL: v4f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vid.v v9
-; CHECK-NEXT: vrsub.vi v10, v9, 3
-; CHECK-NEXT: vrgather.vv v9, v8, v10
-; CHECK-NEXT: vmv.v.v v8, v9
-; CHECK-NEXT: ret
- %v4f32 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
- ret <4 x float> %v4f32
-}
-
-define <8 x float> @v4f32_2(<4 x float> %a, <4 x float> %b) {
-; CHECK-LABEL: v4f32_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v12, v9
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vid.v v9
-; CHECK-NEXT: vrsub.vi v13, v9, 7
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v10, v8, v13
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT: vrsub.vi v8, v9, 3
-; CHECK-NEXT: vmv.v.i v0, 15
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v10, v12, v8, v0.t
-; CHECK-NEXT: vmv.v.v v8, v10
-; CHECK-NEXT: ret
- %v8f32 = shufflevector <4 x float> %a, <4 x float> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <8 x float> %v8f32
-}
-
-define <8 x float> @v8f32(<8 x float> %a) {
-; CHECK-LABEL: v8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vid.v v10
-; CHECK-NEXT: vrsub.vi v12, v10, 7
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
-; CHECK-NEXT: vmv.v.v v8, v10
-; CHECK-NEXT: ret
- %v8f32 = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <8 x float> %v8f32
-}
-
-define <16 x float> @v8f32_2(<8 x float> %a, <8 x float> %b) {
-; CHECK-LABEL: v8f32_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vmv2r.v v16, v10
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vid.v v10
-; CHECK-NEXT: vrsub.vi v18, v10, 15
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v12, v8, v18
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vrsub.vi v8, v10, 7
-; CHECK-NEXT: li a0, 255
-; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v12, v16, v8, v0.t
-; CHECK-NEXT: vmv.v.v v8, v12
-; CHECK-NEXT: ret
- %v16f32 = shufflevector <8 x float> %a, <8 x float> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <16 x float> %v16f32
-}
-
-define <2 x double> @v2f64(<2 x double> %a) {
-; CHECK-LABEL: v2f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v9, v8, 1
-; CHECK-NEXT: vslideup.vi v9, v8, 1
-; CHECK-NEXT: vmv.v.v v8, v9
-; CHECK-NEXT: ret
- %v2f64 = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> <i32 1, i32 0>
- ret <2 x double> %v2f64
-}
-
-define <4 x double> @v2f64_2(<2 x double> %a, < 2 x double> %b) {
-; CHECK-LABEL: v2f64_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v10, v8, 1
-; CHECK-NEXT: vslideup.vi v10, v8, 1
-; CHECK-NEXT: vslidedown.vi v8, v9, 1
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 2
-; CHECK-NEXT: ret
- %v4f64 = shufflevector <2 x double> %a, <2 x double> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
- ret <4 x double> %v4f64
-}
-
-define <4 x double> @v4f64(<4 x double> %a) {
-; CHECK-LABEL: v4f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vid.v v10
-; CHECK-NEXT: vrsub.vi v12, v10, 3
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
-; CHECK-NEXT: vmv.v.v v8, v10
-; CHECK-NEXT: ret
- %v4f64 = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
- ret <4 x double> %v4f64
-}
-
-define <8 x double> @v4f64_2(<4 x double> %a, <4 x double> %b) {
-; CHECK-LABEL: v4f64_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vmv2r.v v16, v10
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vid.v v10
-; CHECK-NEXT: vrsub.vi v11, v10, 7
-; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v12, v8, v11
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT: vrsub.vi v8, v10, 3
-; CHECK-NEXT: vmv.v.i v0, 15
-; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v12, v16, v8, v0.t
-; CHECK-NEXT: vmv.v.v v8, v12
-; CHECK-NEXT: ret
- %v8f64 = shufflevector <4 x double> %a, <4 x double> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <8 x double> %v8f64
-}
-
-define <32 x i8> @v32i8(<32 x i8> %a) {
-; CHECK-LABEL: v32i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vid.v v10
-; CHECK-NEXT: li a0, 31
-; CHECK-NEXT: vrsub.vx v12, v10, a0
-; CHECK-NEXT: vrgather.vv v10, v8, v12
-; CHECK-NEXT: vmv.v.v v8, v10
-; CHECK-NEXT: ret
- %v32i8 = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <32 x i8> %v32i8
-}
-
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; RV32: {{.*}}
-; RV64: {{.*}}
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