[llvm] ac92dcc - [RISCV] Lower fixed reverse vector_shuffles through vector_reverse (#104461)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 15 22:26:35 PDT 2024
Author: Luke Lau
Date: 2024-08-16T13:26:30+08:00
New Revision: ac92dcc7562ca1c0b1ee84bcc678738aefbe5c18
URL: https://github.com/llvm/llvm-project/commit/ac92dcc7562ca1c0b1ee84bcc678738aefbe5c18
DIFF: https://github.com/llvm/llvm-project/commit/ac92dcc7562ca1c0b1ee84bcc678738aefbe5c18.diff
LOG: [RISCV] Lower fixed reverse vector_shuffles through vector_reverse (#104461)
This teaches lowerVECTOR_REVERSE to handle fixed length vectors, and
then lowers reverse vector_shuffles through it.
The motiviation for this is to allow fixed length vectors to share a
potential optimization on vector_reverse in an upcoming patch (splitting
up LMUL > 1 vrgathers.vv)
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 515d7dbcd47bd9..434f22bb9c8df3 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1087,8 +1087,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR}, VT,
Custom);
- setOperationAction({ISD::BUILD_VECTOR, ISD::CONCAT_VECTORS}, VT,
- Custom);
+ setOperationAction(
+ {ISD::BUILD_VECTOR, ISD::CONCAT_VECTORS, ISD::VECTOR_REVERSE}, VT,
+ Custom);
setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT},
VT, Custom);
@@ -1235,8 +1236,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
// expansion to a build_vector of 0s.
setOperationAction(ISD::UNDEF, VT, Custom);
- setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR,
- ISD::EXTRACT_SUBVECTOR},
+ setOperationAction({ISD::CONCAT_VECTORS, ISD::VECTOR_REVERSE,
+ ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR},
VT, Custom);
// FIXME: mload, mstore, mgather, mscatter, vp_load/store,
@@ -5160,6 +5161,9 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
return convertFromScalableVector(VT, Res, DAG, Subtarget);
}
+ if (ShuffleVectorInst::isReverseMask(Mask, NumElts) && V2.isUndef())
+ return DAG.getNode(ISD::VECTOR_REVERSE, DL, VT, V1);
+
// If this is a deinterleave and we can widen the vector, then we can use
// vnsrl to deinterleave.
if (isDeinterleaveShuffle(VT, ContainerVT, V1, V2, Mask, Subtarget)) {
@@ -10308,14 +10312,24 @@ SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,
SDValue Op2 = DAG.getNode(ISD::VECTOR_REVERSE, DL, WidenVT, Op1);
return DAG.getNode(ISD::TRUNCATE, DL, VecVT, Op2);
}
- unsigned EltSize = VecVT.getScalarSizeInBits();
- unsigned MinSize = VecVT.getSizeInBits().getKnownMinValue();
+
+ MVT ContainerVT = VecVT;
+ SDValue Vec = Op.getOperand(0);
+ if (VecVT.isFixedLengthVector()) {
+ ContainerVT = getContainerForFixedLengthVector(VecVT);
+ Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget);
+ }
+
+ unsigned EltSize = ContainerVT.getScalarSizeInBits();
+ unsigned MinSize = ContainerVT.getSizeInBits().getKnownMinValue();
unsigned VectorBitsMax = Subtarget.getRealMaxVLen();
unsigned MaxVLMAX =
- RISCVTargetLowering::computeVLMAX(VectorBitsMax, EltSize, MinSize);
+ VecVT.isFixedLengthVector()
+ ? VecVT.getVectorNumElements()
+ : RISCVTargetLowering::computeVLMAX(VectorBitsMax, EltSize, MinSize);
unsigned GatherOpc = RISCVISD::VRGATHER_VV_VL;
- MVT IntVT = VecVT.changeVectorElementTypeToInteger();
+ MVT IntVT = ContainerVT.changeVectorElementTypeToInteger();
// If this is SEW=8 and VLMAX is potentially more than 256, we need
// to use vrgatherei16.vv.
@@ -10340,7 +10354,7 @@ SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,
}
// Just promote the int type to i16 which will double the LMUL.
- IntVT = MVT::getVectorVT(MVT::i16, VecVT.getVectorElementCount());
+ IntVT = MVT::getVectorVT(MVT::i16, ContainerVT.getVectorElementCount());
GatherOpc = RISCVISD::VRGATHEREI16_VV_VL;
}
@@ -10354,12 +10368,13 @@ SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,
}
MVT XLenVT = Subtarget.getXLenVT();
- auto [Mask, VL] = getDefaultScalableVLOps(VecVT, DL, DAG, Subtarget);
+ auto [Mask, VL] = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget);
// Calculate VLMAX-1 for the desired SEW.
- SDValue VLMinus1 = DAG.getNode(ISD::SUB, DL, XLenVT,
- computeVLMax(VecVT, DL, DAG),
- DAG.getConstant(1, DL, XLenVT));
+ SDValue VLMinus1 = DAG.getNode(
+ ISD::SUB, DL, XLenVT,
+ DAG.getElementCount(DL, XLenVT, VecVT.getVectorElementCount()),
+ DAG.getConstant(1, DL, XLenVT));
// Splat VLMAX-1 taking care to handle SEW==64 on RV32.
bool IsRV32E64 =
@@ -10375,8 +10390,11 @@ SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,
SDValue Indices = DAG.getNode(RISCVISD::SUB_VL, DL, IntVT, SplatVL, VID,
DAG.getUNDEF(IntVT), Mask, VL);
- return DAG.getNode(GatherOpc, DL, VecVT, Op.getOperand(0), Indices,
- DAG.getUNDEF(VecVT), Mask, VL);
+ SDValue Gather = DAG.getNode(GatherOpc, DL, ContainerVT, Vec, Indices,
+ DAG.getUNDEF(ContainerVT), Mask, VL);
+ if (VecVT.isFixedLengthVector())
+ Gather = convertFromScalableVector(VecVT, Gather, DAG, Subtarget);
+ return Gather;
}
SDValue RISCVTargetLowering::lowerVECTOR_SPLICE(SDValue Op,
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
index 4b1f0beb487008..d6e66577fa97a7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
@@ -101,10 +101,10 @@ define <32 x i1> @reverse_v32i1(<32 x i1> %a) {
; NO-ZVBB-LABEL: reverse_v32i1:
; NO-ZVBB: # %bb.0:
; NO-ZVBB-NEXT: li a0, 32
-; NO-ZVBB-NEXT: lui a1, %hi(.LCPI4_0)
-; NO-ZVBB-NEXT: addi a1, a1, %lo(.LCPI4_0)
; NO-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; NO-ZVBB-NEXT: vle8.v v8, (a1)
+; NO-ZVBB-NEXT: vid.v v8
+; NO-ZVBB-NEXT: li a0, 31
+; NO-ZVBB-NEXT: vrsub.vx v8, v8, a0
; NO-ZVBB-NEXT: vmv.v.i v10, 0
; NO-ZVBB-NEXT: vmerge.vim v10, v10, 1, v0
; NO-ZVBB-NEXT: vrgather.vv v12, v10, v8
@@ -124,10 +124,10 @@ define <64 x i1> @reverse_v64i1(<64 x i1> %a) {
; NO-ZVBB-LABEL: reverse_v64i1:
; NO-ZVBB: # %bb.0:
; NO-ZVBB-NEXT: li a0, 64
-; NO-ZVBB-NEXT: lui a1, %hi(.LCPI5_0)
-; NO-ZVBB-NEXT: addi a1, a1, %lo(.LCPI5_0)
; NO-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; NO-ZVBB-NEXT: vle8.v v8, (a1)
+; NO-ZVBB-NEXT: vid.v v8
+; NO-ZVBB-NEXT: li a0, 63
+; NO-ZVBB-NEXT: vrsub.vx v8, v8, a0
; NO-ZVBB-NEXT: vmv.v.i v12, 0
; NO-ZVBB-NEXT: vmerge.vim v12, v12, 1, v0
; NO-ZVBB-NEXT: vrgather.vv v16, v12, v8
@@ -147,10 +147,10 @@ define <128 x i1> @reverse_v128i1(<128 x i1> %a) {
; CHECK-LABEL: reverse_v128i1:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 128
-; CHECK-NEXT: lui a1, %hi(.LCPI6_0)
-; CHECK-NEXT: addi a1, a1, %lo(.LCPI6_0)
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vle8.v v8, (a1)
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: li a0, 127
+; CHECK-NEXT: vrsub.vx v8, v8, a0
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
; CHECK-NEXT: vrgather.vv v24, v16, v8
@@ -229,10 +229,10 @@ define <32 x i8> @reverse_v32i8(<32 x i8> %a) {
; CHECK-LABEL: reverse_v32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: lui a1, %hi(.LCPI12_0)
-; CHECK-NEXT: addi a1, a1, %lo(.LCPI12_0)
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vle8.v v12, (a1)
+; CHECK-NEXT: vid.v v10
+; CHECK-NEXT: li a0, 31
+; CHECK-NEXT: vrsub.vx v12, v10, a0
; CHECK-NEXT: vrgather.vv v10, v8, v12
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
@@ -244,10 +244,10 @@ define <64 x i8> @reverse_v64i8(<64 x i8> %a) {
; CHECK-LABEL: reverse_v64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 64
-; CHECK-NEXT: lui a1, %hi(.LCPI13_0)
-; CHECK-NEXT: addi a1, a1, %lo(.LCPI13_0)
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vle8.v v16, (a1)
+; CHECK-NEXT: vid.v v12
+; CHECK-NEXT: li a0, 63
+; CHECK-NEXT: vrsub.vx v16, v12, a0
; CHECK-NEXT: vrgather.vv v12, v8, v16
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
@@ -324,11 +324,10 @@ define <32 x i16> @reverse_v32i16(<32 x i16> %a) {
; CHECK-LABEL: reverse_v32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: lui a1, %hi(.LCPI19_0)
-; CHECK-NEXT: addi a1, a1, %lo(.LCPI19_0)
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vle8.v v12, (a1)
-; CHECK-NEXT: vsext.vf2 v16, v12
+; CHECK-NEXT: vid.v v12
+; CHECK-NEXT: li a0, 31
+; CHECK-NEXT: vrsub.vx v16, v12, a0
; CHECK-NEXT: vrgather.vv v12, v8, v16
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
@@ -521,11 +520,10 @@ define <32 x half> @reverse_v32f16(<32 x half> %a) {
; CHECK-LABEL: reverse_v32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: lui a1, %hi(.LCPI34_0)
-; CHECK-NEXT: addi a1, a1, %lo(.LCPI34_0)
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vle8.v v12, (a1)
-; CHECK-NEXT: vsext.vf2 v16, v12
+; CHECK-NEXT: vid.v v12
+; CHECK-NEXT: li a0, 31
+; CHECK-NEXT: vrsub.vx v16, v12, a0
; CHECK-NEXT: vrgather.vv v12, v8, v16
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
index 368f454fa5fda1..9e62bb623a03bd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
@@ -106,21 +106,20 @@ define <16 x i8> @v16i8(<16 x i8> %a) {
define <32 x i8> @v16i8_2(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: v16i8_2:
; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v12, v9
; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: lui a1, %hi(.LCPI7_0)
-; CHECK-NEXT: addi a1, a1, %lo(.LCPI7_0)
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vle8.v v12, (a1)
-; CHECK-NEXT: vmv1r.v v14, v9
-; CHECK-NEXT: vrgather.vv v10, v8, v12
-; CHECK-NEXT: vid.v v8
-; CHECK-NEXT: vrsub.vi v8, v8, 15
+; CHECK-NEXT: vid.v v14
+; CHECK-NEXT: li a0, 31
+; CHECK-NEXT: vrsub.vx v16, v14, a0
+; CHECK-NEXT: vrgather.vv v10, v8, v16
+; CHECK-NEXT: vrsub.vi v8, v14, 15
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, mu
-; CHECK-NEXT: vrgather.vv v10, v14, v8, v0.t
+; CHECK-NEXT: vrgather.vv v10, v12, v8, v0.t
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
%v32i8 = shufflevector <16 x i8> %a, <16 x i8> %b, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
@@ -230,22 +229,21 @@ define <16 x i16> @v16i16(<16 x i16> %a) {
define <32 x i16> @v16i16_2(<16 x i16> %a, <16 x i16> %b) {
; CHECK-LABEL: v16i16_2:
; CHECK: # %bb.0:
+; CHECK-NEXT: vmv2r.v v16, v10
; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: lui a1, %hi(.LCPI15_0)
-; CHECK-NEXT: addi a1, a1, %lo(.LCPI15_0)
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vle16.v v16, (a1)
-; CHECK-NEXT: vmv2r.v v20, v10
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vrgather.vv v8, v12, v16
-; CHECK-NEXT: vid.v v12
-; CHECK-NEXT: vrsub.vi v12, v12, 15
+; CHECK-NEXT: vid.v v20
+; CHECK-NEXT: li a0, 31
+; CHECK-NEXT: vrsub.vx v24, v20, a0
+; CHECK-NEXT: vrgather.vv v12, v8, v24
+; CHECK-NEXT: vrsub.vi v8, v20, 15
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, mu
-; CHECK-NEXT: vrgather.vv v8, v20, v12, v0.t
+; CHECK-NEXT: vrgather.vv v12, v16, v8, v0.t
+; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
%v32i16 = shufflevector <16 x i16> %a, <16 x i16> %b, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <32 x i16> %v32i16
@@ -363,17 +361,17 @@ define <16 x i32> @v16i32(<16 x i32> %a) {
define <32 x i32> @v16i32_2(<16 x i32> %a, <16 x i32> %b) {
; CHECK-LABEL: v16i32_2:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: lui a1, %hi(.LCPI23_0)
-; CHECK-NEXT: addi a1, a1, %lo(.LCPI23_0)
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vle16.v v20, (a1)
; CHECK-NEXT: vmv4r.v v24, v12
; CHECK-NEXT: vmv4r.v v16, v8
-; CHECK-NEXT: vrgatherei16.vv v8, v16, v20
+; CHECK-NEXT: li a0, 32
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: vid.v v20
+; CHECK-NEXT: li a0, 31
+; CHECK-NEXT: vrsub.vx v28, v20, a0
+; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; CHECK-NEXT: vrgatherei16.vv v8, v16, v28
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vid.v v16
-; CHECK-NEXT: vrsub.vi v16, v16, 15
+; CHECK-NEXT: vrsub.vi v16, v20, 15
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -549,10 +547,10 @@ define <32 x half> @v16f16_2(<16 x half> %a) {
; CHECK-LABEL: v16f16_2:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: lui a1, %hi(.LCPI35_0)
-; CHECK-NEXT: addi a1, a1, %lo(.LCPI35_0)
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vle16.v v16, (a1)
+; CHECK-NEXT: vid.v v12
+; CHECK-NEXT: li a0, 31
+; CHECK-NEXT: vrsub.vx v16, v12, a0
; CHECK-NEXT: vrgather.vv v12, v8, v16
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
@@ -720,10 +718,10 @@ define <32 x i8> @v32i8(<32 x i8> %a) {
; CHECK-LABEL: v32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: lui a1, %hi(.LCPI46_0)
-; CHECK-NEXT: addi a1, a1, %lo(.LCPI46_0)
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vle8.v v12, (a1)
+; CHECK-NEXT: vid.v v10
+; CHECK-NEXT: li a0, 31
+; CHECK-NEXT: vrsub.vx v12, v10, a0
; CHECK-NEXT: vrgather.vv v10, v8, v12
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
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