[llvm] [AMDGPU][True16][MC] 16bit operand support in asm/disasm (PR #104510)

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``````````bash
git-clang-format --diff eae1d65f3435b1399e1468cb27bfe745f95d4df2 3bf43638265874282d5ffb77ae12230f7628f18b --extensions cpp -- llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index fd10e02025..6181a36b01 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -2174,7 +2174,8 @@ bool AMDGPUOperand::isVRegWithInputMods() const {
           AsmParser->getFeatureBits()[AMDGPU::FeatureDPALU_DPP]);
 }
 
-template <bool IsFake16> bool AMDGPUOperand::isT16_Lo128VRegWithInputMods() const {
+template <bool IsFake16>
+bool AMDGPUOperand::isT16_Lo128VRegWithInputMods() const {
   return isRegClass(IsFake16 ? AMDGPU::VGPR_32_Lo128RegClassID
                              : AMDGPU::VGPR_16_Lo128RegClassID);
 }
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index ada6c3f263..9295ec77c5 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -342,8 +342,8 @@ static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm,
     return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
   }
   return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(
-                               OpWidth, Imm & 0xFF, false, ImmWidth,
-                               (AMDGPU::OperandSemantics)OperandSemantics));
+                              OpWidth, Imm & 0xFF, false, ImmWidth,
+                              (AMDGPU::OperandSemantics)OperandSemantics));
 }
 
 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
@@ -360,8 +360,8 @@ static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm,
     return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
   }
   return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(
-                               OpWidth, Imm & 0xFF, false, ImmWidth,
-                               (AMDGPU::OperandSemantics)OperandSemantics));
+                              OpWidth, Imm & 0xFF, false, ImmWidth,
+                              (AMDGPU::OperandSemantics)OperandSemantics));
 }
 
 static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm,

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https://github.com/llvm/llvm-project/pull/104510