[llvm] [RISCV] Gate CSR defined by experimental and vendor extensions (PR #104424)

Jesse Huang via llvm-commits llvm-commits at lists.llvm.org
Thu Aug 15 10:38:39 PDT 2024


================
@@ -351,7 +364,10 @@ def SysRegVLENB: SysReg<"vlenb", 0xC22>;
 //===----------------------------------------------------------------------===//
 // Shadow Stack CSR
 //===----------------------------------------------------------------------===//
-def : SysReg<"ssp", 0x011>;
+
+let FeaturesRequired = [{ {RISCV::FeatureStdExtZicfiss} }] in {
+  def : SysReg<"ssp", 0x011>;
----------------
jaidTw wrote:

I see your point, while we don't have any CSR that is unratified now, so I simply think it's a way to show how things work in the code. Else this patch turns into a error message update and we should consider document or comment it somewhere for developers to notice

https://github.com/llvm/llvm-project/pull/104424


More information about the llvm-commits mailing list