[llvm] [DAG] Support saturated truncate (PR #99418)

[Craig Topper via llvm-commits]

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@@ -8279,11 +8287,18 @@ SDValue RISCVTargetLowering::lowerVectorTruncLike(SDValue Op,
         getDefaultVLOps(SrcVT, ContainerVT, DL, DAG, Subtarget);
   }
 
+  unsigned NewOpc;
+  if (Opc == ISD::TRUNCATE_SSAT_S)
+    NewOpc = RISCVISD::TRUNCATE_VECTOR_VL_SSAT;
+  else if (Opc == ISD::TRUNCATE_SSAT_U || Opc == ISD::TRUNCATE_USAT_U)
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topperc wrote:

How are we lowering 2 differnet opcodes to the same RISC-V instruction?

https://github.com/llvm/llvm-project/pull/99418