[llvm] [RISCV] Gate CSR defined by experimental and vendor extensions (PR #104424)

[Craig Topper via llvm-commits]

================
@@ -351,7 +364,10 @@ def SysRegVLENB: SysReg<"vlenb", 0xC22>;
 //===----------------------------------------------------------------------===//
 // Shadow Stack CSR
 //===----------------------------------------------------------------------===//
-def : SysReg<"ssp", 0x011>;
+
+let FeaturesRequired = [{ {RISCV::FeatureStdExtZicfiss} }] in {
+  def : SysReg<"ssp", 0x011>;
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topperc wrote:

The extension is experimental in LLVM due to incomplete implementation of CodeGen support for Zicfiss. The extension itself is ratified so the CSR address is frozen. Should we consider assembly support for Zicfiss as non-experimental?

https://github.com/llvm/llvm-project/pull/104424