[llvm] tmp (PR #104449)
Brox Chen via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 15 07:53:18 PDT 2024
https://github.com/broxigarchen created https://github.com/llvm/llvm-project/pull/104449
None
>From d699c66b628e190dff6e1a0f5c7d564249c0bf7f Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Thu, 15 Aug 2024 10:52:48 -0400
Subject: [PATCH] tmp
---
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 158 +++++++++++---
llvm/lib/Target/AMDGPU/SIInstructions.td | 2 +-
llvm/lib/Target/AMDGPU/VOP1Instructions.td | 92 ++++----
llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s | 174 +++++++--------
.../MC/AMDGPU/gfx11_asm_vop1_t16_promote.s | 201 +++++++++---------
5 files changed, 365 insertions(+), 262 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index e99b43afd1c3a2..b31c86a114a5b9 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -1207,9 +1207,11 @@ class FPVCSrcInputModsMatchClass <int opSize> : FPInputModsMatchClass <opSize> {
}
def FP16InputModsMatchClass : FPInputModsMatchClass<16>;
-def FPT16InputModsMatchClass : FPInputModsMatchClass<16> {
- let Name = "RegOrImmWithFPT16InputMods";
- let PredicateMethod = "isRegOrImmWithFPT16InputMods";
+class FPT16InputModsMatchClass<bit IsFake16> : FPInputModsMatchClass<16> {
+ let Name = !if(IsFake16, "RegOrImmWithFPFake16InputMods",
+ "RegOrImmWithFPT16InputMods");
+ let PredicateMethod = "isRegOrImmWithFPT16InputMods<" #
+ !if(IsFake16, "true", "false") # ">";
}
def FP32InputModsMatchClass : FPInputModsMatchClass<32>;
def FP64InputModsMatchClass : FPInputModsMatchClass<64>;
@@ -1234,12 +1236,19 @@ class FPInputMods <FPInputModsMatchClass matchClass> : InputMods <matchClass> {
}
def FP16InputMods : FPInputMods<FP16InputModsMatchClass>;
-def FPT16InputMods : FPInputMods<FPT16InputModsMatchClass>;
+class FPT16InputMods<bit IsFake16> : FPInputMods<FPT16InputModsMatchClass<IsFake16>> {
+ let EncoderMethod = "getMachineOpValueT16";
+}
def FP32InputMods : FPInputMods<FP32InputModsMatchClass>;
+def FP32T16DstInputMods : FPInputMods<FP32InputModsMatchClass> {
+ let EncoderMethod = "getMachineOpValueT16";
+}
def FP64InputMods : FPInputMods<FP64InputModsMatchClass>;
-class FP16VCSrcInputMods<bit IsFake16>
- : FPInputMods<FP16VCSrcInputModsMatchClass<IsFake16>>;
+class FPT16VCSrcInputMods<bit IsFake16 = 0>
+ : FPInputMods<FP16VCSrcInputModsMatchClass<IsFake16>> {
+let EncoderMethod = "getMachineOpValueT16";
+}
def FP32VCSrcInputMods : FPInputMods<FP32VCSrcInputModsMatchClass>;
class IntInputModsMatchClass <int opSize> : AsmOperandClass {
@@ -1251,21 +1260,38 @@ class IntVCSrcInputModsMatchClass <int opSize> : IntInputModsMatchClass <opSize>
let Name = "RegOrInlineImmWithInt"#opSize#"InputMods";
let PredicateMethod = "isRegOrInlineImmWithInt"#opSize#"InputMods";
}
-def IntT16InputModsMatchClass : IntInputModsMatchClass<16> {
- let Name = "RegOrImmWithIntT16InputMods";
- let PredicateMethod = "isRegOrImmWithIntT16InputMods";
+class IntT16InputModsMatchClass<bit IsFake16> : IntInputModsMatchClass<16> {
+ let Name = !if(IsFake16, "RegOrImmWithIntFake16InputMods",
+ "RegOrImmWithIntT16InputMods");
+ let PredicateMethod = "isRegOrImmWithIntT16InputMods<" #
+ !if(IsFake16, "true", "false") # ">";
}
def Int32InputModsMatchClass : IntInputModsMatchClass<32>;
def Int64InputModsMatchClass : IntInputModsMatchClass<64>;
def Int32VCSrcInputModsMatchClass : IntVCSrcInputModsMatchClass<32>;
+class IntT16VCSrcInputModsMatchClass<bit IsFake16> : IntInputModsMatchClass<16> {
+ let Name = !if(IsFake16, "RegOrInlineImmWithIntFake16InputMods",
+ "RegOrInlineImmWithIntT16InputMods");
+ let PredicateMethod = "isRegOrInlineImmWithIntT16InputMods<" #
+ !if(IsFake16, "true", "false") # ">";
+}
class IntInputMods <IntInputModsMatchClass matchClass> : InputMods <matchClass> {
let PrintMethod = "printOperandAndIntInputMods";
}
-def IntT16InputMods : IntInputMods<IntT16InputModsMatchClass>;
+class IntT16InputMods<bit IsFake16> : IntInputMods<IntT16InputModsMatchClass<IsFake16>> {
+ let EncoderMethod = "getMachineOpValueT16";
+}
def Int32InputMods : IntInputMods<Int32InputModsMatchClass>;
+def Int32T16DstInputMods : IntInputMods<Int32InputModsMatchClass> {
+ let EncoderMethod = "getMachineOpValueT16";
+}
def Int64InputMods : IntInputMods<Int64InputModsMatchClass>;
def Int32VCSrcInputMods : IntInputMods<Int32VCSrcInputModsMatchClass>;
+class IntT16VCSrcInputMods<bit IsFake16 = 0>
+ : IntInputMods<IntT16VCSrcInputModsMatchClass<IsFake16>> {
+ let EncoderMethod = "getMachineOpValueT16";
+}
class OpSelModsMatchClass : AsmOperandClass {
let Name = "OpSelMods";
@@ -1299,6 +1325,23 @@ def FPVRegInputModsMatchClass : AsmOperandClass {
let PredicateMethod = "isVRegWithInputMods";
}
+def FPVRegInputMods : InputMods <FPVRegInputModsMatchClass> {
+ let PrintMethod = "printOperandAndFPInputMods";
+}
+
+def FPVRegT16DstInputMods : InputMods <FPVRegInputModsMatchClass> {
+ let PrintMethod = "printOperandAndFPInputMods";
+ let EncoderMethod = "getMachineOpValueT16";
+}
+
+class FPT16_Lo128VRegInputModsMatchClass<bit IsFake16> : AsmOperandClass {
+ let Name = !if(IsFake16, "Fake16_Lo128VRegWithFPInputMods",
+ "T16_Lo128VRegWithFPInputMods");
+ let ParserMethod = "parseRegWithFPInputMods";
+ let PredicateMethod = "isT16_Lo128VRegWithInputMods<" #
+ !if(IsFake16, "true", "false") # ">";
+}
+
class FPT16VRegInputModsMatchClass<bit IsFake16> : AsmOperandClass {
let Name = !if(IsFake16, "Fake16VRegWithFPInputMods",
"T16VRegWithFPInputMods");
@@ -1307,13 +1350,16 @@ class FPT16VRegInputModsMatchClass<bit IsFake16> : AsmOperandClass {
!if(IsFake16, "true", "false") # ">";
}
-def FPVRegInputMods : InputMods <FPVRegInputModsMatchClass> {
+class FPT16_Lo128VRegInputMods<bit IsFake16 = 0>
+ : InputMods <FPT16_Lo128VRegInputModsMatchClass<IsFake16>> {
let PrintMethod = "printOperandAndFPInputMods";
+ let EncoderMethod = "getMachineOpValueT16Lo128";
}
-class FPT16VRegInputMods<bit IsFake16>
+class FPT16VRegInputMods<bit IsFake16 = 0>
: InputMods <FPT16VRegInputModsMatchClass<IsFake16>> {
let PrintMethod = "printOperandAndFPInputMods";
+ let EncoderMethod = "getMachineOpValueT16";
}
class IntSDWAInputModsMatchClass <int opSize> : AsmOperandClass {
@@ -1344,7 +1390,15 @@ def IntVRegInputModsMatchClass : AsmOperandClass {
let PredicateMethod = "isVRegWithInputMods";
}
-class IntT16VRegInputModsMatchClass<bit IsFake16> : AsmOperandClass {
+class IntT16_Lo128VRegInputModsMatchClass<bit IsFake16 = 0> : AsmOperandClass {
+ let Name = !if(IsFake16, "Fake16_Lo128VRegWithIntInputMods",
+ "T16_Lo128VRegWithIntInputMods");
+ let ParserMethod = "parseRegWithIntInputMods";
+ let PredicateMethod = "isT16_Lo128VRegWithInputMods<" #
+ !if(IsFake16, "true", "false") # ">";
+}
+
+class IntT16VRegInputModsMatchClass<bit IsFake16 = 0> : AsmOperandClass {
let Name = !if(IsFake16, "Fake16VRegWithIntInputMods",
"T16VRegWithIntInputMods");
let ParserMethod = "parseRegWithIntInputMods";
@@ -1352,15 +1406,27 @@ class IntT16VRegInputModsMatchClass<bit IsFake16> : AsmOperandClass {
!if(IsFake16, "true", "false") # ">";
}
-class IntT16VRegInputMods<bit IsFake16>
+class IntT16_Lo128VRegInputMods<bit IsFake16 = 0>
+ : InputMods <IntT16_Lo128VRegInputModsMatchClass<IsFake16>> {
+ let PrintMethod = "printOperandAndIntInputMods";
+ let EncoderMethod = "getMachineOpValueT16Lo128";
+}
+
+class IntT16VRegInputMods<bit IsFake16 = 0>
: InputMods <IntT16VRegInputModsMatchClass<IsFake16>> {
let PrintMethod = "printOperandAndIntInputMods";
+ let EncoderMethod = "getMachineOpValueT16";
}
def IntVRegInputMods : InputMods <IntVRegInputModsMatchClass> {
let PrintMethod = "printOperandAndIntInputMods";
}
+def IntVRegT16DstInputMods : InputMods <IntVRegInputModsMatchClass> {
+ let PrintMethod = "printOperandAndIntInputMods";
+ let EncoderMethod = "getMachineOpValueT16";
+}
+
class PackedFPInputModsMatchClass <int opSize> : AsmOperandClass {
let Name = "PackedFP"#opSize#"InputMods";
let ParserMethod = "parseRegOrImmWithFPInputMods";
@@ -1559,7 +1625,7 @@ class getSDWADstForVT<ValueType VT> {
// Returns the register class to use for source 0 of VOP[12C]
// instructions for the given VT.
-class getVOPSrc0ForVT<ValueType VT, bit IsTrue16, bit IsFake16 = 1> {
+class getVOPSrc0ForVT<ValueType VT, bit IsTrue16, bit IsFake16 = 0> {
RegisterOperand ret =
!cond(!eq(VT, i64) : VSrc_b64,
!eq(VT, f64) : VSrc_f64,
@@ -1668,16 +1734,28 @@ class isModifierType<ValueType SrcVT> {
!eq(SrcVT.Value, v16bf16.Value));
}
-// Return type of input modifiers operand for specified input operand
-class getSrcMod <ValueType VT, bit IsTrue16 = 0> {
- Operand ret = !if(!eq(VT.Size, 64),
+// Return type of input modifiers operand for specified input operand.
+// True16: If the destination is a 16-bit value, the src0 modifier must hold
+// dst's opsel bit. Use a dummy value for DstVT if getting the mod for a src operand besides 0.
+// 64-bit src types are not implemented for True16 dst.
+class getSrc0Mod <ValueType VT, ValueType DstVT, bit IsTrue16 = 0, bit IsFake16 = 0> {
+ defvar T16Dst = !if(!eq(VT.Size, 64),
+ !if(VT.isFP, FP64InputMods, Int64InputMods),
+ !if(!eq(VT.Size, 16),
+ !if(VT.isFP, !if(IsTrue16, FPT16InputMods<IsFake16>, FP16InputMods),
+ !if(IsTrue16, IntT16InputMods<IsFake16>, IntOpSelMods)),
+ !if(VT.isFP, FP32T16DstInputMods, Int32T16DstInputMods)));
+ defvar Normal = !if(!eq(VT.Size, 64),
!if(VT.isFP, FP64InputMods, Int64InputMods),
!if(!eq(VT.Size, 16),
- !if(VT.isFP, !if(IsTrue16, FPT16InputMods, FP16InputMods),
- !if(IsTrue16, IntT16InputMods, IntOpSelMods)),
+ !if(VT.isFP, !if(IsTrue16, FPT16InputMods<IsFake16>, FP16InputMods),
+ !if(IsTrue16, IntT16InputMods<IsFake16>, IntOpSelMods)),
!if(VT.isFP, FP32InputMods, Int32InputMods)));
+ Operand ret = !if(!and(IsTrue16, !eq(DstVT.Size, 16)), T16Dst, Normal);
}
+class getSrcMod<ValueType VT, bit IsTrue16 = 0, bit IsFake16 = 0> : getSrc0Mod<VT, f128/*Dummy Arg*/, IsTrue16, IsFake16>;
+
class getOpSelMod <ValueType VT> {
Operand ret = !cond(!eq(VT, f16) : FP16InputMods,
!eq(VT, bf16) : FP16InputMods,
@@ -1691,7 +1769,7 @@ class getSrcModDPP <ValueType VT> {
Operand ret = !if(VT.isFP, FPVRegInputMods, IntVRegInputMods);
}
-class getSrcModDPP_t16 <ValueType VT, bit IsFake16 = 1> {
+class getSrcModDPP_t16 <ValueType VT, bit IsFake16 = 0> {
Operand ret =
!if (VT.isFP,
!if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)),
@@ -1701,12 +1779,36 @@ class getSrcModDPP_t16 <ValueType VT, bit IsFake16 = 1> {
}
// Return type of input modifiers operand for specified input operand for DPP
-class getSrcModVOP3DPP <ValueType VT, bit IsFake16 = 1> {
+// True16: If the destination is a 16-bit value, the src0 modifier must hold
+// dst's opsel bit. Use a dummy value for DstVT if getting the mod for a src operand besides 0.
+// 64-bit src types are not implemented for True16 dst.
+class getSrc0ModVOP3DPP <ValueType VT, ValueType DstVT, bit IsFake16 = 0> {
+ defvar T16Dst =
+ !if (VT.isFP,
+ !if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)),
+ FPT16VRegInputMods<IsFake16>, FPVRegT16DstInputMods),
+ !if (!eq(VT.Value, i16.Value), IntT16VRegInputMods<IsFake16>,
+ IntVRegT16DstInputMods));
+ defvar Normal =
+ !if (VT.isFP,
+ !if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)),
+ FPT16VRegInputMods<IsFake16>, FPVRegInputMods),
+ !if (!eq(VT.Value, i16.Value),
+ IntT16VRegInputMods<IsFake16>,
+ IntVRegInputMods));
+ Operand ret = !if(!and(!not(IsFake16), !eq(DstVT.Size, 16)), T16Dst, Normal);
+}
+
+// GFX11 only supports VGPR src1, but the restriction is done in AsmParser
+// and GCNDPPCombine.
+class getSrcModVOP3DPP<ValueType VT, bit IsFake16 = 0> {
Operand ret =
!if (VT.isFP,
!if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)),
- FP16VCSrcInputMods<IsFake16>, FP32VCSrcInputMods),
- Int32VCSrcInputMods);
+ FPT16VCSrcInputMods<IsFake16>, FP32VCSrcInputMods),
+ !if (!eq(VT.Value, i16.Value),
+ IntT16VCSrcInputMods<IsFake16>,
+ Int32VCSrcInputMods));
}
// Return type of input modifiers operand specified input operand for SDWA
@@ -1747,9 +1849,11 @@ class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
(ins Src0Mod:$src0_modifiers, Src0RC:$src0)))
/* else */,
// VOP1 without modifiers
- !if (HasClamp,
- (ins Src0RC:$src0, Clamp0:$clamp),
- (ins Src0RC:$src0))
+ !if(HasOMod,
+ (ins Src0RC:$src0, Clamp0:$clamp, omod0:$omod),
+ !if (HasClamp,
+ (ins Src0RC:$src0, Clamp0:$clamp),
+ (ins Src0RC:$src0)))
/* endif */ ),
!if (!eq(NumSrcArgs, 2),
!if (HasModifiers,
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 5a139d1cf8d825..893c9c10039390 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -1174,7 +1174,7 @@ let SubtargetPredicate = NotHasTrue16BitInsts in
defm : f16_fp_Pats<V_CVT_F16_F32_e64, V_CVT_F32_F16_e64>;
let SubtargetPredicate = HasTrue16BitInsts in
-defm : f16_fp_Pats<V_CVT_F16_F32_t16_e64, V_CVT_F32_F16_t16_e64>;
+defm : f16_fp_Pats<V_CVT_F16_F32_e64, V_CVT_F32_F16_e64>;
//===----------------------------------------------------------------------===//
// VOP2 Patterns
diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index 03e4cb9fcf49b7..13e19bbbdb08e7 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -187,21 +187,17 @@ class VOPProfileI2F<ValueType dstVt, ValueType srcVt> :
let HasClamp = 1;
}
-class VOPProfileI2F_True16<ValueType dstVt, ValueType srcVt> :
- VOPProfile_Fake16<VOPProfile<[dstVt, srcVt, untyped, untyped]>> {
-
- let Ins64 = (ins Src0RC64:$src0, Clamp:$clamp, omod:$omod);
- let InsVOP3Base = (ins Src0VOP3DPP:$src0, Clamp:$clamp, omod:$omod);
- let AsmVOP3Base = "$vdst, $src0$clamp$omod";
-
- let HasModifiers = 0;
- let HasClamp = 1;
-}
-
def VOP1_F64_I32 : VOPProfileI2F <f64, i32>;
def VOP1_F32_I32 : VOPProfileI2F <f32, i32>;
def VOP1_F16_I16 : VOPProfileI2F <f16, i16>;
-def VOP1_F16_I16_t16 : VOPProfileI2F_True16 <f16, i16>;
+def VOP1_F16_I16_t16 : VOPProfile_True16 <VOP1_F16_I16> {
+ let HasClamp = 1;
+}
+def VOP1_F16_I16_fake16 : VOPProfile_Fake16 <VOP1_F16_I16> {
+ let HasModifiers = 0;
+ let HasOMod = 1;
+ let HasClamp = 1;
+}
def VOP_NOP_PROFILE : VOPProfile <[untyped, untyped, untyped, untyped]>{
let HasExtVOP3DPP = 0;
@@ -217,7 +213,10 @@ class VOP_SPECIAL_OMOD_PROF<ValueType dstVt, ValueType srcVt> :
def VOP_I32_F32_SPECIAL_OMOD : VOP_SPECIAL_OMOD_PROF<i32, f32>;
def VOP_I32_F64_SPECIAL_OMOD : VOP_SPECIAL_OMOD_PROF<i32, f64>;
def VOP_I16_F16_SPECIAL_OMOD : VOP_SPECIAL_OMOD_PROF<i16, f16>;
-def VOP_I16_F16_SPECIAL_OMOD_t16 : VOPProfile_Fake16<VOP_I16_F16> {
+def VOP_I16_F16_SPECIAL_OMOD_t16 : VOPProfile_True16<VOP_I16_F16> {
+ let HasOMod = 1;
+}
+def VOP_I16_F16_SPECIAL_OMOD_fake16 : VOPProfile_Fake16<VOP_I16_F16> {
let HasOMod = 1;
}
@@ -294,16 +293,23 @@ defm V_CVT_F32_U32 : VOP1Inst <"v_cvt_f32_u32", VOP1_F32_I32, uint_to_fp>;
defm V_CVT_U32_F32 : VOP1Inst <"v_cvt_u32_f32", VOP_I32_F32_SPECIAL_OMOD, fp_to_uint>;
defm V_CVT_I32_F32 : VOP1Inst <"v_cvt_i32_f32", VOP_I32_F32_SPECIAL_OMOD, fp_to_sint>;
let FPDPRounding = 1, isReMaterializable = 0 in {
+ // V_CVT_F16_F32 and V_CVT_F32_F16 are special cases because they are
+ // present in targets without Has16BitInsts. Otherwise they can use
+ // class VOP1Inst_t16
let OtherPredicates = [NotHasTrue16BitInsts] in
defm V_CVT_F16_F32 : VOP1Inst <"v_cvt_f16_f32", VOP_F16_F32, any_fpround>;
- let OtherPredicates = [HasTrue16BitInsts] in
- defm V_CVT_F16_F32_t16 : VOP1Inst <"v_cvt_f16_f32_t16", VOPProfile_Fake16<VOP_F16_F32>, any_fpround>;
+ let OtherPredicates = [UseRealTrue16Insts] in
+ defm V_CVT_F16_F32_t16 : VOP1Inst <"v_cvt_f16_f32_t16", VOPProfile_True16<VOP_F16_F32>, any_fpround>;
+ let OtherPredicates = [UseFakeTrue16Insts] in
+ defm V_CVT_F16_F32_fake16 : VOP1Inst <"v_cvt_f16_f32_fake16", VOPProfile_Fake16<VOP_F16_F32>, any_fpround>;
} // End FPDPRounding = 1, isReMaterializable = 0
let OtherPredicates = [NotHasTrue16BitInsts] in
defm V_CVT_F32_F16 : VOP1Inst <"v_cvt_f32_f16", VOP_F32_F16, any_fpextend>;
-let OtherPredicates = [HasTrue16BitInsts] in
-defm V_CVT_F32_F16_t16 : VOP1Inst <"v_cvt_f32_f16_t16", VOPProfile_Fake16<VOP_F32_F16>, any_fpextend>;
+let OtherPredicates = [UseRealTrue16Insts] in
+ defm V_CVT_F32_F16_t16 : VOP1Inst <"v_cvt_f32_f16_t16", VOPProfile_True16<VOP_F32_F16>, any_fpextend>;
+let OtherPredicates = [UseFakeTrue16Insts] in
+ defm V_CVT_F32_F16_fake16 : VOP1Inst <"v_cvt_f32_f16_fake16", VOPProfile_Fake16<VOP_F32_F16>, any_fpextend>;
let ReadsModeReg = 0, mayRaiseFPException = 0 in {
defm V_CVT_RPI_I32_F32 : VOP1Inst <"v_cvt_rpi_i32_f32", VOP_I32_F32, cvt_rpi_i32_f32>;
@@ -473,24 +479,15 @@ let SubtargetPredicate = isGFX7Plus in {
} // End isReMaterializable = 1
let FPDPRounding = 1 in {
-let OtherPredicates = [Has16BitInsts, NotHasTrue16BitInsts] in {
-defm V_CVT_F16_U16 : VOP1Inst <"v_cvt_f16_u16", VOP1_F16_I16, uint_to_fp>;
-defm V_CVT_F16_I16 : VOP1Inst <"v_cvt_f16_i16", VOP1_F16_I16, sint_to_fp>;
-}
-let OtherPredicates = [HasTrue16BitInsts] in {
-defm V_CVT_F16_U16_t16 : VOP1Inst <"v_cvt_f16_u16_t16", VOP1_F16_I16_t16, uint_to_fp>;
-defm V_CVT_F16_I16_t16 : VOP1Inst <"v_cvt_f16_i16_t16", VOP1_F16_I16_t16, sint_to_fp>;
-}
+defm V_CVT_F16_U16 : VOP1Inst_t16_with_profiles <"v_cvt_f16_u16", VOP1_F16_I16, VOP1_F16_I16_t16, VOP1_F16_I16_fake16, uint_to_fp>;
+defm V_CVT_F16_I16 : VOP1Inst_t16_with_profiles <"v_cvt_f16_i16", VOP1_F16_I16, VOP1_F16_I16_t16, VOP1_F16_I16_fake16, sint_to_fp>;
} // End FPDPRounding = 1
// OMod clears exceptions when set in these two instructions
-let OtherPredicates = [Has16BitInsts, NotHasTrue16BitInsts] in {
-defm V_CVT_U16_F16 : VOP1Inst <"v_cvt_u16_f16", VOP_I16_F16_SPECIAL_OMOD, fp_to_uint>;
-defm V_CVT_I16_F16 : VOP1Inst <"v_cvt_i16_f16", VOP_I16_F16_SPECIAL_OMOD, fp_to_sint>;
-}
-let OtherPredicates = [HasTrue16BitInsts] in {
-defm V_CVT_U16_F16_t16 : VOP1Inst <"v_cvt_u16_f16_t16", VOP_I16_F16_SPECIAL_OMOD_t16, fp_to_uint>;
-defm V_CVT_I16_F16_t16 : VOP1Inst <"v_cvt_i16_f16_t16", VOP_I16_F16_SPECIAL_OMOD_t16, fp_to_sint>;
-}
+defm V_CVT_U16_F16 : VOP1Inst_t16_with_profiles <"v_cvt_u16_f16",
+ VOP_I16_F16_SPECIAL_OMOD, VOP_I16_F16_SPECIAL_OMOD_t16, VOP_I16_F16_SPECIAL_OMOD, fp_to_uint>;
+defm V_CVT_I16_F16 : VOP1Inst_t16_with_profiles <"v_cvt_i16_f16",
+ VOP_I16_F16_SPECIAL_OMOD, VOP_I16_F16_SPECIAL_OMOD_t16, VOP_I16_F16_SPECIAL_OMOD, fp_to_sint>;
+
let TRANS = 1, SchedRW = [WriteTrans32] in {
defm V_RCP_F16 : VOP1Inst_t16 <"v_rcp_f16", VOP_F16_F16, AMDGPUrcp>;
defm V_SQRT_F16 : VOP1Inst_t16 <"v_sqrt_f16", VOP_F16_F16, any_amdgcn_sqrt>;
@@ -501,12 +498,8 @@ defm V_SIN_F16 : VOP1Inst_t16 <"v_sin_f16", VOP_F16_F16, AMDGPUsin>;
defm V_COS_F16 : VOP1Inst_t16 <"v_cos_f16", VOP_F16_F16, AMDGPUcos>;
} // End TRANS = 1, SchedRW = [WriteTrans32]
defm V_FREXP_MANT_F16 : VOP1Inst_t16 <"v_frexp_mant_f16", VOP_F16_F16, int_amdgcn_frexp_mant>;
-let OtherPredicates = [Has16BitInsts, NotHasTrue16BitInsts] in {
-defm V_FREXP_EXP_I16_F16 : VOP1Inst <"v_frexp_exp_i16_f16", VOP_I16_F16_SPECIAL_OMOD, int_amdgcn_frexp_exp>;
-}
-let OtherPredicates = [HasTrue16BitInsts] in {
-defm V_FREXP_EXP_I16_F16_t16 : VOP1Inst <"v_frexp_exp_i16_f16_t16", VOP_I16_F16_SPECIAL_OMOD_t16, int_amdgcn_frexp_exp>;
-}
+defm V_FREXP_EXP_I16_F16 : VOP1Inst_t16_with_profiles <"v_frexp_exp_i16_f16",
+ VOP_I16_F16_SPECIAL_OMOD, VOP_I16_F16_SPECIAL_OMOD_t16, VOP_I16_F16_SPECIAL_OMOD, int_amdgcn_frexp_exp>;
defm V_FLOOR_F16 : VOP1Inst_t16 <"v_floor_f16", VOP_F16_F16, ffloor>;
defm V_CEIL_F16 : VOP1Inst_t16 <"v_ceil_f16", VOP_F16_F16, fceil>;
defm V_TRUNC_F16 : VOP1Inst_t16 <"v_trunc_f16", VOP_F16_F16, ftrunc>;
@@ -554,14 +547,10 @@ let SubtargetPredicate = isGFX9Plus in {
defm V_SAT_PK_U8_I16 : VOP1Inst_t16<"v_sat_pk_u8_i16", VOP_I16_I32>;
let mayRaiseFPException = 0 in {
- let OtherPredicates = [Has16BitInsts, NotHasTrue16BitInsts] in {
- defm V_CVT_NORM_I16_F16 : VOP1Inst<"v_cvt_norm_i16_f16", VOP_I16_F16_SPECIAL_OMOD>;
- defm V_CVT_NORM_U16_F16 : VOP1Inst<"v_cvt_norm_u16_f16", VOP_I16_F16_SPECIAL_OMOD>;
- }
- let OtherPredicates = [HasTrue16BitInsts] in {
- defm V_CVT_NORM_I16_F16_t16 : VOP1Inst<"v_cvt_norm_i16_f16_t16", VOP_I16_F16_SPECIAL_OMOD_t16>;
- defm V_CVT_NORM_U16_F16_t16 : VOP1Inst<"v_cvt_norm_u16_f16_t16", VOP_I16_F16_SPECIAL_OMOD_t16>;
- }
+ defm V_CVT_NORM_I16_F16 : VOP1Inst_t16_with_profiles<"v_cvt_norm_i16_f16",
+ VOP_I16_F16_SPECIAL_OMOD, VOP_I16_F16_SPECIAL_OMOD_t16, VOP_I16_F16_SPECIAL_OMOD_fake16>;
+ defm V_CVT_NORM_U16_F16 : VOP1Inst_t16_with_profiles<"v_cvt_norm_u16_f16",
+ VOP_I16_F16_SPECIAL_OMOD, VOP_I16_F16_SPECIAL_OMOD_t16, VOP_I16_F16_SPECIAL_OMOD_fake16>;
} // End mayRaiseFPException = 0
} // End SubtargetPredicate = isGFX9Plus
@@ -975,9 +964,13 @@ defm V_CVT_I32_I16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x06a, "v_cvt_i32_
defm V_CVT_U32_U16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x06b, "v_cvt_u32_u16">;
defm V_CVT_F16_U16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x050, "v_cvt_f16_u16">;
+defm V_CVT_F16_U16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x050, "v_cvt_f16_u16">;
defm V_CVT_F16_I16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x051, "v_cvt_f16_i16">;
+defm V_CVT_F16_I16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x051, "v_cvt_f16_i16">;
defm V_CVT_U16_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x052, "v_cvt_u16_f16">;
+defm V_CVT_U16_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x052, "v_cvt_u16_f16">;
defm V_CVT_I16_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x053, "v_cvt_i16_f16">;
+defm V_CVT_I16_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x053, "v_cvt_i16_f16">;
defm V_RCP_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x054, "v_rcp_f16">;
defm V_RCP_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x054, "v_rcp_f16">;
defm V_SQRT_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x055, "v_sqrt_f16">;
@@ -990,6 +983,7 @@ defm V_EXP_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x058, "v_exp_f16"
defm V_EXP_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x058, "v_exp_f16">;
defm V_FREXP_MANT_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x059, "v_frexp_mant_f16">;
defm V_FREXP_EXP_I16_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05a, "v_frexp_exp_i16_f16">;
+defm V_FREXP_EXP_I16_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05a, "v_frexp_exp_i16_f16">;
defm V_FLOOR_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05b, "v_floor_f16">;
defm V_FLOOR_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05b, "v_floor_f16">;
defm V_CEIL_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05c, "v_ceil_f16">;
@@ -1001,10 +995,14 @@ defm V_SIN_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x060, "v_sin_f16"
defm V_COS_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x061, "v_cos_f16">;
defm V_SAT_PK_U8_I16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x062, "v_sat_pk_u8_i16">;
defm V_CVT_NORM_I16_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x063, "v_cvt_norm_i16_f16">;
+defm V_CVT_NORM_I16_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x063, "v_cvt_norm_i16_f16">;
defm V_CVT_NORM_U16_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x064, "v_cvt_norm_u16_f16">;
+defm V_CVT_NORM_U16_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x064, "v_cvt_norm_u16_f16">;
defm V_CVT_F16_F32_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x00a, "v_cvt_f16_f32">;
+defm V_CVT_F16_F32_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x00a, "v_cvt_f16_f32">;
defm V_CVT_F32_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x00b, "v_cvt_f32_f16">;
+defm V_CVT_F32_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x00b, "v_cvt_f32_f16">;
//===----------------------------------------------------------------------===//
// GFX10.
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
index ab587a524fc6e5..43e6e10c9eae69 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
@@ -28,74 +28,74 @@ v_cos_f16_e32 v255, v1
v_cos_f16_e32 v5, v199
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-v_cvt_f16_f32_e32 v128, 0xaf123456
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_cvt_f16_f32_e32 v128.h, 0xaf123456
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f16_f32_e32 v255, v1
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_cvt_f16_f32_e32 v255.h, v1.h
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f16_f32_e32 v255, v255
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_cvt_f16_f32_e32 v255.h, v255.h
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f16_i16_e32 v128, 0xfe0b
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_cvt_f16_i16_e32 v128.l, 0xfe0b
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f16_i16_e32 v255, v1
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_cvt_f16_i16_e32 v255.h, v1.h
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f16_i16_e32 v5, v199
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_cvt_f16_i16_e32 v5.h, v199.l
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f16_u16_e32 v128, 0xfe0b
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_cvt_f16_u16_e32 v128.l, 0xfe0b
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f16_u16_e32 v255, v1
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_cvt_f16_u16_e32 v255.l, v1.h
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f16_u16_e32 v5, v199
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_cvt_f16_u16_e32 v5.h, v199.l
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f32_f16_e32 v5, v199
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_cvt_f32_f16_e32 v5.l, v199.l
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_i16_f16_e32 v128, 0xfe0b
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_cvt_i16_f16_e32 v128.l, 0xfe0b
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_i16_f16_e32 v255, v1
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_cvt_i16_f16_e32 v255.l, v1.l
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_i16_f16_e32 v5, v199
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_cvt_i16_f16_e32 v5.l, v199.
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
v_cvt_i32_i16_e32 v5, v199
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_norm_i16_f16_e32 v128, 0xfe0b
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_cvt_norm_i16_f16_e32 v128.h, 0xfe0b
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_norm_i16_f16_e32 v255, v1
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_cvt_norm_i16_f16_e32 v255.l, v1.h
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_norm_i16_f16_e32 v5, v199
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_cvt_norm_i16_f16_e32 v5.l, v199.h
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_norm_u16_f16_e32 v128, 0xfe0b
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_cvt_norm_u16_f16_e32 v128.l, 0xfe0b
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_norm_u16_f16_e32 v255, v1
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_cvt_norm_u16_f16_e32 v255.h, v1.l
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_norm_u16_f16_e32 v5, v199
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_cvt_norm_u16_f16_e32 v5.l, v199.h
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_u16_f16_e32 v128, 0xfe0b
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_cvt_u16_f16_e32 v128.l, 0xfe0b
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_u16_f16_e32 v255, v1
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_cvt_u16_f16_e32 v255.h, v1
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_u16_f16_e32 v5, v199
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_cvt_u16_f16_e32 v5.l, v199
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
v_cvt_u32_u16_e32 v5, v199
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
@@ -127,14 +127,14 @@ v_fract_f16_e32 v255, v1
v_fract_f16_e32 v5, v199
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-v_frexp_exp_i16_f16_e32 v128, 0xfe0b
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_frexp_exp_i16_f16_e32 v128.l, 0xfe0b
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_frexp_exp_i16_f16_e32 v255, v1
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_frexp_exp_i16_f16_e32 v255.h, v1
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_frexp_exp_i16_f16_e32 v5, v199
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+v_frexp_exp_i16_f16_e32 v5.h, v199.l
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
v_frexp_mant_f16_e32 v128, 0xfe0b
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
@@ -250,58 +250,58 @@ v_cos_f16_e32 v255, v1 quad_perm:[3,2,1,0]
v_cos_f16_e32 v5, v199 quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f16_f32_e32 v128, 0xaf123456 quad_perm:[3,2,1,0]
+v_cvt_f16_f32_e32 v128.h, 0xaf123456 quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f16_f32_e32 v255, v1 quad_perm:[3,2,1,0]
+v_cvt_f16_f32_e32 v255.h, v1.h quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f16_f32_e32 v255, v255 quad_perm:[3,2,1,0]
+v_cvt_f16_f32_e32 v255.h, v255.h quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f16_i16_e32 v255, v1 quad_perm:[3,2,1,0]
+v_cvt_f16_i16_e32 v255.h, v1.l quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f16_i16_e32 v5, v199 quad_perm:[3,2,1,0]
+v_cvt_f16_i16_e32 v5.l, v199.h quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f16_u16_e32 v255, v1 quad_perm:[3,2,1,0]
+v_cvt_f16_u16_e32 v255.l, v1.h quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f16_u16_e32 v5, v199 quad_perm:[3,2,1,0]
+v_cvt_f16_u16_e32 v5.l, v199.h quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f32_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+v_cvt_f32_f16_e32 v5.1, v199.1 quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_i16_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+v_cvt_i16_f16_e32 v255.l, v1.h quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_i16_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+v_cvt_i16_f16_e32 v5.l, v199.h quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
v_cvt_i32_i16_e32 v5, v199 quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_norm_i16_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+v_cvt_norm_i16_f16_e32 v255.l, v1.l quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_norm_i16_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+v_cvt_norm_i16_f16_e32 v5.h, v199.l quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_norm_u16_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+v_cvt_norm_u16_f16_e32 v255.h, v1.l quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_norm_u16_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+v_cvt_norm_u16_f16_e32 v5.l, v199.h quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_u16_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+v_cvt_u16_f16_e32 v255.l, v1.h quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_u16_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+v_cvt_u16_f16_e32 v5.h, v199.l quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_u32_u16_e32 v5, v199 quad_perm:[3,2,1,0]
+v_cvt_u32_u16_e32 v5.l, v199.h quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
v_exp_f16_e32 v255.l, v1.l quad_perm:[3,2,1,0]
@@ -322,10 +322,10 @@ v_fract_f16_e32 v255, v1 quad_perm:[3,2,1,0]
v_fract_f16_e32 v5, v199 quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_frexp_exp_i16_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+v_frexp_exp_i16_f16_e32 v255.l, v1.h quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_frexp_exp_i16_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+v_frexp_exp_i16_f16_e32 v5.l, v199.l quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
v_frexp_mant_f16_e32 v255, v1 quad_perm:[3,2,1,0]
@@ -403,55 +403,55 @@ v_cos_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
v_cos_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f16_f32_e32 v128, 0xaf123456 dpp8:[7,6,5,4,3,2,1,0]
+v_cvt_f16_f32_e32 v128.l, 0xaf123456 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f16_f32_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+v_cvt_f16_f32_e32 v255.l, v1 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f16_f32_e32 v255, v255 dpp8:[7,6,5,4,3,2,1,0]
+v_cvt_f16_f32_e32 v255.l, v255 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f16_i16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+v_cvt_f16_i16_e32 v255.l, v1.h dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f16_i16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+v_cvt_f16_i16_e32 v5.l, v199.h dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f16_u16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+v_cvt_f16_u16_e32 v255.l, v1 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f16_u16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+v_cvt_f16_u16_e32 v5.h, v199.l dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_f32_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+v_cvt_f32_f16_e32 v5.h, v199.h dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_i16_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+v_cvt_i16_f16_e32 v255.h, v1.l dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_i16_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+v_cvt_i16_f16_e32 v5.h, v199.l dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
v_cvt_i32_i16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_norm_i16_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+v_cvt_norm_i16_f16_e32 v255.h, v1.h dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_norm_i16_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+v_cvt_norm_i16_f16_e32 v5.l, v199.h dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_norm_u16_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+v_cvt_norm_u16_f16_e32 v255.h, v1.l dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_norm_u16_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+v_cvt_norm_u16_f16_e32 v5.l, v199.h dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_u16_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+v_cvt_u16_f16_e32 v255.l, v1.h dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_cvt_u16_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+v_cvt_u16_f16_e32 v5.h, v199.l dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
v_cvt_u32_u16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
@@ -475,10 +475,10 @@ v_fract_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
v_fract_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_frexp_exp_i16_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+v_frexp_exp_i16_f16_e32 v255.h, v1.l dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-v_frexp_exp_i16_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+v_frexp_exp_i16_f16_e32 v5.l, v199.h dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
v_frexp_mant_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
index 68de95a9857e81..f2369ebc33651a 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
@@ -1,5 +1,6 @@
-// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 -show-encoding %s | FileCheck --check-prefix=GFX11 --implicit-check-not=_e32 %s
-// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 --implicit-check-not=_e32 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefix=GFX11 --implicit-check-not=_e32 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefix=GFX11 --implicit-check-not=_e32 %s
+// FIXME-TRUE16 enable V_CVT_F16_F32/V_CVT_F32_F16 when asm parser change are ready
v_ceil_f16 v128, 0xfe0b
// GFX11: v_ceil_f16_e64
@@ -97,7 +98,7 @@ v_cos_f16 v255, vcc_lo
v_cos_f16 v5, v199
// GFX11: v_cos_f16_e64
-v_cvt_f16_f32 v128, 0xaf123456
+v_cvt_f16_f32 v128.l, 0xaf123456
// GFX11: v_cvt_f16_f32_e64
v_cvt_f16_f32 v255, -1
@@ -142,301 +143,301 @@ v_cvt_f16_f32 v255, vcc_hi
v_cvt_f16_f32 v255, vcc_lo
// GFX11: v_cvt_f16_f32_e64
-v_cvt_f16_i16 v128, 0xfe0b
+v_cvt_f16_i16 v128.l, 0xfe0b
// GFX11: v_cvt_f16_i16_e64
-v_cvt_f16_i16 v255, -1
+v_cvt_f16_i16 v255.l, -1
// GFX11: v_cvt_f16_i16_e64
-v_cvt_f16_i16 v255, 0.5
+v_cvt_f16_i16 v255.l, 0.5
// GFX11: v_cvt_f16_i16_e64
-v_cvt_f16_i16 v255, exec_hi
+v_cvt_f16_i16 v255.l, exec_hi
// GFX11: v_cvt_f16_i16_e64
-v_cvt_f16_i16 v255, exec_lo
+v_cvt_f16_i16 v255.l, exec_lo
// GFX11: v_cvt_f16_i16_e64
-v_cvt_f16_i16 v255, m0
+v_cvt_f16_i16 v255.l, m0
// GFX11: v_cvt_f16_i16_e64
-v_cvt_f16_i16 v255, null
+v_cvt_f16_i16 v255.l, null
// GFX11: v_cvt_f16_i16_e64
-v_cvt_f16_i16 v255, s1
+v_cvt_f16_i16 v255.l, s1
// GFX11: v_cvt_f16_i16_e64
-v_cvt_f16_i16 v255, s105
+v_cvt_f16_i16 v255.l, s105
// GFX11: v_cvt_f16_i16_e64
-v_cvt_f16_i16 v255, src_scc
+v_cvt_f16_i16 v255.l, src_scc
// GFX11: v_cvt_f16_i16_e64
-v_cvt_f16_i16 v255, ttmp15
+v_cvt_f16_i16 v255.l, ttmp15
// GFX11: v_cvt_f16_i16_e64
-v_cvt_f16_i16 v255, v1
+v_cvt_f16_i16 v255.l, v1.l
// GFX11: v_cvt_f16_i16_e64
-v_cvt_f16_i16 v255, v127
+v_cvt_f16_i16 v5.l, v199.l
// GFX11: v_cvt_f16_i16_e64
-v_cvt_f16_i16 v255, vcc_hi
+v_cvt_f16_i16 v255.l, v127.l
// GFX11: v_cvt_f16_i16_e64
-v_cvt_f16_i16 v255, vcc_lo
+v_cvt_f16_i16 v255.l, vcc_hi
// GFX11: v_cvt_f16_i16_e64
-v_cvt_f16_i16 v5, v199
+v_cvt_f16_i16 v255.l, vcc_lo
// GFX11: v_cvt_f16_i16_e64
-v_cvt_f16_u16 v128, 0xfe0b
+v_cvt_f16_u16 v128.l, 0xfe0b
// GFX11: v_cvt_f16_u16_e64
-v_cvt_f16_u16 v255, -1
+v_cvt_f16_u16 v255.l, -1
// GFX11: v_cvt_f16_u16_e64
-v_cvt_f16_u16 v255, 0.5
+v_cvt_f16_u16 v255.l, 0.5
// GFX11: v_cvt_f16_u16_e64
-v_cvt_f16_u16 v255, exec_hi
+v_cvt_f16_u16 v255.l, exec_hi
// GFX11: v_cvt_f16_u16_e64
-v_cvt_f16_u16 v255, exec_lo
+v_cvt_f16_u16 v255.l, exec_lo
// GFX11: v_cvt_f16_u16_e64
-v_cvt_f16_u16 v255, m0
+v_cvt_f16_u16 v255.l, m0
// GFX11: v_cvt_f16_u16_e64
-v_cvt_f16_u16 v255, null
+v_cvt_f16_u16 v255.l, null
// GFX11: v_cvt_f16_u16_e64
-v_cvt_f16_u16 v255, s1
+v_cvt_f16_u16 v255.l, s1
// GFX11: v_cvt_f16_u16_e64
-v_cvt_f16_u16 v255, s105
+v_cvt_f16_u16 v255.l, s105
// GFX11: v_cvt_f16_u16_e64
-v_cvt_f16_u16 v255, src_scc
+v_cvt_f16_u16 v255.l, src_scc
// GFX11: v_cvt_f16_u16_e64
-v_cvt_f16_u16 v255, ttmp15
+v_cvt_f16_u16 v255.l, ttmp15
// GFX11: v_cvt_f16_u16_e64
-v_cvt_f16_u16 v255, v1
+v_cvt_f16_u16 v255.l, v1.l
// GFX11: v_cvt_f16_u16_e64
-v_cvt_f16_u16 v255, v127
+v_cvt_f16_u16 v255.l, v127.l
// GFX11: v_cvt_f16_u16_e64
-v_cvt_f16_u16 v255, vcc_hi
+v_cvt_f16_u16 v255.l, vcc_hi
// GFX11: v_cvt_f16_u16_e64
-v_cvt_f16_u16 v255, vcc_lo
+v_cvt_f16_u16 v255.l, vcc_lo
// GFX11: v_cvt_f16_u16_e64
-v_cvt_f16_u16 v5, v199
+v_cvt_f16_u16 v5.l, v199.l
// GFX11: v_cvt_f16_u16_e64
v_cvt_f32_f16 v5, v199
// GFX11: v_cvt_f32_f16_e64
-v_cvt_i16_f16 v128, 0xfe0b
+v_cvt_i16_f16 v128.l, 0xfe0b
// GFX11: v_cvt_i16_f16_e64
-v_cvt_i16_f16 v255, -1
+v_cvt_i16_f16 v255.l, -1
// GFX11: v_cvt_i16_f16_e64
-v_cvt_i16_f16 v255, 0.5
+v_cvt_i16_f16 v255.h, 0.5
// GFX11: v_cvt_i16_f16_e64
-v_cvt_i16_f16 v255, exec_hi
+v_cvt_i16_f16 v255.l, exec_hi
// GFX11: v_cvt_i16_f16_e64
-v_cvt_i16_f16 v255, exec_lo
+v_cvt_i16_f16 v255.h, exec_lo
// GFX11: v_cvt_i16_f16_e64
-v_cvt_i16_f16 v255, m0
+v_cvt_i16_f16 v255.l, m0
// GFX11: v_cvt_i16_f16_e64
-v_cvt_i16_f16 v255, null
+v_cvt_i16_f16 v255.l, null
// GFX11: v_cvt_i16_f16_e64
-v_cvt_i16_f16 v255, s1
+v_cvt_i16_f16 v255.l, s1
// GFX11: v_cvt_i16_f16_e64
-v_cvt_i16_f16 v255, s105
+v_cvt_i16_f16 v255.l, s105
// GFX11: v_cvt_i16_f16_e64
-v_cvt_i16_f16 v255, src_scc
+v_cvt_i16_f16 v255.l, src_scc
// GFX11: v_cvt_i16_f16_e64
-v_cvt_i16_f16 v255, ttmp15
+v_cvt_i16_f16 v255.l, ttmp15
// GFX11: v_cvt_i16_f16_e64
-v_cvt_i16_f16 v255, v1
+v_cvt_i16_f16 v255.l, v1.l
// GFX11: v_cvt_i16_f16_e64
-v_cvt_i16_f16 v255, v127
+v_cvt_i16_f16 v255.l, v127.l
// GFX11: v_cvt_i16_f16_e64
-v_cvt_i16_f16 v255, vcc_hi
+v_cvt_i16_f16 v255.l, vcc_hi
// GFX11: v_cvt_i16_f16_e64
-v_cvt_i16_f16 v255, vcc_lo
+v_cvt_i16_f16 v255.l, vcc_lo
// GFX11: v_cvt_i16_f16_e64
-v_cvt_i16_f16 v5, v199
+v_cvt_i16_f16 v5.h, v199.l
// GFX11: v_cvt_i16_f16_e64
v_cvt_i32_i16 v5, v199
// GFX11: v_cvt_i32_i16_e64
-v_cvt_norm_i16_f16 v128, 0xfe0b
+v_cvt_norm_i16_f16 v128.l, 0xfe0b
// GFX11: v_cvt_norm_i16_f16_e64
-v_cvt_norm_i16_f16 v255, -1
+v_cvt_norm_i16_f16 v255.l, -1
// GFX11: v_cvt_norm_i16_f16_e64
-v_cvt_norm_i16_f16 v255, 0.5
+v_cvt_norm_i16_f16 v255.l, 0.5
// GFX11: v_cvt_norm_i16_f16_e64
-v_cvt_norm_i16_f16 v255, exec_hi
+v_cvt_norm_i16_f16 v255.h, exec_hi
// GFX11: v_cvt_norm_i16_f16_e64
-v_cvt_norm_i16_f16 v255, exec_lo
+v_cvt_norm_i16_f16 v255.l, exec_lo
// GFX11: v_cvt_norm_i16_f16_e64
-v_cvt_norm_i16_f16 v255, m0
+v_cvt_norm_i16_f16 v255.l, m0
// GFX11: v_cvt_norm_i16_f16_e64
-v_cvt_norm_i16_f16 v255, null
+v_cvt_norm_i16_f16 v255.l, null
// GFX11: v_cvt_norm_i16_f16_e64
-v_cvt_norm_i16_f16 v255, s1
+v_cvt_norm_i16_f16 v255.h, s1
// GFX11: v_cvt_norm_i16_f16_e64
-v_cvt_norm_i16_f16 v255, s105
+v_cvt_norm_i16_f16 v255.l, s105
// GFX11: v_cvt_norm_i16_f16_e64
-v_cvt_norm_i16_f16 v255, src_scc
+v_cvt_norm_i16_f16 v255.l, src_scc
// GFX11: v_cvt_norm_i16_f16_e64
-v_cvt_norm_i16_f16 v255, ttmp15
+v_cvt_norm_i16_f16 v255.h, ttmp15
// GFX11: v_cvt_norm_i16_f16_e64
-v_cvt_norm_i16_f16 v255, v1
+v_cvt_norm_i16_f16 v255.l, v1.l
// GFX11: v_cvt_norm_i16_f16_e64
-v_cvt_norm_i16_f16 v255, v127
+v_cvt_norm_i16_f16 v255.l. v127.l
// GFX11: v_cvt_norm_i16_f16_e64
-v_cvt_norm_i16_f16 v255, vcc_hi
+v_cvt_norm_i16_f16 v255.h, vcc_hi
// GFX11: v_cvt_norm_i16_f16_e64
-v_cvt_norm_i16_f16 v255, vcc_lo
+v_cvt_norm_i16_f16 v255.h, vcc_lo
// GFX11: v_cvt_norm_i16_f16_e64
-v_cvt_norm_i16_f16 v5, v199
+v_cvt_norm_i16_f16 v5.l, v199.l
// GFX11: v_cvt_norm_i16_f16_e64
-v_cvt_norm_u16_f16 v128, 0xfe0b
+v_cvt_norm_u16_f16 v128.l, 0xfe0b
// GFX11: v_cvt_norm_u16_f16_e64
-v_cvt_norm_u16_f16 v255, -1
+v_cvt_norm_u16_f16 v255.h, -1
// GFX11: v_cvt_norm_u16_f16_e64
-v_cvt_norm_u16_f16 v255, 0.5
+v_cvt_norm_u16_f16 v255.h, 0.5
// GFX11: v_cvt_norm_u16_f16_e64
-v_cvt_norm_u16_f16 v255, exec_hi
+v_cvt_norm_u16_f16 v255.l, exec_hi
// GFX11: v_cvt_norm_u16_f16_e64
-v_cvt_norm_u16_f16 v255, exec_lo
+v_cvt_norm_u16_f16 v255.l, exec_lo
// GFX11: v_cvt_norm_u16_f16_e64
-v_cvt_norm_u16_f16 v255, m0
+v_cvt_norm_u16_f16 v25.l, m0
// GFX11: v_cvt_norm_u16_f16_e64
-v_cvt_norm_u16_f16 v255, null
+v_cvt_norm_u16_f16 v255.h, null
// GFX11: v_cvt_norm_u16_f16_e64
-v_cvt_norm_u16_f16 v255, s1
+v_cvt_norm_u16_f16 v255.l, s1
// GFX11: v_cvt_norm_u16_f16_e64
-v_cvt_norm_u16_f16 v255, s105
+v_cvt_norm_u16_f16 v255.h, s105
// GFX11: v_cvt_norm_u16_f16_e64
-v_cvt_norm_u16_f16 v255, src_scc
+v_cvt_norm_u16_f16 v255.l, src_scc
// GFX11: v_cvt_norm_u16_f16_e64
-v_cvt_norm_u16_f16 v255, ttmp15
+v_cvt_norm_u16_f16 v255.l, ttmp15
// GFX11: v_cvt_norm_u16_f16_e64
-v_cvt_norm_u16_f16 v255, v1
+v_cvt_norm_u16_f16 v255.h, v1.h
// GFX11: v_cvt_norm_u16_f16_e64
-v_cvt_norm_u16_f16 v255, v127
+v_cvt_norm_u16_f16 v255.l, v127.l
// GFX11: v_cvt_norm_u16_f16_e64
-v_cvt_norm_u16_f16 v255, vcc_hi
+v_cvt_norm_u16_f16 v255.h, vcc_hi
// GFX11: v_cvt_norm_u16_f16_e64
-v_cvt_norm_u16_f16 v255, vcc_lo
+v_cvt_norm_u16_f16 v255.l, vcc_lo
// GFX11: v_cvt_norm_u16_f16_e64
-v_cvt_norm_u16_f16 v5, v199
+v_cvt_norm_u16_f16 v5.h, v199.l
// GFX11: v_cvt_norm_u16_f16_e64
-v_cvt_u16_f16 v128, 0xfe0b
+v_cvt_u16_f16 v128.l, 0xfe0b
// GFX11: v_cvt_u16_f16_e64
-v_cvt_u16_f16 v255, -1
+v_cvt_u16_f16 v255.h, -1
// GFX11: v_cvt_u16_f16_e64
-v_cvt_u16_f16 v255, 0.5
+v_cvt_u16_f16 v255.l, 0.5
// GFX11: v_cvt_u16_f16_e64
-v_cvt_u16_f16 v255, exec_hi
+v_cvt_u16_f16 v255.h, exec_hi
// GFX11: v_cvt_u16_f16_e64
-v_cvt_u16_f16 v255, exec_lo
+v_cvt_u16_f16 v255.h, exec_lo
// GFX11: v_cvt_u16_f16_e64
-v_cvt_u16_f16 v255, m0
+v_cvt_u16_f16 v255.l, m0
// GFX11: v_cvt_u16_f16_e64
-v_cvt_u16_f16 v255, null
+v_cvt_u16_f16 v255.h, null
// GFX11: v_cvt_u16_f16_e64
-v_cvt_u16_f16 v255, s1
+v_cvt_u16_f16 v255.h, s1
// GFX11: v_cvt_u16_f16_e64
-v_cvt_u16_f16 v255, s105
+v_cvt_u16_f16 v255.l, s105
// GFX11: v_cvt_u16_f16_e64
-v_cvt_u16_f16 v255, src_scc
+v_cvt_u16_f16 v255.h, src_scc
// GFX11: v_cvt_u16_f16_e64
-v_cvt_u16_f16 v255, ttmp15
+v_cvt_u16_f16 v255.l, ttmp15
// GFX11: v_cvt_u16_f16_e64
-v_cvt_u16_f16 v255, v1
+v_cvt_u16_f16 v255.h, v1.l
// GFX11: v_cvt_u16_f16_e64
-v_cvt_u16_f16 v255, v127
+v_cvt_u16_f16 v255.h, v127.l
// GFX11: v_cvt_u16_f16_e64
-v_cvt_u16_f16 v255, vcc_hi
+v_cvt_u16_f16 v255.h, vcc_hi
// GFX11: v_cvt_u16_f16_e64
-v_cvt_u16_f16 v255, vcc_lo
+v_cvt_u16_f16 v255.l, vcc_lo
// GFX11: v_cvt_u16_f16_e64
-v_cvt_u16_f16 v5, v199
+v_cvt_u16_f16 v5.h, v199.h
// GFX11: v_cvt_u16_f16_e64
-v_cvt_u32_u16 v5, v199
+v_cvt_u32_u16 v5.h, v199.l
// GFX11: v_cvt_u32_u16_e64
v_exp_f16 v128, 0xfe0b
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