[llvm] 82cf655 - [LoongArch] Pre-commit tests for validating the merge base offset in vecotrs. NFC
WANG Rui via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 15 06:06:10 PDT 2024
Author: WANG Rui
Date: 2024-08-15T21:06:27+08:00
New Revision: 82cf6558e50ea7fe024264cc2fb76ca20450fb82
URL: https://github.com/llvm/llvm-project/commit/82cf6558e50ea7fe024264cc2fb76ca20450fb82
DIFF: https://github.com/llvm/llvm-project/commit/82cf6558e50ea7fe024264cc2fb76ca20450fb82.diff
LOG: [LoongArch] Pre-commit tests for validating the merge base offset in vecotrs. NFC
Added:
Modified:
llvm/test/CodeGen/LoongArch/merge-base-offset.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/LoongArch/merge-base-offset.ll b/llvm/test/CodeGen/LoongArch/merge-base-offset.ll
index 32a4c4bdd1508a..58a8e5d77c63fe 100644
--- a/llvm/test/CodeGen/LoongArch/merge-base-offset.ll
+++ b/llvm/test/CodeGen/LoongArch/merge-base-offset.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch32 --mattr=+d --verify-machineinstrs < %s \
+; RUN: llc --mtriple=loongarch32 --mattr=+lasx --verify-machineinstrs < %s \
; RUN: | FileCheck --check-prefix=LA32 %s
-; RUN: llc --mtriple=loongarch64 --mattr=+d --verify-machineinstrs < %s \
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx --verify-machineinstrs < %s \
; RUN: | FileCheck --check-prefix=LA64 %s
-; RUN: llc --mtriple=loongarch64 --mattr=+d --verify-machineinstrs \
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx --verify-machineinstrs \
; RUN: --code-model=large < %s | FileCheck --check-prefix=LA64-LARGE %s
@g_i8 = dso_local global i8 0
@@ -405,10 +405,7 @@ define dso_local void @store_f64() nounwind {
; LA32-LABEL: store_f64:
; LA32: # %bb.0: # %entry
; LA32-NEXT: pcalau12i $a0, %pc_hi20(g_f64)
-; LA32-NEXT: addi.w $a1, $zero, 1
-; LA32-NEXT: movgr2fr.w $fa0, $a1
-; LA32-NEXT: ffint.s.w $fa0, $fa0
-; LA32-NEXT: fcvt.d.s $fa0, $fa0
+; LA32-NEXT: vldi $vr0, -912
; LA32-NEXT: fst.d $fa0, $a0, %pc_lo12(g_f64)
; LA32-NEXT: ret
;
@@ -538,6 +535,184 @@ entry:
ret void
}
+ at g_i32x4_src = dso_local global [4 x i32] zeroinitializer, align 16
+ at g_i32x4_dst = dso_local global [4 x i32] zeroinitializer, align 16
+
+define dso_local void @copy_i32x4() nounwind {
+; LA32-LABEL: copy_i32x4:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: pcalau12i $a0, %pc_hi20(g_i32x4_src)
+; LA32-NEXT: addi.w $a0, $a0, %pc_lo12(g_i32x4_src)
+; LA32-NEXT: vld $vr0, $a0, 0
+; LA32-NEXT: pcalau12i $a0, %pc_hi20(g_i32x4_dst)
+; LA32-NEXT: addi.w $a0, $a0, %pc_lo12(g_i32x4_dst)
+; LA32-NEXT: vst $vr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: copy_i32x4:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: pcalau12i $a0, %pc_hi20(g_i32x4_src)
+; LA64-NEXT: addi.d $a0, $a0, %pc_lo12(g_i32x4_src)
+; LA64-NEXT: vld $vr0, $a0, 0
+; LA64-NEXT: pcalau12i $a0, %pc_hi20(g_i32x4_dst)
+; LA64-NEXT: addi.d $a0, $a0, %pc_lo12(g_i32x4_dst)
+; LA64-NEXT: vst $vr0, $a0, 0
+; LA64-NEXT: ret
+;
+; LA64-LARGE-LABEL: copy_i32x4:
+; LA64-LARGE: # %bb.0: # %entry
+; LA64-LARGE-NEXT: pcalau12i $a0, %pc_hi20(g_i32x4_src)
+; LA64-LARGE-NEXT: addi.d $a1, $zero, %pc_lo12(g_i32x4_src)
+; LA64-LARGE-NEXT: lu32i.d $a1, %pc64_lo20(g_i32x4_src)
+; LA64-LARGE-NEXT: lu52i.d $a1, $a1, %pc64_hi12(g_i32x4_src)
+; LA64-LARGE-NEXT: add.d $a0, $a1, $a0
+; LA64-LARGE-NEXT: vld $vr0, $a0, 0
+; LA64-LARGE-NEXT: pcalau12i $a0, %pc_hi20(g_i32x4_dst)
+; LA64-LARGE-NEXT: addi.d $a1, $zero, %pc_lo12(g_i32x4_dst)
+; LA64-LARGE-NEXT: lu32i.d $a1, %pc64_lo20(g_i32x4_dst)
+; LA64-LARGE-NEXT: lu52i.d $a1, $a1, %pc64_hi12(g_i32x4_dst)
+; LA64-LARGE-NEXT: add.d $a0, $a1, $a0
+; LA64-LARGE-NEXT: vst $vr0, $a0, 0
+; LA64-LARGE-NEXT: ret
+entry:
+ %0 = load <4 x i32>, ptr @g_i32x4_src, align 16
+ store <4 x i32> %0, ptr @g_i32x4_dst, align 16
+ ret void
+}
+
+ at g_i32x8_src = dso_local global [8 x i32] zeroinitializer, align 32
+ at g_i32x8_dst = dso_local global [8 x i32] zeroinitializer, align 32
+
+define dso_local void @copy_i32x8() nounwind {
+; LA32-LABEL: copy_i32x8:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: pcalau12i $a0, %pc_hi20(g_i32x4_src)
+; LA32-NEXT: addi.w $a0, $a0, %pc_lo12(g_i32x4_src)
+; LA32-NEXT: xvld $xr0, $a0, 0
+; LA32-NEXT: pcalau12i $a0, %pc_hi20(g_i32x4_dst)
+; LA32-NEXT: addi.w $a0, $a0, %pc_lo12(g_i32x4_dst)
+; LA32-NEXT: xvst $xr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: copy_i32x8:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: pcalau12i $a0, %pc_hi20(g_i32x4_src)
+; LA64-NEXT: addi.d $a0, $a0, %pc_lo12(g_i32x4_src)
+; LA64-NEXT: xvld $xr0, $a0, 0
+; LA64-NEXT: pcalau12i $a0, %pc_hi20(g_i32x4_dst)
+; LA64-NEXT: addi.d $a0, $a0, %pc_lo12(g_i32x4_dst)
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
+;
+; LA64-LARGE-LABEL: copy_i32x8:
+; LA64-LARGE: # %bb.0: # %entry
+; LA64-LARGE-NEXT: pcalau12i $a0, %pc_hi20(g_i32x4_src)
+; LA64-LARGE-NEXT: addi.d $a1, $zero, %pc_lo12(g_i32x4_src)
+; LA64-LARGE-NEXT: lu32i.d $a1, %pc64_lo20(g_i32x4_src)
+; LA64-LARGE-NEXT: lu52i.d $a1, $a1, %pc64_hi12(g_i32x4_src)
+; LA64-LARGE-NEXT: add.d $a0, $a1, $a0
+; LA64-LARGE-NEXT: xvld $xr0, $a0, 0
+; LA64-LARGE-NEXT: pcalau12i $a0, %pc_hi20(g_i32x4_dst)
+; LA64-LARGE-NEXT: addi.d $a1, $zero, %pc_lo12(g_i32x4_dst)
+; LA64-LARGE-NEXT: lu32i.d $a1, %pc64_lo20(g_i32x4_dst)
+; LA64-LARGE-NEXT: lu52i.d $a1, $a1, %pc64_hi12(g_i32x4_dst)
+; LA64-LARGE-NEXT: add.d $a0, $a1, $a0
+; LA64-LARGE-NEXT: xvst $xr0, $a0, 0
+; LA64-LARGE-NEXT: ret
+entry:
+ %0 = load <8 x i32>, ptr @g_i32x4_src, align 32
+ store <8 x i32> %0, ptr @g_i32x4_dst, align 32
+ ret void
+}
+
+ at g_i8x16 = dso_local global <16 x i8> zeroinitializer, align 16
+
+define void @copy_i8_to_i8x16() {
+; LA32-LABEL: copy_i8_to_i8x16:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: pcalau12i $a0, %pc_hi20(g_i8)
+; LA32-NEXT: addi.w $a0, $a0, %pc_lo12(g_i8)
+; LA32-NEXT: vldrepl.b $vr0, $a0, 0
+; LA32-NEXT: pcalau12i $a0, %pc_hi20(g_i8x16)
+; LA32-NEXT: addi.w $a0, $a0, %pc_lo12(g_i8x16)
+; LA32-NEXT: vst $vr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: copy_i8_to_i8x16:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: pcalau12i $a0, %pc_hi20(g_i8)
+; LA64-NEXT: addi.d $a0, $a0, %pc_lo12(g_i8)
+; LA64-NEXT: vldrepl.b $vr0, $a0, 0
+; LA64-NEXT: pcalau12i $a0, %pc_hi20(g_i8x16)
+; LA64-NEXT: addi.d $a0, $a0, %pc_lo12(g_i8x16)
+; LA64-NEXT: vst $vr0, $a0, 0
+; LA64-NEXT: ret
+;
+; LA64-LARGE-LABEL: copy_i8_to_i8x16:
+; LA64-LARGE: # %bb.0: # %entry
+; LA64-LARGE-NEXT: pcalau12i $a0, %pc_hi20(g_i8)
+; LA64-LARGE-NEXT: addi.d $a1, $zero, %pc_lo12(g_i8)
+; LA64-LARGE-NEXT: lu32i.d $a1, %pc64_lo20(g_i8)
+; LA64-LARGE-NEXT: lu52i.d $a1, $a1, %pc64_hi12(g_i8)
+; LA64-LARGE-NEXT: add.d $a0, $a1, $a0
+; LA64-LARGE-NEXT: vldrepl.b $vr0, $a0, 0
+; LA64-LARGE-NEXT: pcalau12i $a0, %pc_hi20(g_i8x16)
+; LA64-LARGE-NEXT: addi.d $a1, $zero, %pc_lo12(g_i8x16)
+; LA64-LARGE-NEXT: lu32i.d $a1, %pc64_lo20(g_i8x16)
+; LA64-LARGE-NEXT: lu52i.d $a1, $a1, %pc64_hi12(g_i8x16)
+; LA64-LARGE-NEXT: add.d $a0, $a1, $a0
+; LA64-LARGE-NEXT: vst $vr0, $a0, 0
+; LA64-LARGE-NEXT: ret
+entry:
+ %0 = call <16 x i8> @llvm.loongarch.lsx.vldrepl.b(ptr @g_i8, i32 0)
+ store <16 x i8> %0, ptr @g_i8x16, align 16
+ ret void
+}
+
+ at g_i8x32 = dso_local global <32 x i8> zeroinitializer, align 32
+
+define void @copy_i8_to_i8x32() {
+; LA32-LABEL: copy_i8_to_i8x32:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: pcalau12i $a0, %pc_hi20(g_i8)
+; LA32-NEXT: addi.w $a0, $a0, %pc_lo12(g_i8)
+; LA32-NEXT: xvldrepl.b $xr0, $a0, 0
+; LA32-NEXT: pcalau12i $a0, %pc_hi20(g_i8x32)
+; LA32-NEXT: addi.w $a0, $a0, %pc_lo12(g_i8x32)
+; LA32-NEXT: xvst $xr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: copy_i8_to_i8x32:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: pcalau12i $a0, %pc_hi20(g_i8)
+; LA64-NEXT: addi.d $a0, $a0, %pc_lo12(g_i8)
+; LA64-NEXT: xvldrepl.b $xr0, $a0, 0
+; LA64-NEXT: pcalau12i $a0, %pc_hi20(g_i8x32)
+; LA64-NEXT: addi.d $a0, $a0, %pc_lo12(g_i8x32)
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
+;
+; LA64-LARGE-LABEL: copy_i8_to_i8x32:
+; LA64-LARGE: # %bb.0: # %entry
+; LA64-LARGE-NEXT: pcalau12i $a0, %pc_hi20(g_i8)
+; LA64-LARGE-NEXT: addi.d $a1, $zero, %pc_lo12(g_i8)
+; LA64-LARGE-NEXT: lu32i.d $a1, %pc64_lo20(g_i8)
+; LA64-LARGE-NEXT: lu52i.d $a1, $a1, %pc64_hi12(g_i8)
+; LA64-LARGE-NEXT: add.d $a0, $a1, $a0
+; LA64-LARGE-NEXT: xvldrepl.b $xr0, $a0, 0
+; LA64-LARGE-NEXT: pcalau12i $a0, %pc_hi20(g_i8x32)
+; LA64-LARGE-NEXT: addi.d $a1, $zero, %pc_lo12(g_i8x32)
+; LA64-LARGE-NEXT: lu32i.d $a1, %pc64_lo20(g_i8x32)
+; LA64-LARGE-NEXT: lu52i.d $a1, $a1, %pc64_hi12(g_i8x32)
+; LA64-LARGE-NEXT: add.d $a0, $a1, $a0
+; LA64-LARGE-NEXT: xvst $xr0, $a0, 0
+; LA64-LARGE-NEXT: ret
+entry:
+ %0 = call <32 x i8> @llvm.loongarch.lasx.xvldrepl.b(ptr @g_i8, i32 0)
+ store <32 x i8> %0, ptr @g_i8x32, align 32
+ ret void
+}
+
@g_rmw = dso_local global i64 0
define dso_local void @rmw() nounwind {
@@ -659,11 +834,11 @@ define dso_local void @control_flow_with_mem_access() nounwind {
; LA32-NEXT: pcalau12i $a0, %pc_hi20(g_a32+4)
; LA32-NEXT: ld.w $a1, $a0, %pc_lo12(g_a32+4)
; LA32-NEXT: ori $a2, $zero, 1
-; LA32-NEXT: blt $a1, $a2, .LBB21_2
+; LA32-NEXT: blt $a1, $a2, .LBB25_2
; LA32-NEXT: # %bb.1: # %if.then
; LA32-NEXT: ori $a1, $zero, 10
; LA32-NEXT: st.w $a1, $a0, %pc_lo12(g_a32+4)
-; LA32-NEXT: .LBB21_2: # %if.end
+; LA32-NEXT: .LBB25_2: # %if.end
; LA32-NEXT: ret
;
; LA64-LABEL: control_flow_with_mem_access:
@@ -671,11 +846,11 @@ define dso_local void @control_flow_with_mem_access() nounwind {
; LA64-NEXT: pcalau12i $a0, %pc_hi20(g_a32+4)
; LA64-NEXT: ld.w $a1, $a0, %pc_lo12(g_a32+4)
; LA64-NEXT: ori $a2, $zero, 1
-; LA64-NEXT: blt $a1, $a2, .LBB21_2
+; LA64-NEXT: blt $a1, $a2, .LBB25_2
; LA64-NEXT: # %bb.1: # %if.then
; LA64-NEXT: ori $a1, $zero, 10
; LA64-NEXT: st.w $a1, $a0, %pc_lo12(g_a32+4)
-; LA64-NEXT: .LBB21_2: # %if.end
+; LA64-NEXT: .LBB25_2: # %if.end
; LA64-NEXT: ret
;
; LA64-LARGE-LABEL: control_flow_with_mem_access:
@@ -686,7 +861,7 @@ define dso_local void @control_flow_with_mem_access() nounwind {
; LA64-LARGE-NEXT: lu52i.d $a1, $a1, %pc64_hi12(g_a32+4)
; LA64-LARGE-NEXT: ldx.w $a0, $a1, $a0
; LA64-LARGE-NEXT: ori $a1, $zero, 1
-; LA64-LARGE-NEXT: blt $a0, $a1, .LBB21_2
+; LA64-LARGE-NEXT: blt $a0, $a1, .LBB25_2
; LA64-LARGE-NEXT: # %bb.1: # %if.then
; LA64-LARGE-NEXT: pcalau12i $a0, %pc_hi20(g_a32+4)
; LA64-LARGE-NEXT: addi.d $a1, $zero, %pc_lo12(g_a32+4)
@@ -694,7 +869,7 @@ define dso_local void @control_flow_with_mem_access() nounwind {
; LA64-LARGE-NEXT: lu52i.d $a1, $a1, %pc64_hi12(g_a32+4)
; LA64-LARGE-NEXT: ori $a2, $zero, 10
; LA64-LARGE-NEXT: stx.w $a2, $a1, $a0
-; LA64-LARGE-NEXT: .LBB21_2: # %if.end
+; LA64-LARGE-NEXT: .LBB25_2: # %if.end
; LA64-LARGE-NEXT: ret
entry:
%0 = load i32, ptr getelementptr inbounds ([1 x i32], ptr @g_a32, i32 1), align 4
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