[llvm] [RISCV] Narrow indices to e16 for LMUL > 1 when lowering vector_reverse (PR #104427)

[Pengcheng Wang via llvm-commits]

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@@ -10348,6 +10346,14 @@ SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,
     GatherOpc = RISCVISD::VRGATHEREI16_VV_VL;
   }
 
+  // At LMUL > 1, do the index computation in 16 bits to reduce register
+  // pressure.
+  if (IntVT.getScalarType().bitsGT(MVT::i16) && isUInt<16>(MaxVLMAX - 1) &&
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wangpc-pp wrote:

> lagest VLMAX of 65,536 occurs for LMUL=8 and SEW=8 with VLEN=65,536

According to spec, we don't need `isUInt<16>(MaxVLMAX - 1)` here.

https://github.com/llvm/llvm-project/pull/104427